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Mon, 14 Jun 2021 16:33:04 +0000 From: Biju Das To: Laurent Pinchart CC: Geert Uytterhoeven , Vinod Koul , Rob Herring , Chris Brandt , dmaengine , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Chris Paterson , Prabhakar Mahadev Lad , Linux-Renesas Subject: RE: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings Thread-Topic: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings Thread-Index: AQHXXrYS1Y35K9bUV02GRKgFCWvED6sTb4CAgAAIHiCAAB5YgIAAGraggAADZICAAABasIAAAroAgAAAsKA= Date: Mon, 14 Jun 2021 16:33:03 +0000 Message-ID: References: <20210611113642.18457-1-biju.das.jz@bp.renesas.com> <20210611113642.18457-2-biju.das.jz@bp.renesas.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: ideasonboard.com; dkim=none (message not signed) header.d=none;ideasonboard.com; dmarc=none action=none header.from=bp.renesas.com; x-originating-ip: [193.141.219.20] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 079ff8d9-5106-408e-11a4-08d92f521552 x-ms-traffictypediagnostic: OSAPR01MB5153: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OS0PR01MB5922.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 079ff8d9-5106-408e-11a4-08d92f521552 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Jun 2021 16:33:03.9138 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rqhrEXni4Hj340jxpqWMdTyGSePDcKvRUZuT17LuvJH4P978hL9gWJgIIB8H0HKLBlMpzXgUZaiF9RGQ5GrDSvZYcnRfS6GlCcOGW5MKR+g= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSAPR01MB5153 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Hi Laurent, > Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings >=20 > Hi Biju, >=20 > On Mon, Jun 14, 2021 at 04:24:38PM +0000, Biju Das wrote: > > > On Mon, Jun 14, 2021 at 04:09:04PM +0000, Biju Das wrote: > > > > > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote: > > > > > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das wrote: > > > > > > > > Document RZ/G2L DMAC bindings. > > > > > > > > > > > > > > > > Signed-off-by: Biju Das > > > > > > > > Reviewed-by: Lad Prabhakar > > > > > > > > > > > > > > > > > > > > > > Thanks for your patch! > > > > > > > > > > > > > > > --- /dev/null > > > > > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dma > > > > > > > > +++ c.ya > > > > > > > > +++ ml > > > > > > > > @@ -0,0 +1,132 @@ > > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > > > > +%YAML > > > > > > > > +1.2 > > > > > > > > +--- > > > > > > > > +$id: > > > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=3Dhttp= % > > > > > > > > +3A%2 > > > > > > > > +F%2F > > > > > > > > +devi > > > > > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&am > > > > > > > > +p;da > > > > > > > > +ta=3D0 > > > > > > > > +4%7C > > > > > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d850 > > > > > > > > +8d92 > > > > > > > > +f2da > > > > > > > > +0c0% > > > > > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286 > > > > > > > > +8468 > > > > > > > > +09%7 > > > > > > > > +CUnk > > > > > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLC > > > > > > > > +JBTi > > > > > > > > +I6Ik > > > > > > > > +1haW > > > > > > > > +wiLCJXVCI6Mn0%3D%7C1000&sdata=3D5Jh%2FxPaia5ZOY0CrViQC= c > > > > > > > > +rNtz > > > > > > > > +uDej > > > > > > > > +p8wo > > > > > > > > +Nrx9iO0ht8%3D&reserved=3D0 > > > > > > > > +$schema: > > > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=3Dhttp= % > > > > > > > > +3A%2 > > > > > > > > +F%2F > > > > > > > > +devi > > > > > > > > +cetree.org%2Fmeta- > > > > > schemas%2Fcore.yaml%23&data=3D04%7C01%7Cbiju.das. > > > > > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C > > > > > > > > +53d8 > > > > > > > > +2571 > > > > > > > > +da19 > > > > > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnkno > > > > > > > > +wn%7 > > > > > > > > +CTWF > > > > > > > > +pbGZ > > > > > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi > > > > > > > > +LCJX > > > > > > > > +VCI6 > > > > > > > > +Mn0% > > > > > > > > +3D%7C1000&sdata=3D5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRI= A > > > > > > > > +dLnh > > > > > > > > +Jraw > > > > > > > > +%3D& > > > > > > > > +amp;reserved=3D0 > > > > > > > > > > *sigh* > > > > > > > > > > > > > + > > > > > > > > +title: Renesas RZ/G2L DMA Controller > > > > > > > > + > > > > > > > > +maintainers: > > > > > > > > + - Biju Das > > > > > > > > + > > > > > > > > +allOf: > > > > > > > > + - $ref: "dma-controller.yaml#" > > > > > > > > + > > > > > > > > +properties: > > > > > > > > + compatible: > > > > > > > > + items: > > > > > > > > + - enum: > > > > > > > > + - renesas,dmac-r9a07g044 # RZ/G2{L,LC} > > > > > > > > > > > > > > Please use "renesas,r9a07g044-dmac". > > > > > > > > > > > > OK. Will change. > > > > > > > > > > > > > > + - const: renesas,rz-dmac > > > > > > > > > > > > > > Does this need many changes for RZ/A1H and RZ/A2M? > > > > > > > > > > > > It will work on both RZ/A1H and RZ/A2M. I have n't tested since > I don't have the board. > > > > > > There is some difference in MID bit size. Other wise both > identical. > > > > > > > > > > > > > > + renesas,rz-dmac-slavecfg: > > > > > > > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > > > > > > > + description: | > > > > > > > > + DMA configuration for a slave channel. Each channel > > > > > > > > + must have an array of > > > > > > > > + 3 items as below. > > > > > > > > + first item in the array is MID+RID > > > > > > > > > > > > > > Already in dmas. > > > > > > > > > > > > > > > + second item in the array is slave src or dst > > > > > > > > + address > > > > > > > > > > > > > > As pointed out by Rob, already known by the slave driver. > > > > > > > > > > > > > > > + third item in the array is channel configuration > value. > > > > > > > > > > > > > > What exactly is this? > > > > > > > > > > What would prevent the DMA client from passing the configuration > > > > > to the DMA channel through the DMA engine API, just like it > > > > > passes the slave source or destination address ? > > > > > > > > On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both > tx and rx. > > > > The only way we can distinguish it is from channel configuration > value. > > > > > > Are those two different hardware DMA channels ? And configuration > > > values change between the two ? > > > > Yes, REQD is different, apart from this Rx have transfer source and Tx > have Transfer destination. > > This particular SSIF ch2 is used only for half duplex compared to other > SSIF channels. >=20 > Does this mean there's a single DMA channel, used by two clients, but not > at the same time as it only supports half-duplex ? >From hardware perspective, it is 2 channel. For eg:- playback/recording use= case. You cannot do simultaneous playback, but you can do playback or record sepa= rately. Cheers, Biju > > > > > > > Does the R-Car DMAC have this too? If yes, how does its > > > > > > > driver handle it? > > > > > > > > > > > > On R-CAR DMAC, we have only MID + RID values. Where as here we > > > > > > have channel configuration value With different set of > > > > > > parameter as mentioned in Table 16.4. > > > > > > > > > > > > Please see Page 569, Table 16.4 On-Chip Module requests section= . > > > > > > > > > > > > For eg:- as per Rob's suggestion, I have modelled the driver > > > > > > with the below entries in ALSA driver for playback/record use > case. > > > > > > > > > > > > dmas =3D <&dmac 0x255 0x10049c18 > CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>, > > > > > > <&dmac 0x256 0x10049c1c > > > > > > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>; > > > > > > dma-names =3D "tx", "rx"; > > > > > > > > > > > > Using first parameter, it gets dmac channel. using second and > > > > > > third parameter it configures the channel. >=20 > -- > Regards, >=20 > Laurent Pinchart