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x-ms-exchange-antispam-messagedata: DTWZGAtScX5rUh0mBIsbm9C7HUbqhs4RaoCxLNPOElDZdH6sz7slct+VVTNAMirBDaZPJZzmqS/2mbYfuBUPe3lCEA4jB0XGczw+eilFCOA2RB+bjWWh44gq7HyRXuIXRDw/Uu6yqkIlpxPtnkACtY7Xs48VFK/rHQU30eNzFdSbULIK7qA+pXLOKcUDNjzkch8O5yEnaQ+yiAYjAUlYCmf15HgKQ8UUQgCb1CDrLDJzaBBLz7URDyKP0Q0G6YkYWBM9HEWuZBxB9XVbAXfqX2kvL1wcp8u45h/qOcCuFqrLfb5kJCSH0uFzX7S/48EzXMP2vMK4tIO04DLKVuzQtFuWWE/BVxKwP8zpP0lM6LqJ83YYwACfSQcOx+zheh8tjPkT1OCw7B/0TZvx4snISG27mj45covTeD/mEDeWJB90eZk9OEsoNKD9Vv2rqbWq2lEEYAgF2p8EPcBW007qqP5pgdIXzR0eWchZsP0zHd0= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VE1PR04MB6638.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 43b7d7da-1d0c-4d6c-4e9a-08d82fba3d5e X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Jul 2020 10:13:41.1169 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: yQ923lzmJLn9ZofjqoU6ncIIJvnvx6mG22/VGn1MUIVWhN8JEzppQnNovLydmIWv5e4Wu5SqTcBlkOGJLXCGOw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6640 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On 2020/07/17 3:48 Rob Herring wrote: > > + > > + reg: > > + minItems: 2 > > + maxItems: 32 >=20 > Needs some sort of description as to what each region is. Okay, will add it in v3. >=20 > > + > > + interrupts: > > + minItems: 2 > > + maxItems: 32 >=20 > ditto Will add it in v3. >=20 > > + > > + interrupt-names: > > + minItems: 2 > > + maxItems: 32 > > + items: > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$" >=20 > What about interrupts 8-31? If you want a pattern for all entries, you Here 8 lines matches with the 8 channel used in dts (same example as the bottom of this yaml file below), otherwise, below warning comes out with 'make dt_binding_check' if I remove the above last line: dma-controller@5a1f0000: interrupt-names: Additional items are not allowed = ('edma2-chan15-tx' was unexpected) Maybe there something I miss, please correct me if I'm wrong, thanks. > do: >=20 > items: > pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$" >=20 > (If 'items' is a schema instead of a list, then it applies to all > entries.) >=20 > What does edma[0-2] correspond to? The names should be local to the > instance. There are 3 edma controllers on i.mx8QXP/QM, [0-2] is controller index. Clear controller index here may make dts readable since every edma channel has unique register map, interrupt number, power domain. >=20 > Really, what's the point of names that just have the channel number in th= em? > The driver can create names dynamically if needed. We already have > properties to define how many channels and a mask of present channels. interrupt-names/power-domain-names here just for better readable in dts, be= sides, the clear interrupt name for every channel including edma controller id which passed by dts could be used to register irq. >=20 > > + > > + '#dma-cells': > > + const: 3 > > + description: | > > + The 1st cell specifies the channel ID. > > + > > + The 2nd cell specifies the channel priority. > > + > > + The 3rd cell specifies the channel attributes: > > + bit0 transmit or receive. > > + 0 =3D transmit > > + 1 =3D receive > > + bit1 local or remote access. > > + 0 =3D local > > + 1 =3D remote > > + bit2 dualfifo case or not(only in Audio cyclic now). > > + 0 =3D not dual fifo case > > + 1 =3D dualfifo case. > > + > > + dma-channels: > > + minimum: 2 > > + maximum: 32 > > + > > + power-domains: > > + minItems: 2 > > + maxItems: 32 > > + > > + power-domain-names: > > + minItems: 2 > > + maxItems: 32 > > + items: > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$" > > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$" >=20 > Again, why do you need names here? >=20 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - interrupt-names > > + - '#dma-cells' > > + - dma-channels > > + - power-domains > > + - power-domain-names > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + #include > > + > > + edma2: dma-controller@5a1f0000 { > > + compatible =3D "fsl,imx8qm-edma"; > > + reg =3D <0x5a280000 0x10000>, /* channel8 UART0 rx */ > > + <0x5a290000 0x10000>, /* channel9 UART0 tx */ > > + <0x5a2a0000 0x10000>, /* channel10 UART1 rx */ > > + <0x5a2b0000 0x10000>, /* channel11 UART1 tx */ > > + <0x5a2c0000 0x10000>, /* channel12 UART2 rx */ > > + <0x5a2d0000 0x10000>, /* channel13 UART2 tx */ > > + <0x5a2e0000 0x10000>, /* channel14 UART3 rx */ > > + <0x5a2f0000 0x10000>; /* channel15 UART3 tx */ > > + #dma-cells =3D <3>; > > + dma-channels =3D <8>; > > + interrupts =3D , > > + , > > + , > > + , > > + , > > + , > > + , > > + ; > > + interrupt-names =3D "edma2-chan8-rx", "edma2-chan9-tx", > > + "edma2-chan10-rx", "edma2-chan11-tx", > > + "edma2-chan12-rx", "edma2-chan13-tx", > > + "edma2-chan14-rx", "edma2-chan15-tx"; > > + power-domains =3D <&pd IMX_SC_R_DMA_2_CH8>, > > + <&pd IMX_SC_R_DMA_2_CH9>, > > + <&pd IMX_SC_R_DMA_2_CH10>, > > + <&pd IMX_SC_R_DMA_2_CH11>, > > + <&pd IMX_SC_R_DMA_2_CH12>, > > + <&pd IMX_SC_R_DMA_2_CH13>, > > + <&pd IMX_SC_R_DMA_2_CH14>, > > + <&pd IMX_SC_R_DMA_2_CH15>; > > + power-domain-names =3D "edma2-chan8", "edma2-chan9", > > + "edma2-chan10", "edma2-chan11", > > + "edma2-chan12", "edma2-chan13", > > + "edma2-chan14", "edma2-chan15"; > > + }; > > -- > > 2.7.4 > >