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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: yZS4jewgwEvXTUfa231d4KcXmcNLL1B9wCSJ81T3FGVr+0M/rbLjzIiHbY/ITQP1zrEatK+YCPdQENe8AauqQmrY5Q/ZcC9lWDgCUujd+cHFwvR/Jp5rmUTt3W7et5DvD5WHa+KMqUlLRkoWqtuaCAQ0ljpLM714FIg8PTMY727zNIV7sQ+UZ55sORQLozvcdfK/si+CM7D6U2aiyVd0U9Em305zfyfEXwgZ6EmlFjghrNCzmoqVcC1Kmz2wUPxDze8wvI3K7Q6vzzTmGNshbG4YHZqmPIkaPhnvmPolhj8nny3r/DLqxccqGFM4q+3W0oOiSSrR4Fp0wSs8xTsSTi15R+cNC83/9co3CR+QrsP2uM0dPAAepbG8tyj8vmH+4XeO9A1sWZ1ti3OanvVFyDdIcA3ZTXulgQmnsdfLW24= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 703b991c-f674-4c44-1887-08d7567139a6 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Oct 2019 21:54:19.3734 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JkaM1WocWiHD5LUhPBLOzCE4OTwBglqQHHD4DT9/N/1rl1gpFwGuTRJHSiA+lGiBqTSTUky/P2sXoqd+vRy4mQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6766 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org > -----Original Message----- > From: Peng Ma > Sent: Sunday, October 20, 2019 9:22 PM > To: vkoul@kernel.org > Cc: dan.j.williams@intel.com; Leo Li ; > k.kozlowski.k@gmail.com; Fabio Estevam ; > dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org; Peng Ma > > Subject: [V2] dmaengine: fsl-edma: Add eDMA support for QorIQ LS1028A > platform >=20 > Our platforms(such as LS1021A, LS1012A, LS1043A, LS1046A, LS1028A) with > below You only covered QorIQ SoCs, how about the situation for IMX SoCs? > registers(CHCFG0 - CHCFG15) of eDMA as follows: > *-----------------------------------------------------------* > | Offset | OTHERS | LS1028A | > |--------------|--------------------|-----------------------| > | 0x0 | CHCFG0 | CHCFG3 | > |--------------|--------------------|-----------------------| > | 0x1 | CHCFG1 | CHCFG2 | > |--------------|--------------------|-----------------------| > | 0x2 | CHCFG2 | CHCFG1 | > |--------------|--------------------|-----------------------| > | 0x3 | CHCFG3 | CHCFG0 | > |--------------|--------------------|-----------------------| > | ... | ...... | ...... | > |--------------|--------------------|-----------------------| > | 0xC | CHCFG12 | CHCFG15 | > |--------------|--------------------|-----------------------| > | 0xD | CHCFG13 | CHCFG14 | > |--------------|--------------------|-----------------------| > | 0xE | CHCFG14 | CHCFG13 | > |--------------|--------------------|-----------------------| > | 0xF | CHCFG15 | CHCFG12 | > *-----------------------------------------------------------* >=20 > This patch is to improve edma driver to fit LS1028A platform. >=20 > Signed-off-by: Peng Ma > --- > Changed for V2: > - Explaining what's the "Our platforms" >=20 > drivers/dma/fsl-edma-common.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) >=20 > diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma- > common.c index b1a7ca9..611186b 100644 > --- a/drivers/dma/fsl-edma-common.c > +++ b/drivers/dma/fsl-edma-common.c > @@ -7,6 +7,7 @@ > #include > #include > #include > +#include >=20 > #include "fsl-edma-common.h" >=20 > @@ -42,6 +43,11 @@ >=20 > #define EDMA_TCD 0x1000 >=20 > +static struct soc_device_attribute soc_fixup_tuning[] =3D { > + { .family =3D "QorIQ LS1028A"}, > + { }, > +}; > + > static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) { > struct edma_regs *regs =3D &fsl_chan->edma->regs; @@ -109,10 > +115,16 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, > u32 ch =3D fsl_chan->vchan.chan.chan_id; > void __iomem *muxaddr; > unsigned int chans_per_mux, ch_off; > + int endian_diff[4] =3D {3, 1, -1, -3}; > u32 dmamux_nr =3D fsl_chan->edma->drvdata->dmamuxs; >=20 > chans_per_mux =3D fsl_chan->edma->n_chans / dmamux_nr; > ch_off =3D fsl_chan->vchan.chan.chan_id % chans_per_mux; > + > + if (!fsl_chan->edma->big_endian && > + soc_device_match(soc_fixup_tuning)) > + ch_off +=3D endian_diff[ch_off % 4]; > + This probably is not the best fix now. There is a new mux_configure32() AP= I added but it doesn't consider endianness. How about making it properly t= aken care of endianness? And use it to set these registers? > muxaddr =3D fsl_chan->edma->muxbase[ch / chans_per_mux]; > slot =3D EDMAMUX_CHCFG_SOURCE(slot); >=20 > -- > 2.9.5