From: Vinod Koul <vkoul@kernel.org>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Chris Paterson <Chris.Paterson2@renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
"dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
Chris Brandt <Chris.Brandt@renesas.com>,
"linux-renesas-soc@vger.kernel.org"
<linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH v4 2/4] drivers: dma: sh: Add DMAC driver for RZ/G2L SoC
Date: Wed, 28 Jul 2021 16:35:07 +0530 [thread overview]
Message-ID: <YQE542kiEGcYCCFO@matsya> (raw)
In-Reply-To: <OS0PR01MB59228D6F0AD7A51DAFFB512A86EA9@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Hi Biju,
On 28-07-21, 07:00, Biju Das wrote:
> >
> > Sorry I dont like passing numbers like this :(
> >
> > Can you explain what is meant by each of the above values and looks like
> > some (if not all) can be derived (slave config as well as transaction
> > properties)
>
>
> 0x11228 (Tx)
> 0x11220 (Rx)
>
> BIT 22:- TM :- Transfer Mode
What are the values, here it seems 0
> Bits 16->19 :- DDS(Destination Data Size) --> 0x0001 (16 bits)
> Bits 12->15 :- SDS(Source Data size)--> 0x0001 (16 bits)
use src_addr_width/dst_addr_width ..?
> Bit 11 :- Reserved
> Bits 8->10 :- Ack mode --> 0x010 (Bus cycle mode)
What does this mean?
> Bit 7 :- Reserved
> Bit 6:- LVL --> Level -->0 (DMA request based on edge of thesignal)
> Bit 5:- HIEN --> High Enable --> 1 (Detects a DMA request on rising edge of the signal)
> Bit 4:- LOEN --> Low Enable -->0 (Does not DMA request on falling edge of the signal)
> Bit 3:- REQD --> Request Direction ->1 (DMAREQ is Destination)
how and what decides these values
It is now hardcoded in the client driver, can we do that in dma driver
instead? While deriving most of the values?
--
~Vinod
next prev parent reply other threads:[~2021-07-28 11:05 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-19 9:25 [PATCH v4 0/4] Add RZ/G2L DMAC support Biju Das
2021-07-19 9:25 ` [PATCH v4 2/4] drivers: dma: sh: Add DMAC driver for RZ/G2L SoC Biju Das
2021-07-27 7:56 ` Biju Das
2021-07-27 12:40 ` Vinod Koul
2021-07-27 13:45 ` Biju Das
2021-07-28 6:20 ` Vinod Koul
2021-07-28 7:00 ` Biju Das
2021-07-28 11:05 ` Vinod Koul [this message]
2021-07-28 11:58 ` Biju Das
2021-07-28 12:34 ` Geert Uytterhoeven
2021-07-28 12:42 ` Biju Das
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