From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: linux-renesas-soc@vger.kernel.org,
Magnus Damm <magnus.damm@gmail.com>,
Gareth Williams <gareth.williams.jx@renesas.com>,
Phil Edworthy <phil.edworthy@renesas.com>,
Geert Uytterhoeven <geert@linux-m68k.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
linux-clk@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, Viresh Kumar <vireshk@kernel.org>,
Vinod Koul <vkoul@kernel.org>,
dmaengine@vger.kernel.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Milan Stevanovic <milan.stevanovic@se.com>,
Jimmy Lalande <jimmy.lalande@se.com>,
Pascal Eberhard <pascal.eberhard@se.com>,
Herve Codina <herve.codina@bootlin.com>,
Clement Leger <clement.leger@bootlin.com>
Subject: Re: [PATCH v4 5/9] dma: dw: dmamux: Introduce RZN1 DMA router support
Date: Thu, 10 Mar 2022 19:44:13 +0200 [thread overview]
Message-ID: <Yio47YVZuHaFvwE8@smile.fi.intel.com> (raw)
In-Reply-To: <20220310155755.287294-6-miquel.raynal@bootlin.com>
On Thu, Mar 10, 2022 at 04:57:51PM +0100, Miquel Raynal wrote:
> The Renesas RZN1 DMA IP is based on a DW core, with eg. an additional
> dmamux register located in the system control area which can take up to
> 32 requests (16 per DMA controller). Each DMA channel can be wired to
> two different peripherals.
>
> We need two additional information from the 'dmas' property: the channel
> (bit in the dmamux register) that must be accessed and the value of the
> mux for this channel.
>
> Aside from the driver introduction, as these devices are described as
> subnodes of the system controller, we also need the system controller
> (clock) driver to populate its children manually. Starting from now on,
> one child can be the dmamux.
In all DMA engine related patches the prefix should be "dmaengine:".
...
> +static void *rzn1_dmamux_route_allocate(struct of_phandle_args *dma_spec,
> + struct of_dma *ofdma)
> +{
> + struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
> + struct rzn1_dmamux_data *dmamux = platform_get_drvdata(pdev);
> + struct rzn1_dmamux_map *map;
> + unsigned int dmac_idx, chan, val;
> + u32 mask;
> + int ret;
> +
> + map = kzalloc(sizeof(*map), GFP_KERNEL);
> + if (!map)
> + return ERR_PTR(-ENOMEM);
> + if (dma_spec->args_count != 6) {
> + kfree(map);
> + return ERR_PTR(-EINVAL);
> + }
You may move this check above and get one kfree() call less.
Moreover, you may use a goto approach to call kfree() from
a single point of exit.
> + chan = dma_spec->args[0];
> + map->req_idx = dma_spec->args[4];
> + val = dma_spec->args[5];
> + dma_spec->args_count -= 2;
> +
> + if (chan >= RZN1_DMAMUX_SPLIT) {
> + kfree(map);
> + dev_err(&pdev->dev, "Invalid DMA request line: %u\n", chan);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + if (map->req_idx >= RZN1_DMAMUX_LINES ||
> + (map->req_idx % RZN1_DMAMUX_SPLIT) != chan) {
> + kfree(map);
> + dev_err(&pdev->dev, "Invalid MUX request line: %u\n", map->req_idx);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + dmac_idx = map->req_idx < RZN1_DMAMUX_SPLIT ? 0 : 1;
> + dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", dmac_idx);
> + if (!dma_spec->np) {
> + kfree(map);
> + dev_err(&pdev->dev, "Can't get DMA master\n");
> + return ERR_PTR(-EINVAL);
> + }
> +
> + dev_dbg(&pdev->dev, "Mapping DMAMUX request %u to DMAC%u request %u\n",
> + map->req_idx, dmac_idx, chan);
> +
> + mask = BIT(map->req_idx);
> + mutex_lock(&dmamux->lock);
> + dmamux->used_chans |= mask;
> + ret = r9a06g032_sysctrl_set_dmamux(mask, val ? mask : 0);
> + mutex_unlock(&dmamux->lock);
> + if (ret) {
> + rzn1_dmamux_free(&pdev->dev, map);
> + return ERR_PTR(ret);
> + }
> +
> + return map;
> +}
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2022-03-10 17:45 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-10 15:57 [PATCH v4 0/9] RZN1 DMA support Miquel Raynal
2022-03-10 15:57 ` [PATCH v4 1/9] dt-bindings: dma: Introduce RZN1 dmamux bindings Miquel Raynal
2022-03-11 15:27 ` Rob Herring
2022-03-10 15:57 ` [PATCH v4 2/9] dt-bindings: clock: r9a06g032-sysctrl: Reference the DMAMUX subnode Miquel Raynal
2022-03-11 15:28 ` Rob Herring
2022-03-10 15:57 ` [PATCH v4 3/9] dt-bindings: dma: Introduce RZN1 DMA compatible Miquel Raynal
2022-03-10 15:57 ` [PATCH v4 4/9] soc: renesas: rzn1-sysc: Export function to set dmamux Miquel Raynal
2022-03-10 15:57 ` [PATCH v4 5/9] dma: dw: dmamux: Introduce RZN1 DMA router support Miquel Raynal
2022-03-10 17:44 ` Andy Shevchenko [this message]
2022-03-11 10:23 ` Vinod Koul
2022-03-10 15:57 ` [PATCH v4 6/9] dma: dw: Add RZN1 compatible Miquel Raynal
2022-03-10 15:57 ` [PATCH v4 7/9] dma: dw: Avoid partial transfers Miquel Raynal
2022-03-10 17:50 ` Andy Shevchenko
2022-03-10 18:46 ` Miquel Raynal
2022-03-11 11:24 ` Ilpo Järvinen
2022-03-10 15:57 ` [PATCH v4 8/9] ARM: dts: r9a06g032: Add the two DMA nodes Miquel Raynal
2022-03-10 15:57 ` [PATCH v4 9/9] ARM: dts: r9a06g032: Describe the DMA router Miquel Raynal
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