From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: dma: tegra: add accurate reporting of dma state From: Ben Dooks Message-Id: Date: Wed, 1 May 2019 09:58:37 +0100 To: Dmitry Osipenko , linux-kernel@lists.codethink.co.uk Cc: Laxman Dewangan , Jon Hunter , Vinod Koul , Dan Williams , Thierry Reding , dmaengine@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org List-ID: T24gMjQvMDQvMjAxOSAxOToxNywgRG1pdHJ5IE9zaXBlbmtvIHdyb3RlOgo+IDI0LjA0LjIwMTkg MTk6MjMsIEJlbiBEb29rcyDQv9C40YjQtdGCOgo+PiBUaGUgdHhfc3RhdHVzIGNhbGxiYWNrIGRv ZXMgbm90IHJlcG9ydCB0aGUgc3RhdGUgb2YgdGhlIHRyYW5zZmVyCj4+IGJleW9uZCBjb21wbGV0 ZSBzZWdtZW50cy4gVGhpcyBjYXVzZXMgcHJvYmxlbXMgd2l0aCB1c2VycyBzdWNoIGFzCj4+IEFM U0Egd2hlbiBhcHBsaWNhdGlvbnMgd2FudCB0byBrbm93IGFjY3VyYXRlbHkgaG93IG11Y2ggZGF0 YSBoYXMKPj4gYmVlbiBtb3ZlZC4KPj4KPj4gVGhpcyBwYXRjaCBhZGRlcyBhIGZ1bmN0aW9uIHRl Z3JhX2RtYV91cGRhdGVfcmVzaWR1YWwoKSB0byBxdWVyeQo+PiB0aGUgaGFyZHdhcmUgYW5kIG1v ZGlmeSB0aGUgcmVzaWR1YWwgaW5mb3JtYXRpb24gYWNjb3JkaW5seS4gSXQKPj4gdGFrZXMgaW50 byBhY2NvdW50IGFueSBoYXJkd2FyZSBpc3N1ZXMgd2hlbiB0cnlpbmcgdG8gcmVhZCB0aGUKPj4g c3RhdGUsIHN1Y2ggYXMgZGVsYXlzIGJldHdlZW4gZmluaXNoaW5nIGEgYnVmZmVyIGFuZCBzaWdu YWxsaW5nCj4+IHRoZSBpbnRlcnJ1cHQuCj4+Cj4+IFNpZ25lZC1vZmYtYnk6IEJlbiBEb29rcyA8 YmVuLmRvb2tzQGNvZGV0aGluay5jby51az4KPiAKPiBIZWxsbyBCZW4sCj4gCj4gVGhhbmsgeW91 IHZlcnkgbXVjaCBmb3Iga2VlcGluZyBpdCB1cC4gSSBoYXZlIGNvdXBsZSBjb21tZW50cywgcGxl YXNlIHNlZSB0aGVtIGJlbG93Lgo+IAo+PiBDYzogRG1pdHJ5IE9zaXBlbmtvIDxkaWdldHhAZ21h aWwuY29tPgo+PiBDYzogTGF4bWFuIERld2FuZ2FuIDxsZGV3YW5nYW5AbnZpZGlhLmNvbT4gKHN1 cHBvcnRlcjpURUdSQSBETUEgRFJJVkVSUykKPj4gQ2M6IEpvbiBIdW50ZXIgPGpvbmF0aGFuaEBu dmlkaWEuY29tPiAoc3VwcG9ydGVyOlRFR1JBIERNQSBEUklWRVJTKQo+PiBDYzogVmlub2QgS291 bCA8dmtvdWxAa2VybmVsLm9yZz4gKG1haW50YWluZXI6RE1BIEdFTkVSSUMgT0ZGTE9BRCBFTkdJ TkUgU1VCU1lTVEVNKQo+PiBDYzogRGFuIFdpbGxpYW1zIDxkYW4uai53aWxsaWFtc0BpbnRlbC5j b20+IChyZXZpZXdlcjpBU1lOQ0hST05PVVMgVFJBTlNGRVJTL1RSQU5TRk9STVMgKElPQVQpIEFQ SSkKPj4gQ2M6IFRoaWVycnkgUmVkaW5nIDx0aGllcnJ5LnJlZGluZ0BnbWFpbC5jb20+IChzdXBw b3J0ZXI6VEVHUkEgQVJDSElURUNUVVJFIFNVUFBPUlQpCj4+IENjOiBkbWFlbmdpbmVAdmdlci5r ZXJuZWwub3JnIChvcGVuIGxpc3Q6RE1BIEdFTkVSSUMgT0ZGTE9BRCBFTkdJTkUgU1VCU1lTVEVN KQo+PiBDYzogbGludXgtdGVncmFAdmdlci5rZXJuZWwub3JnIChvcGVuIGxpc3Q6VEVHUkEgQVJD SElURUNUVVJFIFNVUFBPUlQpCj4+IENjOiBsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIChv cGVuIGxpc3QpCj4+IC0tLQo+PiAgIGRyaXZlcnMvZG1hL3RlZ3JhMjAtYXBiLWRtYS5jIHwgOTIg KysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKystLS0KPj4gICAxIGZpbGUgY2hhbmdlZCwg ODYgaW5zZXJ0aW9ucygrKSwgNiBkZWxldGlvbnMoLSkKPj4KPj4gZGlmZiAtLWdpdCBhL2RyaXZl cnMvZG1hL3RlZ3JhMjAtYXBiLWRtYS5jIGIvZHJpdmVycy9kbWEvdGVncmEyMC1hcGItZG1hLmMK Pj4gaW5kZXggY2Y0NjJiMWFiYzBiLi41NDRlNzI3M2U3NDEgMTAwNjQ0Cj4+IC0tLSBhL2RyaXZl cnMvZG1hL3RlZ3JhMjAtYXBiLWRtYS5jCj4+ICsrKyBiL2RyaXZlcnMvZG1hL3RlZ3JhMjAtYXBi LWRtYS5jCj4+IEBAIC04MDgsNiArODA4LDkwIEBAIHN0YXRpYyBpbnQgdGVncmFfZG1hX3Rlcm1p bmF0ZV9hbGwoc3RydWN0IGRtYV9jaGFuICpkYykKPj4gICAJcmV0dXJuIDA7Cj4+ICAgfQo+PiAg IAo+PiArc3RhdGljIHVuc2lnbmVkIGludCB0ZWdyYV9kbWFfdXBkYXRlX3Jlc2lkdWFsKHN0cnVj dCB0ZWdyYV9kbWFfY2hhbm5lbCAqdGRjLAo+PiArCQkJCQkgICAgICBzdHJ1Y3QgdGVncmFfZG1h X3NnX3JlcSAqc2dfcmVxLAo+PiArCQkJCQkgICAgICBzdHJ1Y3QgdGVncmFfZG1hX2Rlc2MgKmRt YV9kZXNjLAo+PiArCQkJCQkgICAgICB1bnNpZ25lZCBpbnQgcmVzaWR1YWwpCj4+ICt7Cj4+ICsJ dW5zaWduZWQgbG9uZyBzdGF0dXMgPSAweDA7Cj4+ICsJdW5zaWduZWQgbG9uZyB3Y291bnQ7Cj4+ ICsJdW5zaWduZWQgbG9uZyBhaGJwdHI7Cj4+ICsJdW5zaWduZWQgbG9uZyB0bXAgPSAweDA7Cj4+ ICsJdW5zaWduZWQgaW50IHJlc3VsdDsKPiAKPiBZb3UgY291bGQgcHJlLWFzc2lnbiBhaGJwdHI9 MHhmZmZmZmZmZiBhbmQgcmVzdWx0PXJlc2lkdWFsIGhlcmUsIHRoZW4geW91IGNvdWxkIHJlbW92 ZSBhbGwgdGhlIGR1cGxpY2F0ZWQgYXNzaWducyBiZWxvdy4KCm9rLCB0YS4KCj4+ICsJaW50IHJl dHJpZXMgPSBURUdSQV9BUEJETUFfQlVSU1RfQ09NUExFVEVfVElNRSAqIDEwOwo+PiArCWludCBk b25lOwo+PiArCj4+ICsJLyogaWYgd2UncmUgbm90IHRoZSBjdXJyZW50IHJlcXVlc3QsIHRoZW4g ZG9uJ3QgYWx0ZXIgdGhlIHJlc2lkdWFsICovCj4+ICsJaWYgKHNnX3JlcSAhPSBsaXN0X2ZpcnN0 X2VudHJ5KCZ0ZGMtPnBlbmRpbmdfc2dfcmVxLAo+PiArCQkJCSAgICAgICBzdHJ1Y3QgdGVncmFf ZG1hX3NnX3JlcSwgbm9kZSkpIHsKPj4gKwkJcmVzdWx0ID0gcmVzaWR1YWw7Cj4+ICsJCWFoYnB0 ciA9IDB4ZmZmZmZmZmY7Cj4+ICsJCWdvdG8gZG9uZTsKPj4gKwl9Cj4+ICsKPj4gKwkvKiBsb29w IHVudGlsIHdlIGhhdmUgYSByZWxpYWJsZSByZXN1bHQgZm9yIHJlc2lkdWFsICovCj4+ICsJZG8g ewo+PiArCQlhaGJwdHIgPSB0ZGNfcmVhZCh0ZGMsIFRFR1JBX0FQQkRNQV9DSEFOX0FIQlBUUik7 Cj4+ICsJCXN0YXR1cyA9IHRkY19yZWFkKHRkYywgVEVHUkFfQVBCRE1BX0NIQU5fU1RBVFVTKTsK Pj4gKwkJdG1wID0gIHRkY19yZWFkKHRkYywgMHgwOCk7CS8qIHRvdGFsIGNvdW50IGZvciBkZWJ1 ZyAqLwo+IAo+IFRoZSAidG1wIiB2YXJpYWJsZSBpc24ndCB1c2VkIGFueXdoZXJlIGluIHRoZSBj b2RlLCBwbGVhc2UgcmVtb3ZlIGl0LgoKbXVzdCBoYXZlIGJlZW4gbGVmdCBvdmVyLgoKPj4gKwo+ PiArCQkvKiBjaGVjayBzdGF0dXMsIGlmIGNoYW5uZWwgaXNuJ3QgYnVzeSB0aGVuIHNraXAgKi8K Pj4gKwkJaWYgKCEoc3RhdHVzICYgVEVHUkFfQVBCRE1BX1NUQVRVU19CVVNZKSkgewo+PiArCQkJ cmVzdWx0ID0gcmVzaWR1YWw7Cj4+ICsJCQlicmVhazsKPj4gKwkJfQo+IAo+IFRoaXMgZG9lc24n dCBsb29rIGNvcnJlY3QgYmVjYXVzZSBUUk0gc2F5cyAiQnVzeSBiaXQgZ2V0cyBzZXQgYXMgc29v biBhcyBhIGNoYW5uZWwgaXMgZW5hYmxlZCBhbmQgZ2V0cyBjbGVhcmVkIGFmdGVyIHRyYW5zZmVy IGNvbXBsZXRlcyIsIGhlbmNlIGEgY2xlYXJlZCBCVVNZIGJpdCBtZWFucyB0aGF0IGFsbCB0cmFu c2ZlcnMgYXJlIGNvbXBsZXRlZCBhbmQgcmVzdWx0PXJlc2lkdWFsIGlzIGluY29ycmVjdCBoZXJl LiBHaXZlbiB0aGF0IHRoZXJlIGlzIGEgY2hlY2sgZm9yIEVPQyBiaXQgYmVpbmcgc2V0IGJlbG93 LCB0aGlzIGh1bmsgc2hvdWxkIGJlIHJlbW92ZWQuCgpJJ2xsIGNoZWNrIG5vdGVzLCBidXQgc2Vl IGJlbG93LgoKPj4gKwo+PiArCQkvKiBpZiB3ZSd2ZSBnb3QgYW4gaW50ZXJydXB0IHBlbmRpbmcg b24gdGhlIGNoYW5uZWwsIGRvbid0Cj4+ICsJCSAqIHRyeSBhbmQgZGVhbCB3aXRoIHRoZSByZXNp ZHVlIGFzIHRoZSBoYXJkd2FyZSBoYXMgbGlrZWx5Cj4+ICsJCSAqIG1vdmVkIG9uIHRvIHRoZSBu ZXh0IGJ1ZmZlci4gcmV0dXJuIGFsbCBkYXRhIG1vdmVkLgo+PiArCQkgKi8KPj4gKwkJaWYgKHN0 YXR1cyAmIFRFR1JBX0FQQkRNQV9TVEFUVVNfSVNFX0VPQykgewo+PiArCQkJcmVzdWx0ID0gcmVz aWR1YWwgLSBzZ19yZXEtPnJlcV9sZW47Cj4+ICsJCQlicmVhazsKPj4gKwkJfQo+PiArCj4+ICsJ CWlmICh0ZGMtPnRkbWEtPmNoaXBfZGF0YS0+c3VwcG9ydF9zZXBhcmF0ZV93Y291bnRfcmVnKQo+ PiArCQkJd2NvdW50ID0gdGRjX3JlYWQodGRjLCBURUdSQV9BUEJETUFfQ0hBTl9XT1JEX1RSQU5T RkVSKTsKPj4gKwkJZWxzZQo+PiArCQkJd2NvdW50ID0gc3RhdHVzOwo+PiArCj4+ICsJCS8qIElm IHRoZSByZXF1ZXN0IGlzIGF0IHRoZSBmdWxsIHBvaW50LCB0aGVuIHRoZXJlIGlzIGEKPj4gKwkJ ICogY2hhbmNlIHRoYXQgd2UgaGF2ZSByZWFkIHRoZSBzdGF0dXMgcmVnaXN0ZXIgaW4gdGhlCj4+ ICsJCSAqIG1pZGRsZSBvZiB0aGUgaGFyZHdhcmUgcmVsb2FkaW5nIHRoZSBuZXh0IGJ1ZmZlci4K Pj4gKwkJICoKPj4gKwkJICogVGhlIHNlcXVlbmNlIHNlZW1zIHRvIGJlIGF0IHRoZSBlbmQgb2Yg dGhlIGJ1ZmZlciwgdG8KPj4gKwkJICogbG9hZCB0aGUgbmV3IHdvcmQgY291bnQgYmVmb3JlIHJh aXNpbmcgdGhlIEVPQyBmbGFnIChvcgo+PiArCQkgKiBjaGFuZ2luZyB0aGUgcGluZy1wb25nIGZs YWcgd2hpY2ggY291bGQgaGF2ZSBhbHNvIGJlZW4KPj4gKwkJICogdXNlZCB0byBkZXRlcm1pbmUg YSBuZXcgYnVmZmVyKS4gVGhpcyAgbWVhbnMgdGhlcmUgaXMgYQo+PiArCQkgKiBzbWFsbCB3aW5k b3cgd2hlcmUgd2UgY2Fubm90IGRldGVybWluZSB6ZXJvLWRvbmUgZm9yIHRoZQo+PiArCQkgKiBj dXJyZW50IGJ1ZmZlciwgb3IgbW92ZWQgdG8gbmV4dCBidWZmZXIuCj4+ICsJCSAqCj4+ICsJCSAq IElmIGRvbmUgc2hvd3MgMCwgdGhlbiByZXRyeSB0aGUgbG9hZCwgYXMgaXQgbWF5IGhpdCB0aGUK Pj4gKwkJICogYWJvdmUgaGFyZHdhcmUgcmFjZS4gV2Ugd2lsbCBlaXRoZXIgZ2V0IGEgbmV3IHZh bHVlIHdoaWNoCj4+ICsJCSAqIGlzIGZyb20gdGhlIGZpcnN0IGJ1ZmZlciwgb3Igd2UgZ2V0IGFu IEVPQyAobmV3IGJ1ZmZlcikKPj4gKwkJICogb3IgYm90aCBhIG5ldyB2YWx1ZSBhbmQgYW4gRU9D Li4uCj4+ICsJCSAqLwo+PiArCQlkb25lID0gZ2V0X2N1cnJlbnRfeGZlcnJlZF9jb3VudCh0ZGMs IHNnX3JlcSwgd2NvdW50KTsKPj4gKwkJaWYgKGRvbmUgIT0gMCkgewo+PiArCQkJcmVzdWx0ID0g cmVzaWR1YWwgLSBkb25lOwo+PiArCQkJYnJlYWs7Cj4+ICsJCX0KPj4gKwo+PiArCQluZGVsYXko MTAwKTsKPiAKPiBQbGVhc2UgdXNlIHVkZWxheSgxKSBiZWNhdXNlIHRoZXJlIGlzIG5vIG5kZWxh eSBvbiBhcm0zMiBhbmQgbmRlbGF5KDEwMCkgaXMgZ2V0dGluZyByb3VuZGVkIHVwIHRvIDF1c2Vj LiBBRkFJSywgYXJtNjQgZG9lc24ndCBoYXZlIHJlbGlhYmxlIG5kZWxheSBvbiBUZWdyYSBlaXRo ZXIgYmVjYXVzZSB0aW1lciByYXRlIGNoYW5nZXMgd2l0aCB0aGUgQ1BVIGZyZXF1ZW5jeSBzY2Fs aW5nLgoKSSdsbCBjaGVjaywgYnV0IGxhc3QgdGltZSBpdCB3YXMgaW1wbGVtZW50ZWQuIFRoaXMg c2VlbXMgYSBiYWNrd2FyZHMgc3RlcC4KCj4gU2Vjb25kbHkgZG9uZT0wIGlzbid0IGEgZXJyb3Ig Y2FzZSwgdGVjaG5pY2FsbHkgdGhpcyBjb3VsZCBiZSB0aGUgY2FzZSB3aGVuIHRlZ3JhX2RtYV91 cGRhdGVfcmVzaWR1YWwoKSBpcyBpbnZva2VkIGp1c3QgYWZ0ZXIgc3RhcnRpbmcgdGhlIHRyYW5z ZmVyLiBIZW5jZSBJIHRoaW5rIHRoaXMgZG8td2hpbGUgbG9vcCBhbmQgdGltZW91dCBjaGVja2lu ZyBhcmVuJ3QgbmVlZGVkIGF0IGFsbCBzaW5jZSBkb25lPTAgaXMgYSBwZXJmZWN0bHkgdmFsaWQg Y2FzZS4KCnRoaXMgaXMgbm90IGNoZWNraW5nIGZvciBhbiBlcnJvciwgaXQncyBjaGVja2luZyBm b3IgYSBwb3NzaWJsZQppbmFjY3VyYXRlIHJlYWRpbmcuCgo+IAo+IEFsdG9nZXRoZXIgc2VlbXMg dGhlIHRlZ3JhX2RtYV91cGRhdGVfcmVzaWR1YWwoKSBjb3VsZCBiZSByZWR1Y2VkIHRvOgo+IAo+ IHN0YXRpYyB1bnNpZ25lZCBpbnQgdGVncmFfZG1hX3VwZGF0ZV9yZXNpZHVhbChzdHJ1Y3QgdGVn cmFfZG1hX2NoYW5uZWwgKnRkYywKPiAJCQkJCSAgICAgIHN0cnVjdCB0ZWdyYV9kbWFfc2dfcmVx ICpzZ19yZXEsCj4gCQkJCQkgICAgICBzdHJ1Y3QgdGVncmFfZG1hX2Rlc2MgKmRtYV9kZXNjLAo+ IAkJCQkJICAgICAgdW5zaWduZWQgaW50IHJlc2lkdWFsKQo+IHsKPiAJdW5zaWduZWQgbG9uZyBz dGF0dXMsIHdjb3VudDsKPiAKPiAJaWYgKGxpc3RfaXNfZmlyc3QoJnNnX3JlcS0+bm9kZSwgJnRk Yy0+cGVuZGluZ19zZ19yZXEpKQo+IAkJcmV0dXJuIHJlc2lkdWFsOwo+IAo+IAlpZiAodGRjLT50 ZG1hLT5jaGlwX2RhdGEtPnN1cHBvcnRfc2VwYXJhdGVfd2NvdW50X3JlZykKPiAJCXdjb3VudCA9 IHRkY19yZWFkKHRkYywgVEVHUkFfQVBCRE1BX0NIQU5fV09SRF9UUkFOU0ZFUik7Cj4gCj4gCXN0 YXR1cyA9IHRkY19yZWFkKHRkYywgVEVHUkFfQVBCRE1BX0NIQU5fU1RBVFVTKTsKPiAKPiAJaWYg KCF0ZGMtPnRkbWEtPmNoaXBfZGF0YS0+c3VwcG9ydF9zZXBhcmF0ZV93Y291bnRfcmVnKQo+IAkJ d2NvdW50ID0gc3RhdHVzOwo+IAo+IAlpZiAoc3RhdHVzICYgVEVHUkFfQVBCRE1BX1NUQVRVU19J U0VfRU9DKQo+IAkJcmV0dXJuIHJlc2lkdWFsIC0gc2dfcmVxLT5yZXFfbGVuOwo+IAo+IAlyZXR1 cm4gcmVzaWR1YWwgLSBnZXRfY3VycmVudF94ZmVycmVkX2NvdW50KHRkYywgc2dfcmVxLCB3Y291 bnQpOwo+IH0KCkknbSBub3Qgc3VyZSBpZiB0aGF0IHdpbGwgd29yayBhbGwgdGhlIHRpbWUuIEl0 IHRvb2sgZGF5cyBvZiB0ZXN0aW5nIHRvCmdldCByZWxpYWJsZSBlcnJvciBkYXRhIGZvciB0aGUg Y2FzZXMgd2UncmUgbG9va2luZyBmb3IgaGVyZS4K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A615C43219 for ; Wed, 1 May 2019 08:58:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3EEB32081C for ; Wed, 1 May 2019 08:58:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726014AbfEAI6n (ORCPT ); Wed, 1 May 2019 04:58:43 -0400 Received: from imap1.codethink.co.uk ([176.9.8.82]:57125 "EHLO imap1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725776AbfEAI6n (ORCPT ); Wed, 1 May 2019 04:58:43 -0400 Received: from [167.98.27.226] (helo=[10.35.6.83]) by imap1.codethink.co.uk with esmtpsa (Exim 4.84_2 #1 (Debian)) id 1hLl4Y-000347-Rq; Wed, 01 May 2019 09:58:38 +0100 Subject: Re: [PATCH] dma: tegra: add accurate reporting of dma state To: Dmitry Osipenko , linux-kernel@lists.codethink.co.uk Cc: Laxman Dewangan , Jon Hunter , Vinod Koul , Dan Williams , Thierry Reding , dmaengine@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <20190424162348.23692-1-ben.dooks@codethink.co.uk> From: Ben Dooks Organization: Codethink Limited. Message-ID: Date: Wed, 1 May 2019 09:58:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format="flowed" Content-Language: en-GB Content-Transfer-Encoding: 8bit Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Message-ID: <20190501085837.G9elpGev_C-ZRMDJEsa_fI2jXi4Ct9hdX9aZhz68wTM@z> On 24/04/2019 19:17, Dmitry Osipenko wrote: > 24.04.2019 19:23, Ben Dooks пишет: >> The tx_status callback does not report the state of the transfer >> beyond complete segments. This causes problems with users such as >> ALSA when applications want to know accurately how much data has >> been moved. >> >> This patch addes a function tegra_dma_update_residual() to query >> the hardware and modify the residual information accordinly. It >> takes into account any hardware issues when trying to read the >> state, such as delays between finishing a buffer and signalling >> the interrupt. >> >> Signed-off-by: Ben Dooks > > Hello Ben, > > Thank you very much for keeping it up. I have couple comments, please see them below. > >> Cc: Dmitry Osipenko >> Cc: Laxman Dewangan (supporter:TEGRA DMA DRIVERS) >> Cc: Jon Hunter (supporter:TEGRA DMA DRIVERS) >> Cc: Vinod Koul (maintainer:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM) >> Cc: Dan Williams (reviewer:ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API) >> Cc: Thierry Reding (supporter:TEGRA ARCHITECTURE SUPPORT) >> Cc: dmaengine@vger.kernel.org (open list:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM) >> Cc: linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) >> Cc: linux-kernel@vger.kernel.org (open list) >> --- >> drivers/dma/tegra20-apb-dma.c | 92 ++++++++++++++++++++++++++++++++--- >> 1 file changed, 86 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c >> index cf462b1abc0b..544e7273e741 100644 >> --- a/drivers/dma/tegra20-apb-dma.c >> +++ b/drivers/dma/tegra20-apb-dma.c >> @@ -808,6 +808,90 @@ static int tegra_dma_terminate_all(struct dma_chan *dc) >> return 0; >> } >> >> +static unsigned int tegra_dma_update_residual(struct tegra_dma_channel *tdc, >> + struct tegra_dma_sg_req *sg_req, >> + struct tegra_dma_desc *dma_desc, >> + unsigned int residual) >> +{ >> + unsigned long status = 0x0; >> + unsigned long wcount; >> + unsigned long ahbptr; >> + unsigned long tmp = 0x0; >> + unsigned int result; > > You could pre-assign ahbptr=0xffffffff and result=residual here, then you could remove all the duplicated assigns below. ok, ta. >> + int retries = TEGRA_APBDMA_BURST_COMPLETE_TIME * 10; >> + int done; >> + >> + /* if we're not the current request, then don't alter the residual */ >> + if (sg_req != list_first_entry(&tdc->pending_sg_req, >> + struct tegra_dma_sg_req, node)) { >> + result = residual; >> + ahbptr = 0xffffffff; >> + goto done; >> + } >> + >> + /* loop until we have a reliable result for residual */ >> + do { >> + ahbptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR); >> + status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); >> + tmp = tdc_read(tdc, 0x08); /* total count for debug */ > > The "tmp" variable isn't used anywhere in the code, please remove it. must have been left over. >> + >> + /* check status, if channel isn't busy then skip */ >> + if (!(status & TEGRA_APBDMA_STATUS_BUSY)) { >> + result = residual; >> + break; >> + } > > This doesn't look correct because TRM says "Busy bit gets set as soon as a channel is enabled and gets cleared after transfer completes", hence a cleared BUSY bit means that all transfers are completed and result=residual is incorrect here. Given that there is a check for EOC bit being set below, this hunk should be removed. I'll check notes, but see below. >> + >> + /* if we've got an interrupt pending on the channel, don't >> + * try and deal with the residue as the hardware has likely >> + * moved on to the next buffer. return all data moved. >> + */ >> + if (status & TEGRA_APBDMA_STATUS_ISE_EOC) { >> + result = residual - sg_req->req_len; >> + break; >> + } >> + >> + if (tdc->tdma->chip_data->support_separate_wcount_reg) >> + wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER); >> + else >> + wcount = status; >> + >> + /* If the request is at the full point, then there is a >> + * chance that we have read the status register in the >> + * middle of the hardware reloading the next buffer. >> + * >> + * The sequence seems to be at the end of the buffer, to >> + * load the new word count before raising the EOC flag (or >> + * changing the ping-pong flag which could have also been >> + * used to determine a new buffer). This means there is a >> + * small window where we cannot determine zero-done for the >> + * current buffer, or moved to next buffer. >> + * >> + * If done shows 0, then retry the load, as it may hit the >> + * above hardware race. We will either get a new value which >> + * is from the first buffer, or we get an EOC (new buffer) >> + * or both a new value and an EOC... >> + */ >> + done = get_current_xferred_count(tdc, sg_req, wcount); >> + if (done != 0) { >> + result = residual - done; >> + break; >> + } >> + >> + ndelay(100); > > Please use udelay(1) because there is no ndelay on arm32 and ndelay(100) is getting rounded up to 1usec. AFAIK, arm64 doesn't have reliable ndelay on Tegra either because timer rate changes with the CPU frequency scaling. I'll check, but last time it was implemented. This seems a backwards step. > Secondly done=0 isn't a error case, technically this could be the case when tegra_dma_update_residual() is invoked just after starting the transfer. Hence I think this do-while loop and timeout checking aren't needed at all since done=0 is a perfectly valid case. this is not checking for an error, it's checking for a possible inaccurate reading. > > Altogether seems the tegra_dma_update_residual() could be reduced to: > > static unsigned int tegra_dma_update_residual(struct tegra_dma_channel *tdc, > struct tegra_dma_sg_req *sg_req, > struct tegra_dma_desc *dma_desc, > unsigned int residual) > { > unsigned long status, wcount; > > if (list_is_first(&sg_req->node, &tdc->pending_sg_req)) > return residual; > > if (tdc->tdma->chip_data->support_separate_wcount_reg) > wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER); > > status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); > > if (!tdc->tdma->chip_data->support_separate_wcount_reg) > wcount = status; > > if (status & TEGRA_APBDMA_STATUS_ISE_EOC) > return residual - sg_req->req_len; > > return residual - get_current_xferred_count(tdc, sg_req, wcount); > } I'm not sure if that will work all the time. It took days of testing to get reliable error data for the cases we're looking for here. -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html