From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_DKIMWL_WL_HIGH autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95A68C282DD for ; Mon, 10 Jun 2019 07:59:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6AD1420833 for ; Mon, 10 Jun 2019 07:59:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="FVvmuguv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388249AbfFJH72 (ORCPT ); Mon, 10 Jun 2019 03:59:28 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:4982 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387781AbfFJH71 (ORCPT ); Mon, 10 Jun 2019 03:59:27 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 10 Jun 2019 00:59:26 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 10 Jun 2019 00:59:25 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 10 Jun 2019 00:59:25 -0700 Received: from [10.21.132.148] (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 10 Jun 2019 07:59:22 +0000 Subject: Re: [PATCH] [RFC] dmaengine: add fifo_size member To: Peter Ujfalusi , Sameer Pujar , Vinod Koul CC: , , , , , , , , linux-tegra References: <1556623828-21577-1-git-send-email-spujar@nvidia.com> <20190502122506.GP3845@vkoul-mobl.Dlink> <3368d1e1-0d7f-f602-5b96-a978fcf4d91b@nvidia.com> <20190504102304.GZ3845@vkoul-mobl.Dlink> <20190506155046.GH3845@vkoul-mobl.Dlink>

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<56aa6f45-cfd8-7f1e-9392-628ceb58093f@ti.com> From: Jon Hunter Message-ID: Date: Mon, 10 Jun 2019 08:59:20 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <56aa6f45-cfd8-7f1e-9392-628ceb58093f@ti.com> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560153566; bh=JcATbT2l7rEBL58Wu0smiooiH2B1lY4Spxl1zeqk/aw=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=FVvmuguvwlhcn8Cq++i3XakmXucxFPX17+1d1IRnD/96IYpte5Xh++bIY1ocbD0st IoTu/ZtQf2Dh8zQySP0CNTl4ulU/YDFLsNYKK0p9iEj157I8SxEVnzU0MLzXBdKnjF x59PwXh3Nl2y5PQyebs/DZjrEY3+EIl3fX4Uq14RWvLFZFgdKk8IEYprx+AttHlY5f tWybs5s4Fil9NOnkEUbfR/Wzjgs/AgTwiutTktKo2IhamRC4D/KVnqBSYse6wSgB5g VJG3CywhmM2R5ZSvqjkOCgWZXdtVb/HyOddXf1cI3XyfH1pnn8nMlXHyFvCZG86lL1 TiVb+ohxqR05Q== Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On 07/06/2019 14:35, Peter Ujfalusi wrote: > > > On 07/06/2019 15.58, Jon Hunter wrote: >>> Imho if you can explain it without using 'HACK' in the sentences it >>> might be OK, but it does not feel right. >> >> I don't perceive this as a hack. Although from looking at the >> description of the src/dst_maxburst these are burst size with regard to >> the device, so maybe it is a stretch. >> >>> However since your ADMA and ADMIF is highly coupled and it does needs >>> special maxburst information (burst and allocated FIFO depth) I would >>> rather use src_maxburst/dst_maxburst alone for DEV_TO_MEM/MEM_TO_DEV: >>> >>> ADMA_BURST_SIZE(maxburst) ((maxburst) & 0xff) >>> ADMA_FIFO_SIZE(maxburst) (((maxburst) >> 8) & 0xffffff) >>> >>> So lower 1 byte is the burst value you want from ADMA >>> the other 3 bytes are the allocated FIFO size for the given ADMAIF channel. >>> >>> Sure, you need a header for this to make sure there is no >>> misunderstanding between the two sides. >> >> I don't like this because as I mentioned to Dmitry, the ADMA can perform >> memory-to-memory transfers where such encoding would not be applicable. > > mem2mem does not really use dma_slave_config, it is for used by > is_slave_direction() == true type of transfers. > > But true, if you use ADMA against anything other than ADMAIF then this > might be not right for non cyclic transfers. > >> That does not align with the description in the >> include/linux/dmaengine.h either. > > True. > >>> Or pass the allocated FIFO size via maxburst and then the ADMA driver >>> will pick a 'good/safe' burst value for it. >>> >>> Or new member, but do you need two of them for src/dst? Probably >>> fifo_depth is better word for it, or allocated_fifo_depth. >> >> Right, so looking at the struct dma_slave_config we have ... >> >> u32 src_maxburst; >> u32 dst_maxburst; >> u32 src_port_window_size; >> u32 dst_port_window_size; >> >> Now if we could make these window sizes a union like the following this >> could work ... >> >> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h >> index 8fcdee1c0cf9..851251263527 100644 >> --- a/include/linux/dmaengine.h >> +++ b/include/linux/dmaengine.h >> @@ -360,8 +360,14 @@ struct dma_slave_config { >> enum dma_slave_buswidth dst_addr_width; >> u32 src_maxburst; >> u32 dst_maxburst; >> - u32 src_port_window_size; >> - u32 dst_port_window_size; >> + union { >> + u32 port_window_size; >> + u32 port_fifo_size; >> + } src; >> + union { >> + u32 port_window_size; >> + u32 port_fifo_size; >> + } dst; > > What if in the future someone will have a setup where they would need both? I think if you look at the description for the port_window_size you will see that this is not applicable for FIFOs and so these would be mutually exclusive AFAICT. However, if there was an even weirder DMA out there in the future it could always be patched :-) > So not sure. Your problems are coming from a split DMA setup where the > two are highly coupled, but sits in a different place and need to be > configured as one device. > > I think xilinx_dma is facing with similar issues and they have a custom > API to set parameters which does not fit or is peripheral specific: > include/linux/dma/xilinx_dma.h > > Not sure if that is an acceptable solution. I am not a fan of that but it could work. Cheers Jon -- nvpublic