From: Peter Ujfalusi <peter.ujfalusi@ti.com>
To: <vkoul@kernel.org>, <robh+dt@kernel.org>, <nm@ti.com>,
<ssantosh@kernel.org>
Cc: <dan.j.williams@intel.com>, <dmaengine@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<grygorii.strashko@ti.com>, <lokeshvutla@ti.com>,
<t-kristo@ti.com>, <tony@atomide.com>, <j-keerthy@ti.com>
Subject: Re: [PATCH v5 09/15] dmaengine: ti: New driver for K3 UDMA - split#1: defines, structs, io func
Date: Mon, 11 Nov 2019 17:25:18 +0200 [thread overview]
Message-ID: <f6ad18d4-a8c2-fbed-3e41-40dcb23e651c@ti.com> (raw)
In-Reply-To: <20191111135330.8235-10-peter.ujfalusi@ti.com>
Hi,
On 11/11/2019 15.53, Peter Ujfalusi wrote:
> Split patch for review containing: defines, structs, io and low level
> functions and interrupt callbacks.
>
> DMA driver for
> Texas Instruments K3 NAVSS Unified DMA – Peripheral Root Complex (UDMA-P)
>
> The UDMA-P is intended to perform similar (but significantly upgraded) functions
> as the packet-oriented DMA used on previous SoC devices. The UDMA-P module
> supports the transmission and reception of various packet types. The UDMA-P is
> architected to facilitate the segmentation and reassembly of SoC DMA data
> structure compliant packets to/from smaller data blocks that are natively
> compatible with the specific requirements of each connected peripheral. Multiple
> Tx and Rx channels are provided within the DMA which allow multiple segmentation
> or reassembly operations to be ongoing. The DMA controller maintains state
> information for each of the channels which allows packet segmentation and
> reassembly operations to be time division multiplexed between channels in order
> to share the underlying DMA hardware. An external DMA scheduler is used to
> control the ordering and rate at which this multiplexing occurs for Transmit
> operations. The ordering and rate of Receive operations is indirectly controlled
> by the order in which blocks are pushed into the DMA on the Rx PSI-L interface.
>
> The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
> channels. Channels in the UDMA-P can be configured to be either Packet-Based or
> Third-Party channels on a channel by channel basis.
>
> The initial driver supports:
> - MEM_TO_MEM (TR mode)
> - DEV_TO_MEM (Packet / TR mode)
> - MEM_TO_DEV (Packet / TR mode)
> - Cyclic (Packet / TR mode)
> - Metadata for descriptors
>
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> ---
> drivers/dma/ti/k3-udma.c | 1047 ++++++++++++++++++++++++++++++++++++++
> drivers/dma/ti/k3-udma.h | 120 +++++
> 2 files changed, 1167 insertions(+)
> create mode 100644 drivers/dma/ti/k3-udma.c
> create mode 100644 drivers/dma/ti/k3-udma.h
>
> diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
> new file mode 100644
> index 000000000000..c6f94d79388c
> --- /dev/null
> +++ b/drivers/dma/ti/k3-udma.c
...
> +static bool udma_is_chan_running(struct udma_chan *uc)
> +{
> + u32 trt_ctl = 0;
> + u32 rrt_ctl = 0;
> +
> + if (uc->tchan)
> + trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
> + if (uc->rchan)
> + rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
> +
> + if (trt_ctl & (UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN))
Gash:
if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
> + return true;
> +
> + return false;
> +}
- Péter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
next prev parent reply other threads:[~2019-11-11 15:24 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-11 13:53 [PATCH v5 00/15] dmaengine/soc: Add Texas Instruments UDMA support Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 01/15] bindings: soc: ti: add documentation for k3 ringacc Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 02/15] soc: ti: k3: add navss ringacc driver Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 03/15] dmaengine: doc: Add sections for per descriptor metadata support Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 04/15] dmaengine: Add metadata_ops for dma_async_tx_descriptor Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 05/15] dmaengine: Add support for reporting DMA cached data amount Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 06/15] dmaengine: ti: Add cppi5 header for K3 NAVSS/UDMA Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 07/15] dmaengine: ti: k3 PSI-L remote endpoint configuration Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 08/15] dt-bindings: dma: ti: Add document for K3 UDMA Peter Ujfalusi
2019-11-12 19:27 ` Rob Herring
2019-11-11 13:53 ` [PATCH v5 09/15] dmaengine: ti: New driver for K3 UDMA - split#1: defines, structs, io func Peter Ujfalusi
2019-11-11 15:25 ` Peter Ujfalusi [this message]
2019-11-11 13:53 ` [PATCH v5 10/15] dmaengine: ti: New driver for K3 UDMA - split#2: probe/remove, xlate and filter_fn Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 11/15] dmaengine: ti: New driver for K3 UDMA - split#3: alloc/free chan_resources Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 12/15] dmaengine: ti: New driver for K3 UDMA - split#4: dma_device callbacks 1 Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 13/15] dmaengine: ti: New driver for K3 UDMA - split#5: dma_device callbacks 2 Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 14/15] dmaengine: ti: New driver for K3 UDMA - split#6: Kconfig and Makefile Peter Ujfalusi
2019-11-11 13:53 ` [PATCH v5 15/15] dmaengine: ti: k3-udma: Add glue layer for non DMAengine users Peter Ujfalusi
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