From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF6B5C31E44 for ; Wed, 12 Jun 2019 01:18:23 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id 2BC9020874 for ; Wed, 12 Jun 2019 01:18:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2BC9020874 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 74AD91D0B8; Wed, 12 Jun 2019 03:18:22 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id B95A91D0B7 for ; Wed, 12 Jun 2019 03:18:19 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Jun 2019 18:18:18 -0700 X-ExtLoop1: 1 Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga003.jf.intel.com with ESMTP; 11 Jun 2019 18:18:18 -0700 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 11 Jun 2019 18:18:18 -0700 Received: from shsmsx153.ccr.corp.intel.com (10.239.6.53) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 11 Jun 2019 18:18:17 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.185]) by SHSMSX153.ccr.corp.intel.com ([169.254.12.76]) with mapi id 14.03.0439.000; Wed, 12 Jun 2019 09:17:14 +0800 From: "Xu, Rosen" To: "Pei, Andy" , "dev@dpdk.org" Thread-Topic: [PATCH v2 1/4] net/ipn3ke: add new register address Thread-Index: AQHVIDu+Op2lb5OEzUelUAC3s9cfSKaXOJ1w Date: Wed, 12 Jun 2019 01:17:13 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D73A7EF4FD@SHSMSX104.ccr.corp.intel.com> References: <1559543493-215042-2-git-send-email-andy.pei@intel.com> <1560246526-264797-1-git-send-email-andy.pei@intel.com> In-Reply-To: <1560246526-264797-1-git-send-email-andy.pei@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOTIyNzEyNWUtMmQyNC00MjkyLWJkZGMtZTlkOGFjNzkxODdkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiWDR0NnhMSlNSdVZZUnJPK3pBZXJCQ0tyZFBzYU5rK0oyWnJGcTdwQWtrcmdhV2MxOE5lcGdaMVwvSXI5S1hOeVcifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 1/4] net/ipn3ke: add new register address X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Pei, Andy > Sent: Tuesday, June 11, 2019 17:49 > To: dev@dpdk.org > Cc: Pei, Andy ; Xu, Rosen > Subject: [PATCH v2 1/4] net/ipn3ke: add new register address >=20 > ipn3ke can work on 10G mode and 25G mode. > 10G mode and 25G mode has different MAC register address for statistics. > This patch implemente statistics registers for 10G mode and 25G mode. >=20 > Fixes: c01c748e4ae6 ("net/ipn3ke: add new driver") > Cc: rosen.xu@intel.com >=20 > Signed-off-by: Andy Pei > --- > drivers/net/ipn3ke/ipn3ke_ethdev.h | 572 +++++++++++++++++++++----------= - > ----- > 1 file changed, 331 insertions(+), 241 deletions(-) >=20 > diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h > b/drivers/net/ipn3ke/ipn3ke_ethdev.h > index af2da05..5c84eff 100644 > --- a/drivers/net/ipn3ke/ipn3ke_ethdev.h > +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h > @@ -650,239 +650,298 @@ static inline void _ipn3ke_indrct_write(struct > ipn3ke_hw *hw, #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \ > IPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT) >=20 > -#define IPN3KE_MAC_TX_STATS_CLR 0x0140 > -#define IPN3KE_MAC_TX_STATS_CLR_CLEAR_SHIFT 0 > -#define IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK \ > - IPN3KE_MASK(0x1, IPN3KE_MAC_TX_STATS_CLR_CLEAR_SHIFT) > - > -#define IPN3KE_MAC_RX_STATS_CLR 0x01C0 > -#define IPN3KE_MAC_RX_STATS_CLR_CLEAR_SHIFT 0 > -#define IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK \ > - IPN3KE_MASK(0x1, IPN3KE_MAC_RX_STATS_CLR_CLEAR_SHIFT) > - > -/*tx_stats_framesOK*/ > -#define IPN3KE_MAC_TX_STATS_FRAMESOK_HI 0x0142 -#define > IPN3KE_MAC_TX_STATS_FRAMESOK_LOW 0x0143 > - > -/*rx_stats_framesOK*/ > -#define IPN3KE_MAC_RX_STATS_FRAMESOK_HI 0x01C2 -#define > IPN3KE_MAC_RX_STATS_FRAMESOK_LOW 0x01C3 > - > -/*tx_stats_framesErr*/ > -#define IPN3KE_MAC_TX_STATS_FRAMESERR_HI 0x0144 -#define > IPN3KE_MAC_TX_STATS_FRAMESERR_LOW 0x0145 > - > -/*rx_stats_framesErr*/ > -#define IPN3KE_MAC_RX_STATS_FRAMESERR_HI 0x01C4 -#define > IPN3KE_MAC_RX_STATS_FRAMESERR_LOW 0x01C5 > - > -/*rx_stats_framesCRCErr*/ > -#define IPN3KE_MAC_RX_STATS_FRAMESCRCERR_HI 0x01C6 -#define > IPN3KE_MAC_RX_STATS_FRAMESCRCERR_LOW 0x01C7 > - > -/*tx_stats_octetsOK 64b*/ > -#define IPN3KE_MAC_TX_STATS_OCTETSOK_HI 0x0148 -#define > IPN3KE_MAC_TX_STATS_OCTETSOK_LOW 0x0149 > - > -/*rx_stats_octetsOK 64b*/ > -#define IPN3KE_MAC_RX_STATS_OCTETSOK_HI 0x01C8 -#define > IPN3KE_MAC_RX_STATS_OCTETSOK_LOW 0x01C9 > - > -/*tx_stats_pauseMACCtrl_Frames*/ > -#define IPN3KE_MAC_TX_STATS_PAUSEMACCTRL_FRAMES_HI 0x014A - > #define IPN3KE_MAC_TX_STATS_PAUSEMACCTRL_FRAMES_LOW 0x014B > - > -/*rx_stats_pauseMACCtrl_Frames*/ > -#define IPN3KE_MAC_RX_STATS_PAUSEMACCTRL_FRAMES_HI 0x01CA - > #define IPN3KE_MAC_RX_STATS_PAUSEMACCTRL_FRAMES_LOW 0x01CB > - > -/*tx_stats_ifErrors*/ > -#define IPN3KE_MAC_TX_STATS_IFERRORS_HI 0x014C -#define > IPN3KE_MAC_TX_STATS_IFERRORS_LOW 0x014D > - > -/*rx_stats_ifErrors*/ > -#define IPN3KE_MAC_RX_STATS_IFERRORS_HI 0x01CC -#define > IPN3KE_MAC_RX_STATS_IFERRORS_LOW 0x01CD > - > -/*tx_stats_unicast_FramesOK*/ > -#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESOK_HI 0x014E -#define > IPN3KE_MAC_TX_STATS_UNICAST_FRAMESOK_LOW 0x014F > - > -/*rx_stats_unicast_FramesOK*/ > -#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESOK_HI 0x01CE -#define > IPN3KE_MAC_RX_STATS_UNICAST_FRAMESOK_LOW 0x01CF > - > -/*tx_stats_unicast_FramesErr*/ > -#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESERR_HI 0x0150 -#define > IPN3KE_MAC_TX_STATS_UNICAST_FRAMESERR_LOW 0x0151 > - > -/*rx_stats_unicast_FramesErr*/ > -#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESERR_HI 0x01D0 -#define > IPN3KE_MAC_RX_STATS_UNICAST_FRAMESERR_LOW 0x01D1 > - > -/*tx_stats_multicast_FramesOK*/ > -#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESOK_HI 0x0152 - > #define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESOK_LOW 0x0153 > - > -/*rx_stats_multicast_FramesOK*/ > -#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESOK_HI 0x01D2 - > #define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESOK_LOW 0x01D3 > - > -/*tx_stats_multicast_FramesErr*/ > -#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESERR_HI 0x0154 - > #define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESERR_LOW 0x0155 > - > -/*rx_stats_multicast_FramesErr*/ > -#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESERR_HI 0x01D4 - > #define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESERR_LOW 0x01D5 > - > -/*tx_stats_broadcast_FramesOK*/ > -#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESOK_HI 0x0156 - > #define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESOK_LOW 0x0157 > - > -/*rx_stats_broadcast_FramesOK*/ > -#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESOK_HI 0x01D6 - > #define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESOK_LOW 0x01D7 > - > -/*tx_stats_broadcast_FramesErr*/ > -#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESERR_HI 0x0158 - > #define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESERR_LOW 0x0159 > - > -/*rx_stats_broadcast_FramesErr*/ > -#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESERR_HI 0x01D8 - > #define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESERR_LOW 0x01D9 > - > -/*tx_stats_etherStatsOctets 64b*/ > -#define IPN3KE_MAC_TX_STATS_ETHERSTATSOCTETS_HI 0x015A -#define > IPN3KE_MAC_TX_STATS_ETHERSTATSOCTETS_LOW 0x015B > - > -/*rx_stats_etherStatsOctets 64b*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSOCTETS_HI 0x01DA -#define > IPN3KE_MAC_RX_STATS_ETHERSTATSOCTETS_LOW 0x01DB > - > -/*tx_stats_etherStatsPkts*/ > -#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS_HI 0x015C -#define > IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS_LOW 0x015D > - > -/*rx_stats_etherStatsPkts*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS_HI 0x01DC -#define > IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS_LOW 0x01DD > - > -/*tx_stats_etherStatsUndersizePkts*/ > -#define IPN3KE_MAC_TX_STATS_ETHERSTATSUNDERSIZEPKTS_HI 0x015E - > #define IPN3KE_MAC_TX_STATS_ETHERSTATSUNDERSIZEPKTS_LOW 0x015F > - > -/*rx_stats_etherStatsUndersizePkts*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSUNDERSIZEPKTS_HI 0x01DE - > #define IPN3KE_MAC_RX_STATS_ETHERSTATSUNDERSIZEPKTS_LOW 0x01DF > - > -/*tx_stats_etherStatsOversizePkts*/ > -#define IPN3KE_MAC_TX_STATS_ETHERSTATSOVERSIZEPKTS_HI 0x0160 - > #define IPN3KE_MAC_TX_STATS_ETHERSTATSOVERSIZEPKTS_LOW 0x0161 > - > -/*rx_stats_etherStatsOversizePkts*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSOVERSIZEPKTS_HI 0x01E0 - > #define IPN3KE_MAC_RX_STATS_ETHERSTATSOVERSIZEPKTS_LOW 0x01E1 > - > -/*tx_stats_etherStatsPkts64Octets*/ > -#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS64OCTETS_HI 0x0162 - > #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS64OCTETS_LOW 0x0163 > - > -/*rx_stats_etherStatsPkts64Octets*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS64OCTETS_HI 0x01E2 - > #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS64OCTETS_LOW 0x01E3 > - > -/*tx_stats_etherStatsPkts65to127Octets*/ > -#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS65TO127OCTETS_HI > 0x0164 -#define > IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS65TO127OCTETS_LOW 0x0165 > - > -/*rx_stats_etherStatsPkts65to127Octets*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS65TO127OCTETS_HI > 0x01E4 -#define > IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS65TO127OCTETS_LOW 0x01E5 > - > -/*tx_stats_etherStatsPkts128to255Octets*/ > -#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS128TO255OCTETS_HI > 0x0166 -#define > IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS128TO255OCTETS_LOW 0x0167 > - > -/*rx_stats_etherStatsPkts128to255Octets*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS128TO255OCTETS_HI > 0x01E6 -#define > IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS128TO255OCTETS_LOW 0x01E7 > - > -/*tx_stats_etherStatsPkts256to511Octet*/ > -#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS256TO511OCTET_HI > 0x0168 -#define > IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS256TO511OCTET_LOW 0x0169 > - > -/*rx_stats_etherStatsPkts256to511Octets*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS256TO511OCTETS_HI > 0x01E8 -#define > IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS256TO511OCTETS_LOW 0x01E9 > - > -/*tx_stats_etherStatsPkts512to1023Octets*/ > -#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS512TO1023OCTETS_HI > 0x016A -#define > IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS512TO1023OCTETS_LOW 0x016B > - > -/*rx_stats_etherStatsPkts512to1023Octets*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS512TO1023OCTETS_HI > 0x01EA -#define > IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS512TO1023OCTETS_LOW 0x01EB > - > -/*tx_stats_etherStatPkts1024to1518Octets*/ > -#define IPN3KE_MAC_TX_STATS_ETHERSTATPKTS1024TO1518OCTETS_HI > 0x016C -#define > IPN3KE_MAC_TX_STATS_ETHERSTATPKTS1024TO1518OCTETS_LOW 0x016D > - > -/*rx_stats_etherStatPkts1024to1518Octets*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATPKTS1024TO1518OCTETS_HI > 0x01EC -#define > IPN3KE_MAC_RX_STATS_ETHERSTATPKTS1024TO1518OCTETS_LOW 0x01ED > - > -/*tx_stats_etherStatsPkts1519toXOctets*/ > -#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS1519TOXOCTETS_HI > 0x016E -#define > IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS1519TOXOCTETS_LOW 0x016F > - > -/*rx_stats_etherStatsPkts1519toXOctets*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS1519TOXOCTETS_HI > 0x01EE -#define > IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS1519TOXOCTETS_LOW 0x01EF > - > -/*rx_stats_etherStatsFragments*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSFRAGMENTS_HI 0x01F0 - > #define IPN3KE_MAC_RX_STATS_ETHERSTATSFRAGMENTS_LOW 0x01F1 > - > -/*rx_stats_etherStatsJabbers*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSJABBERS_HI 0x01F2 -#define > IPN3KE_MAC_RX_STATS_ETHERSTATSJABBERS_LOW 0x01F3 > - > -/*rx_stats_etherStatsCRCErr*/ > -#define IPN3KE_MAC_RX_STATS_ETHERSTATSCRCERR_HI 0x01F4 -#define > IPN3KE_MAC_RX_STATS_ETHERSTATSCRCERR_LOW 0x01F5 > - > -/*tx_stats_unicastMACCtrlFrames*/ > -#define IPN3KE_MAC_TX_STATS_UNICASTMACCTRLFRAMES_HI 0x0176 - > #define IPN3KE_MAC_TX_STATS_UNICASTMACCTRLFRAMES_LOW 0x0177 > - > -/*rx_stats_unicastMACCtrlFrames*/ > -#define IPN3KE_MAC_RX_STATS_UNICASTMACCTRLFRAMES_HI 0x01F6 - > #define IPN3KE_MAC_RX_STATS_UNICASTMACCTRLFRAMES_LOW 0x01F7 > - > -/*tx_stats_multicastMACCtrlFrames*/ > -#define IPN3KE_MAC_TX_STATS_MULTICASTMACCTRLFRAMES_HI 0x0178 - > #define IPN3KE_MAC_TX_STATS_MULTICASTMACCTRLFRAMES_LOW 0x0179 > - > -/*rx_stats_multicastMACCtrlFrames*/ > -#define IPN3KE_MAC_RX_STATS_MULTICASTMACCTRLFRAMES_HI 0x01F8 - > #define IPN3KE_MAC_RX_STATS_MULTICASTMACCTRLFRAMES_LOW 0x01F9 > - > -/*tx_stats_broadcastMACCtrlFrames*/ > -#define IPN3KE_MAC_TX_STATS_BROADCASTMACCTRLFRAMES_HI 0x017A - > #define IPN3KE_MAC_TX_STATS_BROADCASTMACCTRLFRAMES_LOW 0x017B > - > -/*rx_stats_broadcastMACCtrlFrames*/ > -#define IPN3KE_MAC_RX_STATS_BROADCASTMACCTRLFRAMES_HI 0x01FA - > #define IPN3KE_MAC_RX_STATS_BROADCASTMACCTRLFRAMES_LOW 0x01FB > - > -/*tx_stats_PFCMACCtrlFrames*/ > -#define IPN3KE_MAC_TX_STATS_PFCMACCTRLFRAMES_HI 0x017C -#define > IPN3KE_MAC_TX_STATS_PFCMACCTRLFRAMES_LOW 0x017D > - > -/*rx_stats_PFCMACCtrlFrames*/ > -#define IPN3KE_MAC_RX_STATS_PFCMACCTRLFRAMES_HI 0x01FC -#define > IPN3KE_MAC_RX_STATS_PFCMACCTRLFRAMES_LOW 0x01FD > +#define IPN3KE_REGISTER_WIDTH 32 > + > +/*Bits[2:0]: Configuration of TX statistics counters: > + *Bit[2]: Shadow request (active high): When set to the value of 1, > +*TX statistics collection is paused. The underlying counters *continue > +to operate, but the readable values reflect a snapshot at *the time > +the pause flag was activated. Write a 0 to release. > + *Bit[1]: Parity-error clear. When software sets this bit, the IP core > +*clears the parity bit CNTR_TX_STATUS[0]. This bit > + *(CNTR_TX_CONFIG[1]) is self-clearing. > + *Bit[0]: Software can set this bit to the value of 1 to reset all of > +*the TX statistics registers at the same time. This bit is selfclearing. > + *Bits[31:3] are Reserved > + */ > +#define IPN3KE_25G_TX_STATISTICS_CONFIG 0x8= 45 > +#define IPN3KE_25G_TX_STATISTICS_CONFIG_SHADOW_REQUEST_MASK > 0x00000004 > + > +/*Bit[1]: Indicates that the TX statistics registers are paused (while > +*CNTR_TX_CONFIG[2] is asserted). > + *Bit[0]: Indicates the presence of at least one parity error in the > +*TX statistics counters. > + *Bits[31:2] are Reserved. > + */ > +#define IPN3KE_25G_TX_STATISTICS_STATUS 0x8= 46 > +#define IPN3KE_25G_TX_STATISTICS_STATUS_SHADOW_REQUEST_MASK > 0x00000002 > + > +#define IPN3KE_25G_CNTR_TX_FRAGMENTS_LO 0x8= 00 > +#define IPN3KE_25G_CNTR_TX_FRAGMENTS_HI 0x8= 01 > +#define IPN3KE_25G_CNTR_TX_JABBERS_LO 0x8= 02 > +#define IPN3KE_25G_CNTR_TX_JABBERS_HI 0x8= 03 > +#define IPN3KE_25G_CNTR_TX_FCS_LO 0x8= 04 > +#define IPN3KE_25G_CNTR_TX_FCS_HI 0x8= 05 > +#define IPN3KE_25G_CNTR_TX_CRCERR_LO 0x8= 06 > +#define IPN3KE_25G_CNTR_TX_CRCERR_HI 0x8= 07 > +#define IPN3KE_25G_CNTR_TX_MCAST_DATA_ERR_LO 0x8= 08 > +#define IPN3KE_25G_CNTR_TX_MCAST_DATA_ERR_HI 0x8= 09 > +#define IPN3KE_25G_CNTR_TX_BCAST_DATA_ERR_LO 0x8= 0A > +#define IPN3KE_25G_CNTR_TX_BCAST_DATA_ERR_HI 0x8= 0B > +#define IPN3KE_25G_CNTR_TX_UCAST_DATA_ERR_LO 0x8= 0C > +#define IPN3KE_25G_CNTR_TX_UCAST_DATA_ERR_HI 0x8= 0D > +#define IPN3KE_25G_CNTR_TX_MCAST_CTRL_ERR_LO 0x8= 0E > +#define IPN3KE_25G_CNTR_TX_MCAST_CTRL_ERR_HI 0x8= 0F > +#define IPN3KE_25G_CNTR_TX_BCAST_CTRL_ERR_LO 0x8= 10 > +#define IPN3KE_25G_CNTR_TX_BCAST_CTRL_ERR_HI 0x8= 11 > +#define IPN3KE_25G_CNTR_TX_UCAST_CTRL_ERR_LO 0x8= 12 > +#define IPN3KE_25G_CNTR_TX_UCAST_CTRL_ERR_HI 0x8= 13 > +#define IPN3KE_25G_CNTR_TX_PAUSE_ERR_LO 0x8= 14 > +#define IPN3KE_25G_CNTR_TX_PAUSE_ERR_HI 0x8= 15 > +#define IPN3KE_25G_CNTR_TX_64B_LO 0x8= 16 > +#define IPN3KE_25G_CNTR_TX_64B_HI 0x8= 17 > +#define IPN3KE_25G_CNTR_TX_65_127B_LO 0x8= 18 > +#define IPN3KE_25G_CNTR_TX_65_127B_HI 0x8= 19 > +#define IPN3KE_25G_CNTR_TX_128_255B_LO 0x8= 1A > +#define IPN3KE_25G_CNTR_TX_128_255B_HI 0x8= 1B > +#define IPN3KE_25G_CNTR_TX_256_511B_LO 0x8= 1C > +#define IPN3KE_25G_CNTR_TX_256_511B_HI 0x8= 1D > +#define IPN3KE_25G_CNTR_TX_512_1023B_LO 0x8= 1E > +#define IPN3KE_25G_CNTR_TX_512_1023B_HI 0x8= 1F > +#define IPN3KE_25G_CNTR_TX_1024_1518B_LO 0x8= 20 > +#define IPN3KE_25G_CNTR_TX_1024_1518B_HI 0x8= 21 > +#define IPN3KE_25G_CNTR_TX_1519_MAXB_LO 0x8= 22 > +#define IPN3KE_25G_CNTR_TX_1519_MAXB_HI 0x8= 23 > +#define IPN3KE_25G_CNTR_TX_OVERSIZE_LO 0x8= 24 > +#define IPN3KE_25G_CNTR_TX_OVERSIZE_HI 0x8= 25 > +#define IPN3KE_25G_CNTR_TX_MCAST_DATA_OK_LO 0x8= 26 > +#define IPN3KE_25G_CNTR_TX_MCAST_DATA_OK_HI 0x8= 27 > +#define IPN3KE_25G_CNTR_TX_BCAST_DATA_OK_LO 0x8= 28 > +#define IPN3KE_25G_CNTR_TX_BCAST_DATA_OK_HI 0x8= 29 > +#define IPN3KE_25G_CNTR_TX_UCAST_DATA_OK_LO 0x8= 2A > +#define IPN3KE_25G_CNTR_TX_UCAST_DATA_OK_HI 0x8= 2B > +#define IPN3KE_25G_CNTR_TX_MCAST_CTRL_LO 0x8= 2C > +#define IPN3KE_25G_CNTR_TX_MCAST_CTRL_HI 0x8= 2D > +#define IPN3KE_25G_CNTR_TX_BCAST_CTRL_LO 0x8= 2E > +#define IPN3KE_25G_CNTR_TX_BCAST_CTRL_HI 0x8= 2F > +#define IPN3KE_25G_CNTR_TX_UCAST_CTRL_LO 0x8= 30 > +#define IPN3KE_25G_CNTR_TX_UCAST_CTRL_HI 0x8= 31 > +#define IPN3KE_25G_CNTR_TX_PAUSE_LO 0x8= 32 > +#define IPN3KE_25G_CNTR_TX_PAUSE_HI 0x8= 33 > +#define IPN3KE_25G_CNTR_TX_RUNT_LO 0x8= 34 > +#define IPN3KE_25G_CNTR_TX_RUNT_HI 0x8= 35 > +#define IPN3KE_25G_TX_PAYLOAD_OCTETS_OK_LO 0x8= 60 > +#define IPN3KE_25G_TX_PAYLOAD_OCTETS_OK_HI 0x8= 61 > +#define IPN3KE_25G_TX_FRAME_OCTETS_OK_LO 0x8= 62 > +#define IPN3KE_25G_TX_FRAME_OCTETS_OK_HI 0x8= 63 > + > +/*Bits[2:0]: Configuration of RX statistics counters: > + *Bit[2]: Shadow request (active high): When set to the value of 1, > +*RX statistics collection is paused. The underlying counters *continue > +to operate, but the readable values reflect a snapshot *at the time > +the pause flag was activated. Write a 0 to release. > + *Bit[1]: Parity-error clear. When software sets this bit, the IP > +*core clears the parity bit CNTR_RX_STATUS[0]. This bit > + *(CNTR_RX_CONFIG[1]) is self-clearing. > + *Bit[0]: Software can set this bit to the value of 1 to reset all of > +*the RX statistics registers at the same time. This bit is selfclearing. > + *Bits[31:3] are Reserved. > + */ > +#define IPN3KE_25G_RX_STATISTICS_CONFIG 0x9= 45 > +#define IPN3KE_25G_RX_STATISTICS_CONFIG_SHADOW_REQUEST_MASK > 0x00000004 > + > +/*Bit[1]: Indicates that the RX statistics registers are paused > +*(while CNTR_RX_CONFIG[2] is asserted). > + *Bit[0]: Indicates the presence of at least one parity error in the > +*RX statistics counters. > + *Bits [31:2] are Reserved > + */ > +#define IPN3KE_25G_RX_STATISTICS_STATUS 0x9= 46 > +#define IPN3KE_25G_RX_STATISTICS_STATUS_SHADOW_REQUEST_MASK > 0x00000002 > + > +#define IPN3KE_25G_CNTR_RX_FRAGMENTS_LO 0x9= 00 > +#define IPN3KE_25G_CNTR_RX_FRAGMENTS_HI 0x9= 01 > +#define IPN3KE_25G_CNTR_RX_JABBERS_LO 0x9= 02 > +#define IPN3KE_25G_CNTR_RX_JABBERS_HI 0x9= 03 > +#define IPN3KE_25G_CNTR_RX_FCS_LO 0x9= 04 > +#define IPN3KE_25G_CNTR_RX_FCS_HI 0x9= 05 > +#define IPN3KE_25G_CNTR_RX_CRCERR_LO 0x9= 06 > +#define IPN3KE_25G_CNTR_RX_CRCERR_HI 0x9= 07 > +#define IPN3KE_25G_CNTR_RX_MCAST_DATA_ERR_LO 0x9= 08 > +#define IPN3KE_25G_CNTR_RX_MCAST_DATA_ERR_HI 0x9= 09 > +#define IPN3KE_25G_CNTR_RX_BCAST_DATA_ERR_LO 0x9= 0A > +#define IPN3KE_25G_CNTR_RX_BCAST_DATA_ERR_HI 0x9= 0B > +#define IPN3KE_25G_CNTR_RX_UCAST_DATA_ERR_LO 0x9= 0C > +#define IPN3KE_25G_CNTR_RX_UCAST_DATA_ERR_HI 0x9= 0D > +#define IPN3KE_25G_CNTR_RX_MCAST_CTRL_ERR_LO 0x9= 0E > +#define IPN3KE_25G_CNTR_RX_MCAST_CTRL_ERR_HI 0x9= 0F > +#define IPN3KE_25G_CNTR_RX_BCAST_CTRL_ERR_LO 0x9= 10 > +#define IPN3KE_25G_CNTR_RX_BCAST_CTRL_ERR_HI 0x9= 11 > +#define IPN3KE_25G_CNTR_RX_UCAST_CTRL_ERR_LO 0x9= 12 > +#define IPN3KE_25G_CNTR_RX_UCAST_CTRL_ERR_HI 0x9= 13 > +#define IPN3KE_25G_CNTR_RX_PAUSE_ERR_LO 0x9= 14 > +#define IPN3KE_25G_CNTR_RX_PAUSE_ERR_HI 0x9= 15 > +#define IPN3KE_25G_CNTR_RX_64B_LO 0x9= 16 > +#define IPN3KE_25G_CNTR_RX_64B_HI 0x9= 17 > +#define IPN3KE_25G_CNTR_RX_65_127B_LO 0x9= 18 > +#define IPN3KE_25G_CNTR_RX_65_127B_HI 0x9= 19 > +#define IPN3KE_25G_CNTR_RX_128_255B_LO 0x9= 1A > +#define IPN3KE_25G_CNTR_RX_128_255B_HI 0x9= 1B > +#define IPN3KE_25G_CNTR_RX_256_511B_LO 0x9= 1C > +#define IPN3KE_25G_CNTR_RX_256_511B_HI 0x9= 1D > +#define IPN3KE_25G_CNTR_RX_512_1023B_LO 0x9= 1E > +#define IPN3KE_25G_CNTR_RX_512_1023B_HI 0x9= 1F > +#define IPN3KE_25G_CNTR_RX_1024_1518B_LO 0x9= 20 > +#define IPN3KE_25G_CNTR_RX_1024_1518B_HI 0x9= 21 > +#define IPN3KE_25G_CNTR_RX_1519_MAXB_LO 0x9= 22 > +#define IPN3KE_25G_CNTR_RX_1519_MAXB_HI 0x9= 23 > +#define IPN3KE_25G_CNTR_RX_OVERSIZE_LO 0x9= 24 > +#define IPN3KE_25G_CNTR_RX_OVERSIZE_HI 0x9= 25 > +#define IPN3KE_25G_CNTR_RX_MCAST_DATA_OK_LO 0x9= 26 > +#define IPN3KE_25G_CNTR_RX_MCAST_DATA_OK_HI 0x9= 27 > +#define IPN3KE_25G_CNTR_RX_BCAST_DATA_OK_LO 0x9= 28 > +#define IPN3KE_25G_CNTR_RX_BCAST_DATA_OK_HI 0x9= 29 > +#define IPN3KE_25G_CNTR_RX_UCAST_DATA_OK_LO 0x9= 2A > +#define IPN3KE_25G_CNTR_RX_UCAST_DATA_OK_HI 0x9= 2B > +#define IPN3KE_25G_CNTR_RX_MCAST_CTRL_LO 0x9= 2C > +#define IPN3KE_25G_CNTR_RX_MCAST_CTRL_HI 0x9= 2D > +#define IPN3KE_25G_CNTR_RX_BCAST_CTRL_LO 0x9= 2E > +#define IPN3KE_25G_CNTR_RX_BCAST_CTRL_HI 0x9= 2F > +#define IPN3KE_25G_CNTR_RX_UCAST_CTRL_LO 0x9= 30 > +#define IPN3KE_25G_CNTR_RX_UCAST_CTRL_HI 0x9= 31 > +#define IPN3KE_25G_CNTR_RX_PAUSE_LO 0x9= 32 > +#define IPN3KE_25G_CNTR_RX_PAUSE_HI 0x9= 33 > +#define IPN3KE_25G_CNTR_RX_RUNT_LO 0x9= 34 > +#define IPN3KE_25G_CNTR_RX_RUNT_HI 0x9= 35 > +#define IPN3KE_25G_RX_PAYLOAD_OCTETS_OK_LO 0x9= 60 > +#define IPN3KE_25G_RX_PAYLOAD_OCTETS_OK_HI 0x9= 61 > +#define IPN3KE_25G_RX_FRAME_OCTETS_OK_LO 0x9= 62 > +#define IPN3KE_25G_RX_FRAME_OCTETS_OK_HI 0x9= 63 > + > +#define IPN3KE_10G_STATS_HI_VALID_MASK 0x0= 000000F > + > +#define IPN3KE_10G_TX_STATS_CLR 0x0= 140 > +#define IPN3KE_10G_TX_STATS_CLR_CLEAR_SHIFT 0 > +#define IPN3KE_10G_TX_STATS_CLR_CLEAR_MASK \ > + IPN3KE_MASK(0x1, IPN3KE_10G_TX_STATS_CLR_CLEAR_SHIFT) > + > +#define IPN3KE_10G_RX_STATS_CLR 0x0= 1C0 > +#define IPN3KE_10G_RX_STATS_CLR_CLEAR_SHIFT 0 > +#define IPN3KE_10G_RX_STATS_CLR_CLEAR_MASK \ > + IPN3KE_MASK(0x1, IPN3KE_10G_RX_STATS_CLR_CLEAR_SHIFT) > + > +#define IPN3KE_10G_TX_STATS_FRAME_OK_LO 0x0= 142 > +#define IPN3KE_10G_TX_STATS_FRAME_OK_HI 0x0= 143 > +#define IPN3KE_10G_RX_STATS_FRAME_OK_LO 0x0= 1C2 > +#define IPN3KE_10G_RX_STATS_FRAME_OK_HI 0x0= 1C3 > +#define IPN3KE_10G_TX_STATS_FRAME_ERR_LO 0x0= 144 > +#define IPN3KE_10G_TX_STATS_FRAME_ERR_HI 0x0= 145 > +#define IPN3KE_10G_RX_STATS_FRAME_ERR_LO 0x0= 1C4 > +#define IPN3KE_10G_RX_STATS_FRAME_ERR_HI 0x0= 1C5 > +#define IPN3KE_10G_RX_STATS_FRAME_CRC_ERR_LO 0x0= 1C6 > +#define IPN3KE_10G_RX_STATS_FRAME_CRC_ERR_HI 0x0= 1C7 > +#define IPN3KE_10G_TX_STATS_OCTETS_OK_LO 0x0= 148 > +#define IPN3KE_10G_TX_STATS_OCTETS_OK_HI 0x0= 149 > +#define IPN3KE_10G_RX_STATS_OCTETS_OK_LO 0x0= 1C8 > +#define IPN3KE_10G_RX_STATS_OCTETS_OK_HI 0x0= 1C9 > +#define IPN3KE_10G_TX_STATS_PAUSE_MAC_CTRL_FRAMES_LO > 0x014A > +#define IPN3KE_10G_TX_STATS_PAUSE_MAC_CTRL_FRAMES_HI > 0x014B > +#define IPN3KE_10G_RX_STATS_PAUSE_MAC_CTRL_FRAMES_LO > 0x01CA > +#define IPN3KE_10G_RX_STATS_PAUSE_MAC_CTRL_FRAMES_HI > 0x01CB > +#define IPN3KE_10G_TX_STATS_IF_ERRORS_LO 0x0= 14C > +#define IPN3KE_10G_TX_STATS_IF_ERRORS_HI 0x0= 14D > +#define IPN3KE_10G_RX_STATS_IF_ERRORS_LO 0x0= 1CC > +#define IPN3KE_10G_RX_STATS_IF_ERRORS_HI 0x0= 1CD > +#define IPN3KE_10G_TX_STATS_UNICAST_FRAME_OK_LO > 0x014E > +#define IPN3KE_10G_TX_STATS_UNICAST_FRAME_OK_HI 0x0= 14F > +#define IPN3KE_10G_RX_STATS_UNICAST_FRAME_OK_LO > 0x01CE > +#define IPN3KE_10G_RX_STATS_UNICAST_FRAME_OK_HI > 0x01CF > +#define IPN3KE_10G_TX_STATS_UNICAST_FRAME_ERR_LO > 0x0150 > +#define IPN3KE_10G_TX_STATS_UNICAST_FRAME_ERR_HI > 0x0151 > +#define IPN3KE_10G_RX_STATS_UNICAST_FRAME_ERR_LO > 0x01D0 > +#define IPN3KE_10G_RX_STATS_UNICAST_FRAME_ERR_HI > 0x01D1 > +#define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_OK_LO > 0x0152 > +#define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_OK_HI > 0x0153 > +#define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_OK_LO > 0x01D2 > +#define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_OK_HI > 0x01D3 > +#define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_ERR_LO > 0x0154 > +#define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_ERR_HI > 0x0155 > +#define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_ERR_LO > 0x01D4 > +#define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_ERR_HI > 0x01D5 > +#define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_OK_LO > 0x0156 > +#define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_OK_HI > 0x0157 > +#define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_OK_LO > 0x01D6 > +#define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_OK_HI > 0x01D7 > +#define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_ERR_LO > 0x0158 > +#define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_ERR_HI > 0x0159 > +#define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_ERR_LO > 0x01D8 > +#define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_ERR_HI > 0x01D9 > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_OCTETS_LO > 0x015A > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_OCTETS_HI > 0x015B > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_OCTETS_LO > 0x01DA > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_OCTETS_HI > 0x01DB > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_LO 0x0= 15C > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_HI 0x0= 15D > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_LO 0x0= 1DC > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_HI 0x0= 1DD > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_LO > 0x015E > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_HI > 0x015F > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_LO > 0x01DE > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_HI > 0x01DF > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_OVER_SIZE_PKTS_LO > 0x0160 > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_OVER_SIZE_PKTS_HI > 0x0161 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_OVER_SIZE_PKTS_LO > 0x01E0 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_OVER_SIZE_PKTS_HI > 0x01E1 > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_64_OCTETS_LO > 0x0162 > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_64_OCTETS_HI > 0x0163 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_64_OCTETS_LO > 0x01E2 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_64_OCTETS_HI > 0x01E3 > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_LO > 0x0164 > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_HI > 0x0165 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_LO > 0x01E4 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_HI > 0x01E5 > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_LO > 0x0166 > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_HI > 0x0167 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_LO > 0x01E6 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_HI > 0x01E7 > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_LO > 0x0168 > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_HI > 0x0169 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_LO > 0x01E8 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_HI > 0x01E9 > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_LO > 0x016A > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_HI > 0x016B > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_LO > 0x01EA > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_HI > 0x01EB > +#define > IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_LO > 0x016C > +#define > IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_HI > 0x016D > +#define > IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_LO > 0x01EC > +#define > IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_HI > 0x01ED > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_LO > 0x016E > +#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_HI > 0x016F > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_LO > 0x01EE > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_HI > 0x01EF > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_FRAGMENTS_LO > 0x01E0 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_FRAGMENTS_HI > 0x01F1 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_JABBERS_LO > 0x01E2 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_JABBERS_HI > 0x01F3 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_CRC_ERR_LO > 0x01E4 > +#define IPN3KE_10G_RX_STATS_ETHER_STATS_CRC_ERR_HI > 0x01F5 > +#define IPN3KE_10G_TX_STATS_UNICAST_MAC_CTRL_FRAMES_LO > 0x0176 > +#define IPN3KE_10G_TX_STATS_UNICAST_MAC_CTRL_FRAMES_HI > 0x0177 > +#define IPN3KE_10G_RX_STATS_UNICAST_MAC_CTRL_FRAMES_LO > 0x01F6 > +#define IPN3KE_10G_RX_STATS_UNICAST_MAC_CTRL_FRAMES_HI > 0x01F7 > +#define IPN3KE_10G_TX_STATS_MULTICAST_MAC_CTRL_FRAMES_LO > 0x0178 > +#define IPN3KE_10G_TX_STATS_MULTICAST_MAC_CTRL_FRAMES_HI > 0x0179 > +#define IPN3KE_10G_RX_STATS_MULTICAST_MAC_CTRL_FRAMES_LO > 0x01F8 > +#define IPN3KE_10G_RX_STATS_MULTICAST_MAC_CTRL_FRAMES_HI > 0x01F9 > +#define IPN3KE_10G_TX_STATS_BROADCAST_MAC_CTRL_FRAMES_LO > 0x017A > +#define IPN3KE_10G_TX_STATS_BROADCAST_MAC_CTRL_FRAMES_HI > 0x017B > +#define IPN3KE_10G_RX_STATS_BROADCAST_MAC_CTRL_FRAMES_LO > 0x01FA > +#define IPN3KE_10G_RX_STATS_BROADCAST_MAC_CTRL_FRAMES_HI > 0x01FB > +#define IPN3KE_10G_TX_STATS_PFC_MAC_CTRL_FRAMES_LO > 0x017C > +#define IPN3KE_10G_TX_STATS_PFC_MAC_CTRL_FRAMES_HI > 0x017D > +#define IPN3KE_10G_RX_STATS_PFC_MAC_CTRL_FRAMES_LO > 0x01FC > +#define IPN3KE_10G_RX_STATS_PFC_MAC_CTRL_FRAMES_HI > 0x01FD >=20 > static inline void ipn3ke_xmac_tx_enable(struct ipn3ke_hw *hw, > uint32_t mac_num, uint32_t eth_group_sel) @@ -945,31 > +1004,62 @@ static inline void ipn3ke_xmac_smac_ovd_dis(struct > ipn3ke_hw *hw, > eth_group_sel); > } >=20 > -static inline void ipn3ke_xmac_tx_clr_stcs(struct ipn3ke_hw *hw, > - uint32_t mac_num, uint32_t eth_group_sel) > +static inline void ipn3ke_xmac_tx_clr_10G_stcs (struct ipn3ke_hw *hw, > +uint32_t mac_num, uint32_t eth_group_sel) > { > #define IPN3KE_XMAC_TX_CLR_STCS (1 & \ > - (IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK)) > + (IPN3KE_10G_TX_STATS_CLR_CLEAR_MASK)) >=20 > (*hw->f_mac_write)(hw, > IPN3KE_XMAC_TX_CLR_STCS, > - IPN3KE_MAC_TX_STATS_CLR, > + IPN3KE_10G_TX_STATS_CLR, > mac_num, > eth_group_sel); > } >=20 > -static inline void ipn3ke_xmac_rx_clr_stcs(struct ipn3ke_hw *hw, > - uint32_t mac_num, uint32_t eth_group_sel) > +static inline void ipn3ke_xmac_rx_clr_10G_stcs (struct ipn3ke_hw *hw, > +uint32_t mac_num, uint32_t eth_group_sel) > { > #define IPN3KE_XMAC_RX_CLR_STCS (1 & \ > - (IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK)) > + (IPN3KE_10G_RX_STATS_CLR_CLEAR_MASK)) >=20 > (*hw->f_mac_write)(hw, > IPN3KE_XMAC_RX_CLR_STCS, > - IPN3KE_MAC_RX_STATS_CLR, > + IPN3KE_10G_RX_STATS_CLR, > mac_num, > eth_group_sel); > } >=20 > +static inline void ipn3ke_xmac_tx_clr_25G_stcs (struct ipn3ke_hw *hw, > +uint32_t mac_num, uint32_t eth_group_sel) { > + uint32_t tmp =3D 0x00000001; > + > + /* Bit[0]: Software can set this bit to the value of 1 > + * to reset all of the TX statistics registers at the same time. > + * This bit is selfclearing. > + */ > + (*hw->f_mac_write)(hw, > + tmp, > + IPN3KE_25G_TX_STATISTICS_CONFIG, > + mac_num, > + eth_group_sel); > +} > + > +static inline void ipn3ke_xmac_rx_clr_25G_stcs (struct ipn3ke_hw *hw, > +uint32_t mac_num, uint32_t eth_group_sel) { > + uint32_t tmp =3D 0x00000001; > + > + /* Bit[0]: Software can set this bit to the value of 1 > + * to reset all of the RX statistics registers at the same time. > + * This bit is selfclearing. > + */ > + (*hw->f_mac_write)(hw, > + tmp, > + IPN3KE_25G_RX_STATISTICS_CONFIG, > + mac_num, > + eth_group_sel); > +} >=20 > #endif /* _IPN3KE_ETHDEV_H_ */ > -- > 1.8.3.1 Acked-by: Rosen Xu