From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D04CEC4649B for ; Fri, 5 Jul 2019 10:27:41 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id 7203220989 for ; Fri, 5 Jul 2019 10:27:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7203220989 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1C0DA1BE4F; Fri, 5 Jul 2019 12:27:31 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 46F101BE4E for ; Fri, 5 Jul 2019 12:27:30 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D284A2B; Fri, 5 Jul 2019 03:27:29 -0700 (PDT) Received: from phil-VirtualBox.shanghai.arm.com (unknown [10.169.109.155]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9D0003F703; Fri, 5 Jul 2019 03:27:27 -0700 (PDT) From: Phil Yang To: dev@dpdk.org Cc: thomas@monjalon.net, david.marchand@redhat.com, konstantin.ananyev@intel.com, jerinj@marvell.com, hemant.agrawal@nxp.com, Honnappa.Nagarahalli@arm.com, gavin.hu@arm.com, nd@arm.com, phil.yang@arm.com Date: Fri, 5 Jul 2019 18:27:07 +0800 Message-Id: <1562322429-18635-3-git-send-email-phil.yang@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1562322429-18635-1-git-send-email-phil.yang@arm.com> References: <1559750328-22377-2-git-send-email-phil.yang@arm.com> <1562322429-18635-1-git-send-email-phil.yang@arm.com> Subject: [dpdk-dev] [PATCH v3 2/3] eal/mcslock: use generic msc queued lock on all arch X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Let all architectures use generic MCS queued lock implementation. Signed-off-by: Phil Yang Reviewed-by: Gavin Hu Reviewed-by: Honnappa Nagarahalli --- .../common/include/arch/arm/rte_mcslock.h | 23 ++++++++++++++++++++++ .../common/include/arch/ppc_64/rte_mcslock.h | 19 ++++++++++++++++++ .../common/include/arch/x86/rte_mcslock.h | 19 ++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 lib/librte_eal/common/include/arch/arm/rte_mcslock.h create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_mcslock.h create mode 100644 lib/librte_eal/common/include/arch/x86/rte_mcslock.h diff --git a/lib/librte_eal/common/include/arch/arm/rte_mcslock.h b/lib/librte_eal/common/include/arch/arm/rte_mcslock.h new file mode 100644 index 0000000..5e41e32 --- /dev/null +++ b/lib/librte_eal/common/include/arch/arm/rte_mcslock.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Arm Limited + */ + +#ifndef _RTE_MCSLOCK_ARM_H_ +#define _RTE_MCSLOCK_ARM_H_ + +#ifndef RTE_FORCE_INTRINSICS +# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_mcslock.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_MCSLOCK_ARM_H_ */ + diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_mcslock.h b/lib/librte_eal/common/include/arch/ppc_64/rte_mcslock.h new file mode 100644 index 0000000..951b6dd --- /dev/null +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_mcslock.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Arm Limited + */ + +#ifndef _RTE_MCSLOCK_PPC_64_H_ +#define _RTE_MCSLOCK_PPC_64_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_mcslock.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_MCSLOCK_PPC_64_H_ */ + diff --git a/lib/librte_eal/common/include/arch/x86/rte_mcslock.h b/lib/librte_eal/common/include/arch/x86/rte_mcslock.h new file mode 100644 index 0000000..573b700 --- /dev/null +++ b/lib/librte_eal/common/include/arch/x86/rte_mcslock.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Arm Limited + */ + +#ifndef _RTE_MCSLOCK_X86_64_H_ +#define _RTE_MCSLOCK_X86_64_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_mcslock.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_MCSLOCK_X86_64_H_ */ + -- 2.7.4