From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FDE8C433DF for ; Tue, 28 Jul 2020 17:50:55 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id CDBE620672 for ; Tue, 28 Jul 2020 17:50:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CDBE620672 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mellanox.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 48577A69; Tue, 28 Jul 2020 19:50:53 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 82A0D3B5 for ; Tue, 28 Jul 2020 19:50:52 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from yuvalav@mellanox.com) with SMTP; 28 Jul 2020 20:50:48 +0300 Received: from pegasus04.mtr.labs.mlnx (pegasus04.mtr.labs.mlnx [10.210.16.126]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06SHomhN026504; Tue, 28 Jul 2020 20:50:48 +0300 Received: from pegasus04.mtr.labs.mlnx (localhost [127.0.0.1]) by pegasus04.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 06SHom2X066624; Tue, 28 Jul 2020 17:50:48 GMT Received: (from yuvalav@localhost) by pegasus04.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 06SHomZ8066621; Tue, 28 Jul 2020 17:50:48 GMT From: Yuval Avnery To: Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko Cc: thomas@monjalon.net, dev@dpdk.org, yuvalav@mellanox.com, orika@mellanox.com Date: Tue, 28 Jul 2020 17:50:44 +0000 Message-Id: <1595958644-66526-1-git-send-email-yuvalav@mellanox.com> X-Mailer: git-send-email 1.8.3.1 Subject: [dpdk-dev] [PATCH v1] common/mlx5: fix set regex register layout X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Reserved field should be 0x60 instead of 0x40. Will fail FW check otherwise. Fixes: be4f4a8b8e3b ("regex/mlx5: add engine status check") Signed-off-by: Yuval Avnery Acked-by: Ori Kam --- drivers/common/mlx5/mlx5_prm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 8fab962..c78b462 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2789,7 +2789,7 @@ struct mlx5_ifc_set_regexp_register_in_bits { u8 engine_id[0x8]; u8 register_address[0x20]; u8 register_data[0x20]; - u8 reserved[0x40]; + u8 reserved[0x60]; }; struct mlx5_ifc_set_regexp_register_out_bits { -- 1.8.3.1