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From: Lance Richardson <lance.richardson@broadcom.com>
To: dev@dpdk.org
Cc: ajit.khaparde@broadcom.com, ferruh.yigit@intel.com,
	maxime.coquelin@redhat.com,
	Lance Richardson <lance.richardson@broadcom.com>
Subject: [dpdk-dev] [PATCH v4 6/8] net/bnxt: update HWRM API to version 1.10.0.19
Date: Wed, 29 May 2019 11:02:32 -0400
Message-ID: <20190529150234.15166-7-lance.richardson@broadcom.com> (raw)
In-Reply-To: <20190529150234.15166-1-lance.richardson@broadcom.com>

From: Ajit Khaparde <ajit.khaparde@broadcom.com>

Update HWRM API to version 1.10.0.19

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
v3:
* Fixed headline in commit log.

 drivers/net/bnxt/hsi_struct_def_dpdk.h | 3112 +++++++++++++++++++-----
 1 file changed, 2514 insertions(+), 598 deletions(-)

diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index e80057936..ea9a7d40e 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2018 Broadcom Limited
+ * Copyright (c) 2014-2019 Broadcom Limited
  * All rights reserved.
  *
  * DO NOT MODIFY!!! This file is automatically generated.
@@ -68,9 +68,9 @@ struct hwrm_resp_hdr {
 /* RoCE slow path command */
 #define TLV_TYPE_ROCE_SP_COMMAND                 UINT32_C(0x3)
 /* RoCE slow path command to query CC Gen1 support. */
-#define TLV_TYPE_QUERY_ROCE_CC_GEN1              UINT32_C(0xcommand 0x0005)
+#define TLV_TYPE_QUERY_ROCE_CC_GEN1              UINT32_C(0x4)
 /* RoCE slow path command to modify CC Gen1 support. */
-#define TLV_TYPE_MODIFY_ROCE_CC_GEN1             UINT32_C(0xcommand 0x0005)
+#define TLV_TYPE_MODIFY_ROCE_CC_GEN1             UINT32_C(0x5)
 /* Engine CKV - The device's serial number. */
 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
 /* Engine CKV - Per-function random nonce data. */
@@ -366,6 +366,7 @@ struct cmd_nums {
 	#define HWRM_TUNNEL_DST_PORT_QUERY                UINT32_C(0xa0)
 	#define HWRM_TUNNEL_DST_PORT_ALLOC                UINT32_C(0xa1)
 	#define HWRM_TUNNEL_DST_PORT_FREE                 UINT32_C(0xa2)
+	#define HWRM_STAT_CTX_ENG_QUERY                   UINT32_C(0xaf)
 	#define HWRM_STAT_CTX_ALLOC                       UINT32_C(0xb0)
 	#define HWRM_STAT_CTX_FREE                        UINT32_C(0xb1)
 	#define HWRM_STAT_CTX_QUERY                       UINT32_C(0xb2)
@@ -442,6 +443,14 @@ struct cmd_nums {
 	#define HWRM_FW_IPC_MSG                           UINT32_C(0x110)
 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO        UINT32_C(0x111)
 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE       UINT32_C(0x112)
+	/* Experimental */
+	#define HWRM_CFA_FLOW_AGING_TIMER_RESET           UINT32_C(0x113)
+	/* Experimental */
+	#define HWRM_CFA_FLOW_AGING_CFG                   UINT32_C(0x114)
+	/* Experimental */
+	#define HWRM_CFA_FLOW_AGING_QCFG                  UINT32_C(0x115)
+	/* Experimental */
+	#define HWRM_CFA_FLOW_AGING_QCAPS                 UINT32_C(0x116)
 	/* Engine CKV - Ping the device and SRT firmware to get the public key. */
 	#define HWRM_ENGINE_CKV_HELLO                     UINT32_C(0x12d)
 	/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -591,61 +600,79 @@ struct cmd_nums {
 struct ret_codes {
 	uint16_t	error_code;
 	/* Request was successfully executed by the HWRM. */
-	#define HWRM_ERR_CODE_SUCCESS                UINT32_C(0x0)
+	#define HWRM_ERR_CODE_SUCCESS                   UINT32_C(0x0)
 	/* The HWRM failed to execute the request. */
-	#define HWRM_ERR_CODE_FAIL                   UINT32_C(0x1)
+	#define HWRM_ERR_CODE_FAIL                      UINT32_C(0x1)
 	/*
 	 * The request contains invalid argument(s) or input
 	 * parameters.
 	 */
-	#define HWRM_ERR_CODE_INVALID_PARAMS         UINT32_C(0x2)
+	#define HWRM_ERR_CODE_INVALID_PARAMS            UINT32_C(0x2)
 	/*
 	 * The requester is not allowed to access the requested
 	 * resource. This error code shall be provided in a
 	 * response to a request to query or modify an existing
 	 * resource that is not accessible by the requester.
 	 */
-	#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
+	#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED    UINT32_C(0x3)
 	/*
 	 * The HWRM is unable to allocate the requested resource.
 	 * This code only applies to requests for HWRM resource
 	 * allocations.
 	 */
-	#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR   UINT32_C(0x4)
+	#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR      UINT32_C(0x4)
 	/*
 	 * Invalid combination of flags is specified in the
 	 * request.
 	 */
-	#define HWRM_ERR_CODE_INVALID_FLAGS          UINT32_C(0x5)
+	#define HWRM_ERR_CODE_INVALID_FLAGS             UINT32_C(0x5)
 	/*
 	 * Invalid combination of enables fields is specified in
 	 * the request.
 	 */
-	#define HWRM_ERR_CODE_INVALID_ENABLES        UINT32_C(0x6)
+	#define HWRM_ERR_CODE_INVALID_ENABLES           UINT32_C(0x6)
 	/*
 	 * Request contains a required TLV that is not supported by
 	 * the installed version of firmware.
 	 */
-	#define HWRM_ERR_CODE_UNSUPPORTED_TLV        UINT32_C(0x7)
+	#define HWRM_ERR_CODE_UNSUPPORTED_TLV           UINT32_C(0x7)
 	/*
 	 * No firmware buffer available to accept the request. Driver
 	 * should retry the request.
 	 */
-	#define HWRM_ERR_CODE_NO_BUFFER              UINT32_C(0x8)
+	#define HWRM_ERR_CODE_NO_BUFFER                 UINT32_C(0x8)
 	/*
 	 * This error code is only reported by firmware when some
 	 * sub-option of a supported HWRM command is unsupported.
 	 */
-	#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+	#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR    UINT32_C(0x9)
+	/*
+	 * This error code is only reported by firmware when the specific
+	 * request is not able to process when the HOT reset in progress.
+	 */
+	#define HWRM_ERR_CODE_HOT_RESET_PROGRESS        UINT32_C(0xa)
+	/*
+	 * This error code is only reported by firmware when the registered
+	 * driver instances are not capable of hot reset.
+	 */
+	#define HWRM_ERR_CODE_HOT_RESET_FAIL            UINT32_C(0xb)
 	/*
 	 * Generic HWRM execution error that represents an
 	 * internal error.
 	 */
-	#define HWRM_ERR_CODE_HWRM_ERROR             UINT32_C(0xf)
+	#define HWRM_ERR_CODE_HWRM_ERROR                UINT32_C(0xf)
+	/*
+	 * This value indicates that the HWRM response is in TLV format and
+	 * should be interpreted as one or more TLVs starting with the
+	 * hwrm_resp_hdr TLV. This value is not an indicatation of any error
+	 * by itself, just an indicatation that the response should be parsed
+	 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
+	 */
+	#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
 	/* Unknown error */
-	#define HWRM_ERR_CODE_UNKNOWN_ERR            UINT32_C(0xfffe)
+	#define HWRM_ERR_CODE_UNKNOWN_ERR               UINT32_C(0xfffe)
 	/* Unsupported or invalid command */
-	#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED      UINT32_C(0xffff)
+	#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED         UINT32_C(0xffff)
 	#define HWRM_ERR_CODE_LAST \
 		HWRM_ERR_CODE_CMD_NOT_SUPPORTED
 	uint16_t	unused_0[3];
@@ -705,11 +732,11 @@ struct hwrm_err_output {
 /* valid key for HWRM response */
 #define HWRM_RESP_VALID_KEY 1
 #define HWRM_VERSION_MAJOR 1
-#define HWRM_VERSION_MINOR 9
-#define HWRM_VERSION_UPDATE 2
+#define HWRM_VERSION_MINOR 10
+#define HWRM_VERSION_UPDATE 0
 /* non-zero means beta version */
-#define HWRM_VERSION_RSVD 53
-#define HWRM_VERSION_STR "1.9.2.53"
+#define HWRM_VERSION_RSVD 19
+#define HWRM_VERSION_STR "1.10.0.19"
 
 /****************
  * hwrm_ver_get *
@@ -959,6 +986,13 @@ struct hwrm_ver_get_output {
 	 */
 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
 		UINT32_C(0x100)
+	/*
+	 * If set to 1, firmware is capable to support flow aging.
+	 * If set to 0, firmware is not capable to support flow aging.
+	 * By default, this flag should be 0 for older version of core firmware.
+	 */
+	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
+		UINT32_C(0x200)
 	/*
 	 * This field represents the major version of RoCE firmware.
 	 * A change in major version represents a major release.
@@ -2031,7 +2065,7 @@ struct cmpl_base {
 	#define CMPL_BASE_TYPE_SFT             0
 	/*
 	 * TX L2 completion:
-	 *  Completion of TX packet.  Length = 16B
+	 * Completion of TX packet.  Length = 16B
 	 */
 	#define CMPL_BASE_TYPE_TX_L2             UINT32_C(0x0)
 	/*
@@ -2116,7 +2150,7 @@ struct tx_cmpl {
 	#define TX_CMPL_TYPE_SFT        0
 	/*
 	 * TX L2 completion:
-	 *  Completion of TX packet.  Length = 16B
+	 * Completion of TX packet.  Length = 16B
 	 */
 	#define TX_CMPL_TYPE_TX_L2        UINT32_C(0x0)
 	#define TX_CMPL_TYPE_LAST        TX_CMPL_TYPE_TX_L2
@@ -2408,30 +2442,31 @@ struct rx_pkt_cmpl_hi {
 	 * inner packet and that the ip_cs_error field indicates if there
 	 * was an error.
 	 */
-	#define RX_PKT_CMPL_FLAGS2_IP_CS_CALC       UINT32_C(0x1)
+	#define RX_PKT_CMPL_FLAGS2_IP_CS_CALC                 UINT32_C(0x1)
 	/*
 	 * This indicates that the TCP, UDP or ICMP checksum was
 	 * calculated for the inner packet and that the l4_cs_error field
 	 * indicates if there was an error.
 	 */
-	#define RX_PKT_CMPL_FLAGS2_L4_CS_CALC       UINT32_C(0x2)
+	#define RX_PKT_CMPL_FLAGS2_L4_CS_CALC                 UINT32_C(0x2)
 	/*
 	 * This indicates that the ip checksum was calculated for the
 	 * tunnel header and that the t_ip_cs_error field indicates if there
 	 * was an error.
 	 */
-	#define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC     UINT32_C(0x4)
+	#define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC               UINT32_C(0x4)
 	/*
 	 * This indicates that the UDP checksum was
 	 * calculated for the tunnel packet and that the t_l4_cs_error field
 	 * indicates if there was an error.
 	 */
-	#define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC     UINT32_C(0x8)
+	#define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC               UINT32_C(0x8)
 	/* This value indicates what format the metadata field is. */
-	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
-	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT  4
+	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK           UINT32_C(0xf0)
+	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT            4
 	/* No metadata informtaion.  Value is zero. */
-	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE   (UINT32_C(0x0) << 4)
+	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
+		(UINT32_C(0x0) << 4)
 	/*
 	 * The metadata field contains the VLAN tag and TPID value.
 	 * - metadata[11:0] contains the vlan VID value.
@@ -2439,16 +2474,70 @@ struct rx_pkt_cmpl_hi {
 	 * - metadata[15:13] contains the vlan PRI value.
 	 * - metadata[31:16] contains the vlan TPID value.
 	 */
-	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN   (UINT32_C(0x1) << 4)
+	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
+		(UINT32_C(0x1) << 4)
+	/*
+	 * If ext_meta_format is equal to 1, the metadata field
+	 * contains the lower 16b of the tunnel ID value, justified
+	 * to LSB
+	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
+	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
+	 * - NVGRE = TNI[23:0] -> Tenant Network ID
+	 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+	 * - IPV4 = 0 (not populated)
+	 * - IPV6 = Flow Label[19:0]
+	 * - PPPoE = sessionID[15:0]
+	 * - MPLs = Outer label[19:0]
+	 * - UPAR = Selected[31:0] with bit mask
+	 */
+	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+		(UINT32_C(0x2) << 4)
+	/*
+	 * if ext_meta_format is equal to 1, metadata field contains
+	 * 16b metadata from the prepended header (chdr_data).
+	 */
+	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+		(UINT32_C(0x3) << 4)
+	/*
+	 * If ext_meta_format is equal to 1, the metadata field contains
+	 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
+	 * inner_l4_size.
+	 * - metadata[8:0] contains the outer_l3_offset.
+	 * - metadata[17:9] contains the inner_l2_offset.
+	 * - metadata[26:18] contains the inner_l3_offset.
+	 * - metadata[31:27] contains the inner_l4_size.
+	 */
+	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+		(UINT32_C(0x4) << 4)
 	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
-		RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
+		RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
 	/*
 	 * This field indicates the IP type for the inner-most IP header.
 	 * A value of '0' indicates IPv4.  A value of '1' indicates IPv6.
 	 * This value is only valid if itype indicates a packet
 	 * with an IP header.
 	 */
-	#define RX_PKT_CMPL_FLAGS2_IP_TYPE          UINT32_C(0x100)
+	#define RX_PKT_CMPL_FLAGS2_IP_TYPE                    UINT32_C(0x100)
+	/*
+	 * This indicates that the complete 1's complement checksum was
+	 * calculated for the packet.
+	 */
+	#define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC     UINT32_C(0x200)
+	/*
+	 * The combination of this value and meta_format indicated what
+	 * format the metadata field is.
+	 */
+	#define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK       UINT32_C(0xc00)
+	#define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT        10
+	/*
+	 * This value is the complete 1's complement checksum calculated from
+	 * the start of the outer L3 header to the end of the packet (not
+	 * including the ethernet crc). It is valid when the
+	 * 'complete_checksum_calc' flag is set.
+	 */
+	#define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+		UINT32_C(0xffff0000)
+	#define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT      16
 	/*
 	 * This is data from the CFA block as indicated by the meta_format
 	 * field.
@@ -2511,8 +2600,14 @@ struct rx_pkt_cmpl_hi {
 	 */
 	#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
 		(UINT32_C(0x3) << 1)
+	/*
+	 * Flush:
+	 * There was a bad_format error on the previous operation
+	 */
+	#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+		(UINT32_C(0x5) << 1)
 	#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
-		RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
+		RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
 	/*
 	 * This indicates that there was an error in the IP header
 	 * checksum.
@@ -2553,7 +2648,7 @@ struct rx_pkt_cmpl_hi {
 	#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT                    9
 	/*
 	 * No additional error occurred on the tunnel portion
-	 * of the packet of the packet does not have a tunnel.
+	 * or the packet of the packet does not have a tunnel.
 	 */
 	#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
 		(UINT32_C(0x0) << 9)
@@ -2611,7 +2706,7 @@ struct rx_pkt_cmpl_hi {
 	#define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT                      12
 	/*
 	 * No additional error occurred on the tunnel portion
-	 * of the packet of the packet does not have a tunnel.
+	 * or the packet of the packet does not have a tunnel.
 	 */
 	#define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
 		(UINT32_C(0x0) << 12)
@@ -2854,28 +2949,33 @@ struct rx_tpa_start_cmpl_hi {
 	 * inner packet and that the sum passed for all segments
 	 * included in the aggregation.
 	 */
-	#define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC       UINT32_C(0x1)
+	#define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC \
+		UINT32_C(0x1)
 	/*
 	 * This indicates that the TCP, UDP or ICMP checksum was
 	 * calculated for the inner packet and that the sum passed
 	 * for all segments included in the aggregation.
 	 */
-	#define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC       UINT32_C(0x2)
+	#define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC \
+		UINT32_C(0x2)
 	/*
 	 * This indicates that the ip checksum was calculated for the
 	 * tunnel header and that the sum passed for all segments
 	 * included in the aggregation.
 	 */
-	#define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC     UINT32_C(0x4)
+	#define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC \
+		UINT32_C(0x4)
 	/*
 	 * This indicates that the UDP checksum was
 	 * calculated for the tunnel packet and that the sum passed for
 	 * all segments included in the aggregation.
 	 */
-	#define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC     UINT32_C(0x8)
+	#define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC \
+		UINT32_C(0x8)
 	/* This value indicates what format the metadata field is. */
-	#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
-	#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT  4
+	#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK \
+		UINT32_C(0xf0)
+	#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT            4
 	/* No metadata informtaion.  Value is zero. */
 	#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
 		(UINT32_C(0x0) << 4)
@@ -2888,13 +2988,71 @@ struct rx_tpa_start_cmpl_hi {
 	 */
 	#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
 		(UINT32_C(0x1) << 4)
+	/*
+	 * If ext_meta_format is equal to 1, the metadata field
+	 * contains the lower 16b of the tunnel ID value, justified
+	 * to LSB
+	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
+	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
+	 * - NVGRE = TNI[23:0] -> Tenant Network ID
+	 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+	 * - IPV4 = 0 (not populated)
+	 * - IPV6 = Flow Label[19:0]
+	 * - PPPoE = sessionID[15:0]
+	 * - MPLs = Outer label[19:0]
+	 * - UPAR = Selected[31:0] with bit mask
+	 */
+	#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+		(UINT32_C(0x2) << 4)
+	/*
+	 * if ext_meta_format is equal to 1, metadata field contains
+	 * 16b metadata from the prepended header (chdr_data).
+	 */
+	#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+		(UINT32_C(0x3) << 4)
+	/*
+	 * If ext_meta_format is equal to 1, the metadata field contains
+	 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
+	 * inner_l4_size.
+	 * - metadata[8:0] contains the outer_l3_offset.
+	 * - metadata[17:9] contains the inner_l2_offset.
+	 * - metadata[26:18] contains the inner_l3_offset.
+	 * - metadata[31:27] contains the inner_l4_size.
+	 */
+	#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+		(UINT32_C(0x4) << 4)
 	#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
-		RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
+		RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
 	/*
 	 * This field indicates the IP type for the inner-most IP header.
 	 * A value of '0' indicates IPv4.  A value of '1' indicates IPv6.
 	 */
-	#define RX_TPA_START_CMPL_FLAGS2_IP_TYPE          UINT32_C(0x100)
+	#define RX_TPA_START_CMPL_FLAGS2_IP_TYPE \
+		UINT32_C(0x100)
+	/*
+	 * This indicates that the complete 1's complement checksum was
+	 * calculated for the packet.
+	 */
+	#define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
+		UINT32_C(0x200)
+	/*
+	 * The combination of this value and meta_format indicated what
+	 * format the metadata field is.
+	 */
+	#define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
+		UINT32_C(0xc00)
+	#define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT        10
+	/*
+	 * This value is the complete 1's complement checksum calculated from
+	 * the start of the outer L3 header to the end of the packet (not
+	 * including the ethernet crc). It is valid when the
+	 * 'complete_checksum_calc' flag is set. For TPA Start completions,
+	 * the complete checksum is calculated for the first packet in the
+	 * aggregation only.
+	 */
+	#define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+		UINT32_C(0xffff0000)
+	#define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT      16
 	/*
 	 * This is data from the CFA block as indicated by the meta_format
 	 * field.
@@ -2911,13 +3069,41 @@ struct rx_tpa_start_cmpl_hi {
 	/* When meta_format=1, this value is the VLAN TPID. */
 	#define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
 	#define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
-	uint16_t	v2;
+	uint16_t	errors_v2;
 	/*
 	 * This value is written by the NIC such that it will be different
 	 * for each pass through the completion queue.   The even passes
 	 * will write 1.  The odd passes will write 0.
 	 */
-	#define RX_TPA_START_CMPL_V2     UINT32_C(0x1)
+	#define RX_TPA_START_CMPL_V2                            UINT32_C(0x1)
+	#define RX_TPA_START_CMPL_ERRORS_MASK \
+		UINT32_C(0xfffe)
+	#define RX_TPA_START_CMPL_ERRORS_SFT                    1
+	/*
+	 * This error indicates that there was some sort of problem with
+	 * the BDs for the packet that was found after part of the
+	 * packet was already placed.  The packet should be treated as
+	 * invalid.
+	 */
+	#define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_MASK       UINT32_C(0xe)
+	#define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_SFT        1
+	/* No buffer error */
+	#define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+		(UINT32_C(0x0) << 1)
+	/*
+	 * Bad Format:
+	 * BDs were not formatted correctly.
+	 */
+	#define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+		(UINT32_C(0x3) << 1)
+	/*
+	 * Flush:
+	 * There was a bad_format error on the previous operation
+	 */
+	#define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+		(UINT32_C(0x5) << 1)
+	#define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
+		RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
 	/*
 	 * This field identifies the CFA action rule that was used for this
 	 * packet.
@@ -3034,11 +3220,11 @@ struct rx_tpa_end_cmpl {
 	/*
 	 * This value indicates what the inner packet determined for the
 	 * packet was.
-	 *  - 2 TCP Packet
-	 *      Indicates that the packet was IP and TCP.  This indicates
-	 *      that the ip_cs field is valid and that the tcp_udp_cs
-	 *      field is valid and contains the TCP checksum.
-	 *      This also indicates that the payload_offset field is valid.
+	 * - 2 TCP Packet
+	 *     Indicates that the packet was IP and TCP.  This indicates
+	 *     that the ip_cs field is valid and that the tcp_udp_cs
+	 *     field is valid and contains the TCP checksum.
+	 *     This also indicates that the payload_offset field is valid.
 	 */
 	#define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK          UINT32_C(0xf000)
 	#define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT           12
@@ -3117,13 +3303,28 @@ struct rx_tpa_end_cmpl_hi {
 	 * This value is the number of duplicate ACKs that have been
 	 * received as part of the TPA operation.
 	 */
-	uint32_t	tpa_dup_acks;
+	uint16_t	tpa_dup_acks;
 	/*
 	 * This value is the number of duplicate ACKs that have been
 	 * received as part of the TPA operation.
 	 */
 	#define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
 	#define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
+	/*
+	 * This value indicated the offset in bytes from the beginning of
+	 * the packet where the inner payload starts. This value is valid
+	 * for TCP, UDP, FCoE and RoCE packets
+	 */
+	uint8_t	payload_offset;
+	/*
+	 * The value is the total number of aggregation buffers that were
+	 * used in the TPA operation. All TPA aggregation buffer completions
+	 * preceed the TPA End completion. If the value is zero, then the
+	 * aggregation is completely contained in the buffer space provided
+	 * in the aggregation start completion.
+	 * Note that the field is simply provided as a cross check.
+	 */
+	uint8_t	tpa_agg_bufs;
 	/*
 	 * This value is the valid when TPA completion is active.  It
 	 * indicates the length of the longest segment of the TPA operation
@@ -3154,6 +3355,9 @@ struct rx_tpa_end_cmpl_hi {
 	 */
 	#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK        UINT32_C(0xe)
 	#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT         1
+	/* No buffer error */
+	#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+		(UINT32_C(0x0) << 1)
 	/*
 	 * This error occurs when there is a fatal HW problem in
 	 * the chip only.  It indicates that there were not
@@ -3162,6 +3366,12 @@ struct rx_tpa_end_cmpl_hi {
 	 */
 	#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
 		(UINT32_C(0x2) << 1)
+	/*
+	 * Bad Format:
+	 * BDs were not formatted correctly.
+	 */
+	#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+		(UINT32_C(0x3) << 1)
 	/*
 	 * This error occurs when TPA block was not configured to
 	 * reserve adequate BDs for TPA operations on this RX
@@ -3174,8 +3384,14 @@ struct rx_tpa_end_cmpl_hi {
 	 */
 	#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
 		(UINT32_C(0x4) << 1)
+	/*
+	 * Flush:
+	 * There was a bad_format error on the previous operation
+	 */
+	#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+		(UINT32_C(0x5) << 1)
 	#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
-		RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
+		RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
 	/* unused5 is 16 b */
 	uint16_t	unused_4;
 	/*
@@ -3239,15 +3455,23 @@ struct eject_cmpl {
 	 * records.  Odd values indicate 32B
 	 * records.
 	 */
-	#define EJECT_CMPL_TYPE_MASK      UINT32_C(0x3f)
-	#define EJECT_CMPL_TYPE_SFT       0
+	#define EJECT_CMPL_TYPE_MASK       UINT32_C(0x3f)
+	#define EJECT_CMPL_TYPE_SFT        0
 	/*
 	 * Statistics Ejection Completion:
 	 * Completion of statistics data ejection buffer.
 	 * Length = 16B
 	 */
-	#define EJECT_CMPL_TYPE_STAT_EJECT  UINT32_C(0x1a)
-	#define EJECT_CMPL_TYPE_LAST       EJECT_CMPL_TYPE_STAT_EJECT
+	#define EJECT_CMPL_TYPE_STAT_EJECT   UINT32_C(0x1a)
+	#define EJECT_CMPL_TYPE_LAST        EJECT_CMPL_TYPE_STAT_EJECT
+	#define EJECT_CMPL_FLAGS_MASK      UINT32_C(0xffc0)
+	#define EJECT_CMPL_FLAGS_SFT       6
+	/*
+	 * When this bit is '1', it indicates a packet that has an
+	 * error of some type.  Type of error is indicated in
+	 * error_flags.
+	 */
+	#define EJECT_CMPL_FLAGS_ERROR      UINT32_C(0x40)
 	/*
 	 * This is the length of the statistics data stored in this
 	 * buffer.
@@ -3258,13 +3482,47 @@ struct eject_cmpl {
 	 * buffer corresponds to.
 	 */
 	uint32_t	opaque;
-	uint32_t	v;
+	uint16_t	v;
 	/*
 	 * This value is written by the NIC such that it will be different
 	 * for each pass through the completion queue.   The even passes
 	 * will write 1.  The odd passes will write 0.
 	 */
-	#define EJECT_CMPL_V     UINT32_C(0x1)
+	#define EJECT_CMPL_V                              UINT32_C(0x1)
+	#define EJECT_CMPL_ERRORS_MASK                    UINT32_C(0xfffe)
+	#define EJECT_CMPL_ERRORS_SFT                     1
+	/*
+	 * This error indicates that there was some sort of problem with
+	 * the BDs for statistics ejection. The statistics ejection should
+	 * be treated as invalid
+	 */
+	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK        UINT32_C(0xe)
+	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT         1
+	/* No buffer error */
+	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+		(UINT32_C(0x0) << 1)
+	/*
+	 * Did Not Fit:
+	 * Statistics did not fit into aggregation buffer provided.
+	 */
+	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
+		(UINT32_C(0x1) << 1)
+	/*
+	 * Bad Format:
+	 * BDs were not formatted correctly.
+	 */
+	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+		(UINT32_C(0x3) << 1)
+	/*
+	 * Flush:
+	 * There was a bad_format error on the previous operation
+	 */
+	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+		(UINT32_C(0x5) << 1)
+	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
+		EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
+	/* reserved16 is 16 b */
+	uint16_t	reserved16;
 	/* unused3 is 32 b */
 	uint32_t	unused_2;
 } __attribute__((packed));
@@ -3470,6 +3728,24 @@ struct hwrm_async_event_cmpl {
 	/* Default VNIC Configuration Change */
 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
 		UINT32_C(0x35)
+	/* HW flow aged */
+	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
+		UINT32_C(0x36)
+	/*
+	 * A debug notification being posted to the driver. These
+	 * notifications are purely for diagnostic purpose and should not be
+	 * used for functional purpose. The driver is not supposed to act
+	 * on these messages except to log/record it.
+	 */
+	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
+		UINT32_C(0x37)
+	/*
+	 * A trace log message. This contains firmware trace logs string
+	 * embedded in the asynchronous message. This is an experimental
+	 * event, not meant for production use at this time.
+	 */
+	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
+		UINT32_C(0xfe)
 	/* HWRM Error */
 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
 		UINT32_C(0xff)
@@ -4111,9 +4387,19 @@ struct hwrm_async_event_cmpl_reset_notify {
 	/* opaque is 7 b */
 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
-	/* 8-lsb timestamp from POR (100-msec resolution) */
+	/*
+	 * 8-lsb timestamp (100-msec resolution)
+	 * The Minimum time required for the Firmware readiness after sending this
+	 * notification to the driver instances.
+	 */
 	uint8_t	timestamp_lo;
-	/* 16-lsb timestamp from POR (100-msec resolution) */
+	/*
+	 * 16-lsb timestamp (100-msec resolution)
+	 * The Maximum Firmware Reset bail out value in the order of 100
+	 * milli seconds. The driver instances will use this value to re-initiate the
+	 * registration process again if the core firmware didn’t set the ready
+	 * state bit.
+	 */
 	uint16_t	timestamp_hi;
 	/* Event specific data */
 	uint32_t	event_data1;
@@ -4829,6 +5115,73 @@ struct hwrm_async_event_cmpl_default_vnic_change {
 		10
 } __attribute__((packed));
 
+/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
+struct hwrm_async_event_cmpl_hw_flow_aged {
+	uint16_t	type;
+	/*
+	 * This field indicates the exact type of the completion.
+	 * By convention, the LSB identifies the length of the
+	 * record in 16B units.  Even values indicate 16B
+	 * records.  Odd values indicate 32B
+	 * records.
+	 */
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
+		UINT32_C(0x3f)
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT             0
+	/* HWRM Asynchronous Event Information */
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
+		UINT32_C(0x2e)
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
+		HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
+	/* Identifiers of events. */
+	uint16_t	event_id;
+	/* Notification of a hw flow aged */
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
+		UINT32_C(0x36)
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
+		HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
+	/* Event specific data */
+	uint32_t	event_data2;
+	uint8_t	opaque_v;
+	/*
+	 * This value is written by the NIC such that it will be different
+	 * for each pass through the completion queue.   The even passes
+	 * will write 1.  The odd passes will write 0.
+	 */
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V          UINT32_C(0x1)
+	/* opaque is 7 b */
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
+	/* 8-lsb timestamp from POR (100-msec resolution) */
+	uint8_t	timestamp_lo;
+	/* 16-lsb timestamp from POR (100-msec resolution) */
+	uint16_t	timestamp_hi;
+	/* Event specific data */
+	uint32_t	event_data1;
+	/* Indicates flow ID this event occured on. */
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
+		UINT32_C(0x7fffffff)
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
+		0
+	/* Indicates flow direction this event occured on. */
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
+		UINT32_C(0x80000000)
+	/*
+	 * If this bit set to 0, then it indicates that the aged
+	 * event was rx flow.
+	 */
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
+		(UINT32_C(0x0) << 31)
+	/*
+	 * If this bit is set to 1, then it indicates that the aged
+	 * event was tx flow.
+	 */
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
+		(UINT32_C(0x1) << 31)
+	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
+		HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
+} __attribute__((packed));
+
 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
 struct hwrm_async_event_cmpl_hwrm_error {
 	uint16_t	type;
@@ -5682,7 +6035,7 @@ struct hwrm_func_qcaps_output {
 	/*
 	 * If the query is for a VF, then this flag shall be ignored,
 	 * If this query is for a PF and this flag is set to 1,
-	 * then the PF has the capability to administer another PF.
+	 * then the PF has the administrative privilege to configure another PF
 	 */
 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
 		UINT32_C(0x40000)
@@ -5700,6 +6053,19 @@ struct hwrm_func_qcaps_output {
 	 */
 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
 		UINT32_C(0x100000)
+	/*
+	 * If 1, then FW has capability to allocate TX rings dynamically
+	 * in ring alloc even if PF reserved pool is zero.
+	 * This bit will be used only for PFs.
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
+		UINT32_C(0x200000)
+	/*
+	 * When this bit is '1', it indicates that core firmware is
+	 * capable of Hot Reset.
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
+		UINT32_C(0x400000)
 	/*
 	 * This value is current MAC address configured for this
 	 * function. A value of 00-00-00-00-00-00 indicates no
@@ -5864,7 +6230,7 @@ struct hwrm_func_qcfg_input {
 	uint8_t	unused_0[6];
 } __attribute__((packed));
 
-/* hwrm_func_qcfg_output (size:640b/80B) */
+/* hwrm_func_qcfg_output (size:704b/88B) */
 struct hwrm_func_qcfg_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
@@ -5951,6 +6317,13 @@ struct hwrm_func_qcfg_output {
 	 */
 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
 		UINT32_C(0x40)
+	/*
+	 * If set to 1, then secure mode is enabled for this function or device.
+	 * If set to 0, then secure mode is disabled (or normal mode) for this
+	 * function or device.
+	 */
+	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
+		UINT32_C(0x80)
 	/*
 	 * This value is current MAC address configured for this
 	 * function. A value of 00-00-00-00-00-00 indicates no
@@ -5995,7 +6368,8 @@ struct hwrm_func_qcfg_output {
 	uint16_t	alloc_vnics;
 	/*
 	 * The maximum transmission unit of the function.
-	 * For rings allocated on this function, this default
+	 * If the reported mtu value is non-zero then it will used for the
+	 * rings allocated on this function. otherwise the default
 	 * value is used if ring MTU is not specified.
 	 */
 	uint16_t	mtu;
@@ -6222,7 +6596,27 @@ struct hwrm_func_qcfg_output {
 	 * reserved for itself (since the NQs must be contiguous in HW).
 	 */
 	uint16_t	alloc_msix;
-	uint8_t	unused_2[5];
+	/*
+	 * The number of registered VF’s associated with the PF. This field
+	 * should be ignored when the request received on the VF interface.
+	 * This field will be updated on the PF interface to initiate
+	 * the unregister request on PF in the HOT Reset Process.
+	 */
+	uint16_t	registered_vfs;
+	uint8_t	unused_1[3];
+	/*
+	 * For backward compatibility this field must be set to 1.
+	 * Older drivers might look for this field to be 1 before
+	 * processing the message.
+	 */
+	uint8_t	always_1;
+	/*
+	 * This GRC address location is used by the Host driver interfaces to poll
+	 * the adapter ready state to re-initiate the registration process again
+	 * after receiving the RESET Notify event.
+	 */
+	uint32_t	reset_addr_poll;
+	uint8_t	unused_2[3];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -6424,6 +6818,13 @@ struct hwrm_func_cfg_input {
 	 */
 	#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
 		UINT32_C(0x200000)
+	/*
+	 * When this bit it set, even if PF reserved pool size is zero,
+	 * FW will allow driver to create TX rings in ring alloc,
+	 * by reserving TX ring, S3 node dynamically.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
+		UINT32_C(0x400000)
 	uint32_t	enables;
 	/*
 	 * This bit must be '1' for the mtu field to be
@@ -7181,6 +7582,17 @@ struct hwrm_func_drv_rgtr_input {
 	 */
 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
 		UINT32_C(0x8)
+	/*
+	 * When this bit is '1', the function is indicating support of
+	 * Hot Reset. The driver interface will destroy the resources,
+	 * unregister the function and register again up on receiving
+	 * the RESET_NOTIFY Async notification from the core firmware.
+	 * The core firmware will this use flag and trigger the Hot Reset
+	 * process only if all the registered driver instances are capable
+	 * of this support.
+	 */
+	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
+		UINT32_C(0x10)
 	uint32_t	enables;
 	/*
 	 * This bit must be '1' for the os_type field to be
@@ -10774,6 +11186,8 @@ struct hwrm_port_phy_cfg_input {
 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB  UINT32_C(0x1f4)
 	/* 100Gb link speed */
 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
+	/* 200Gb link speed */
+	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
 	/* 10Mb link speed */
 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB  UINT32_C(0xffff)
 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
@@ -10878,6 +11292,8 @@ struct hwrm_port_phy_cfg_input {
 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB  UINT32_C(0x1f4)
 	/* 100Gb link speed */
 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+	/* 200Gb link speed */
+	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
 	/* 10Mb link speed */
 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB  UINT32_C(0xffff)
 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
@@ -10930,6 +11346,9 @@ struct hwrm_port_phy_cfg_input {
 	/* 10Mb link speed (Full-duplex) */
 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
 		UINT32_C(0x2000)
+	/* 200Gb link speed */
+	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
+		UINT32_C(0x4000)
 	/* This value controls the wirespeed feature. */
 	uint8_t	wirespeed;
 	/* Wirespeed feature is disabled. */
@@ -11159,6 +11578,8 @@ struct hwrm_port_phy_qcfg_output {
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB  UINT32_C(0x1f4)
 	/* 100Gb link speed */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
+	/* 200Gb link speed */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
 	/* 10Mb link speed */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB  UINT32_C(0xffff)
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
@@ -11238,6 +11659,9 @@ struct hwrm_port_phy_qcfg_output {
 	/* 10Mb link speed (Full-duplex) */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
 		UINT32_C(0x2000)
+	/* 200Gb link speed */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
+		UINT32_C(0x4000)
 	/*
 	 * Current setting of forced link speed.
 	 * When the link speed is not being forced, this
@@ -11267,6 +11691,9 @@ struct hwrm_port_phy_qcfg_output {
 	/* 100Gb link speed */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
 		UINT32_C(0x3e8)
+	/* 200Gb link speed */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
+		UINT32_C(0x7d0)
 	/* 10Mb link speed */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
 		UINT32_C(0xffff)
@@ -11353,6 +11780,8 @@ struct hwrm_port_phy_qcfg_output {
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB  UINT32_C(0x1f4)
 	/* 100Gb link speed */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+	/* 200Gb link speed */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
 	/* 10Mb link speed */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
 		UINT32_C(0xffff)
@@ -11408,6 +11837,9 @@ struct hwrm_port_phy_qcfg_output {
 	/* 10Mb link speed (Full-duplex) */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
 		UINT32_C(0x2000)
+	/* 200Gb link speed */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
+		UINT32_C(0x4000)
 	/* Current setting for wirespeed. */
 	uint8_t	wirespeed;
 	/* Wirespeed feature is disabled. */
@@ -11574,8 +12006,20 @@ struct hwrm_port_phy_qcfg_output {
 	/* 1G_baseCX */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
 		UINT32_C(0x1b)
+	/* 100G_BASECR4 */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
+		UINT32_C(0x1c)
+	/* 100G_BASESR4 */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
+		UINT32_C(0x1d)
+	/* 100G_BASELR4 */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
+		UINT32_C(0x1e)
+	/* 100G_BASEER4 */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
+		UINT32_C(0x1f)
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
-		HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX
+		HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
 	/* This value represents a media type. */
 	uint8_t	media_type;
 	/* Unknown */
@@ -21081,6 +21525,15 @@ struct hwrm_cfa_l2_filter_alloc_input {
 	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
 		UINT32_C(0x9)
+	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
 	/* Any tunneled traffic */
 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
 		UINT32_C(0xff)
@@ -21887,6 +22340,15 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
 	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
 		UINT32_C(0x9)
+	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
 	/* Any tunneled traffic */
 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
 		UINT32_C(0xff)
@@ -22107,6 +22569,12 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
 	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
 		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
 	/* Any tunneled traffic */
 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
 		UINT32_C(0xff)
@@ -22212,6 +22680,12 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
 	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
 		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
 	/* Any tunneled traffic */
 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
 		UINT32_C(0xff)
@@ -22312,6 +22786,12 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
 	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
 		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
 	/* Any tunneled traffic */
 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
 		UINT32_C(0xff)
@@ -22517,8 +22997,14 @@ struct hwrm_cfa_encap_record_alloc_input {
 	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
 		UINT32_C(0x9)
+	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
+		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
-		HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4
+		HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE
 	uint8_t	unused_0[3];
 	/* This value is encap data used for the given encap type. */
 	uint32_t	encap_data[20];
@@ -22872,6 +23358,15 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
 	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
 		UINT32_C(0x9)
+	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
 	/* Any tunneled traffic */
 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
 		UINT32_C(0xff)
@@ -23381,6 +23876,15 @@ struct hwrm_cfa_em_flow_alloc_input {
 	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
 		UINT32_C(0x9)
+	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
 	/* Any tunneled traffic */
 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
 		UINT32_C(0xff)
@@ -23586,13 +24090,13 @@ struct hwrm_cfa_em_flow_free_output {
 	uint8_t	valid;
 } __attribute__((packed));
 
-/*******************************
- * hwrm_cfa_decap_filter_alloc *
- *******************************/
+/********************************
+ * hwrm_cfa_meter_profile_alloc *
+ ********************************/
 
 
-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
-struct hwrm_cfa_decap_filter_alloc_input {
+/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
+struct hwrm_cfa_meter_profile_alloc_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -23620,266 +24124,1670 @@ struct hwrm_cfa_decap_filter_alloc_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint32_t	flags;
-	/* ovs_tunnel is 1 b */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
-		UINT32_C(0x1)
-	uint32_t	enables;
+	uint8_t	flags;
 	/*
-	 * This bit must be '1' for the tunnel_type field to be
-	 * configured.
+	 * Enumeration denoting the RX, TX type of the resource.
+	 * This enumeration is used for resources that are similar for both
+	 * TX and RX paths of the chip.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH     UINT32_C(0x1)
+	/* tx path */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
+		UINT32_C(0x0)
+	/* rx path */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
 		UINT32_C(0x1)
-	/*
-	 * This bit must be '1' for the tunnel_id field to be
-	 * configured.
-	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
+		HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
+	/* The meter algorithm type. */
+	uint8_t	meter_type;
+	/* RFC 2697 (srTCM) */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
+		UINT32_C(0x0)
+	/* RFC 2698 (trTCM) */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
+		UINT32_C(0x1)
+	/* RFC 4115 (trTCM) */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
 		UINT32_C(0x2)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
+		HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
 	/*
-	 * This bit must be '1' for the src_macaddr field to be
-	 * configured.
+	 * This field is reserved for the future use.
+	 * It shall be set to 0.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
-		UINT32_C(0x4)
+	uint16_t	reserved1;
 	/*
-	 * This bit must be '1' for the dst_macaddr field to be
-	 * configured.
+	 * This field is reserved for the future use.
+	 * It shall be set to 0.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
-		UINT32_C(0x8)
-	/*
+	uint32_t	reserved2;
+	/* A meter rate specified in bytes-per-second. */
+	uint32_t	commit_rate;
+	/* The bandwidth value. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
+		UINT32_C(0xfffffff)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
+		0
+	/* The granularity of the value (bits or bytes). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
+		UINT32_C(0x10000000)
+	/* Value is in bits. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
+		(UINT32_C(0x0) << 28)
+	/* Value is in bytes. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
+		(UINT32_C(0x1) << 28)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
+		HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
+	/* bw_value_unit is 3 b */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
+		UINT32_C(0xe0000000)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
+		29
+	/* Value is in Mb or MB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
+		(UINT32_C(0x0) << 29)
+	/* Value is in Kb or KB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
+		(UINT32_C(0x2) << 29)
+	/* Value is in bits or bytes. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
+		(UINT32_C(0x4) << 29)
+	/* Value is in Gb or GB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
+		(UINT32_C(0x6) << 29)
+	/* Value is in 1/100th of a percentage of total bandwidth. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+		(UINT32_C(0x1) << 29)
+	/* Invalid unit */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+		(UINT32_C(0x7) << 29)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
+		HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+	/* A meter burst size specified in bytes. */
+	uint32_t	commit_burst;
+	/* The bandwidth value. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
+		UINT32_C(0xfffffff)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
+		0
+	/* The granularity of the value (bits or bytes). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
+		UINT32_C(0x10000000)
+	/* Value is in bits. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
+		(UINT32_C(0x0) << 28)
+	/* Value is in bytes. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
+		(UINT32_C(0x1) << 28)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
+		HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
+	/* bw_value_unit is 3 b */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
+		UINT32_C(0xe0000000)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
+		29
+	/* Value is in Mb or MB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
+		(UINT32_C(0x0) << 29)
+	/* Value is in Kb or KB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
+		(UINT32_C(0x2) << 29)
+	/* Value is in bits or bytes. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
+		(UINT32_C(0x4) << 29)
+	/* Value is in Gb or GB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
+		(UINT32_C(0x6) << 29)
+	/* Value is in 1/100th of a percentage of total bandwidth. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+		(UINT32_C(0x1) << 29)
+	/* Invalid unit */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
+		(UINT32_C(0x7) << 29)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
+		HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
+	/* A meter rate specified in bytes-per-second. */
+	uint32_t	excess_peak_rate;
+	/* The bandwidth value. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
+		UINT32_C(0xfffffff)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
+		0
+	/* The granularity of the value (bits or bytes). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
+		UINT32_C(0x10000000)
+	/* Value is in bits. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
+		(UINT32_C(0x0) << 28)
+	/* Value is in bytes. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
+		(UINT32_C(0x1) << 28)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
+		HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
+	/* bw_value_unit is 3 b */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
+		UINT32_C(0xe0000000)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
+		29
+	/* Value is in Mb or MB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
+		(UINT32_C(0x0) << 29)
+	/* Value is in Kb or KB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
+		(UINT32_C(0x2) << 29)
+	/* Value is in bits or bytes. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
+		(UINT32_C(0x4) << 29)
+	/* Value is in Gb or GB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
+		(UINT32_C(0x6) << 29)
+	/* Value is in 1/100th of a percentage of total bandwidth. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+		(UINT32_C(0x1) << 29)
+	/* Invalid unit */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+		(UINT32_C(0x7) << 29)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
+		HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+	/* A meter burst size specified in bytes. */
+	uint32_t	excess_peak_burst;
+	/* The bandwidth value. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
+		UINT32_C(0xfffffff)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
+		0
+	/* The granularity of the value (bits or bytes). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
+		UINT32_C(0x10000000)
+	/* Value is in bits. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
+		(UINT32_C(0x0) << 28)
+	/* Value is in bytes. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
+		(UINT32_C(0x1) << 28)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
+		HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
+	/* bw_value_unit is 3 b */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
+		UINT32_C(0xe0000000)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
+		29
+	/* Value is in Mb or MB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
+		(UINT32_C(0x0) << 29)
+	/* Value is in Kb or KB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
+		(UINT32_C(0x2) << 29)
+	/* Value is in bits or bytes. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
+		(UINT32_C(0x4) << 29)
+	/* Value is in Gb or GB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
+		(UINT32_C(0x6) << 29)
+	/* Value is in 1/100th of a percentage of total bandwidth. */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+		(UINT32_C(0x1) << 29)
+	/* Invalid unit */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
+		(UINT32_C(0x7) << 29)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
+		HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_alloc_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* This value identifies a meter profile in CFA. */
+	uint16_t	meter_profile_id;
+	/*
+	 * A value of 0xfff is considered invalid and implies the
+	 * profile is not configured.
+	 */
+	#define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
+		UINT32_C(0xffff)
+	#define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
+		HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
+	uint8_t	unused_0[5];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_meter_profile_free *
+ *******************************/
+
+
+/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_profile_free_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFE - Reserved for internal processors
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	uint8_t	flags;
+	/*
+	 * Enumeration denoting the RX, TX type of the resource.
+	 * This enumeration is used for resources that are similar for both
+	 * TX and RX paths of the chip.
+	 */
+	#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH     UINT32_C(0x1)
+	/* tx path */
+	#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
+		UINT32_C(0x0)
+	/* rx path */
+	#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
+		UINT32_C(0x1)
+	#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
+		HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
+	uint8_t	unused_0;
+	/* This value identifies a meter profile in CFA. */
+	uint16_t	meter_profile_id;
+	/*
+	 * A value of 0xfff is considered invalid and implies the
+	 * profile is not configured.
+	 */
+	#define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
+		UINT32_C(0xffff)
+	#define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
+		HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
+	uint8_t	unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_free_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	uint8_t	unused_0[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_cfa_meter_profile_cfg *
+ ******************************/
+
+
+/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
+struct hwrm_cfa_meter_profile_cfg_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFE - Reserved for internal processors
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	uint8_t	flags;
+	/*
+	 * Enumeration denoting the RX, TX type of the resource.
+	 * This enumeration is used for resources that are similar for both
+	 * TX and RX paths of the chip.
+	 */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH     UINT32_C(0x1)
+	/* tx path */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX    UINT32_C(0x0)
+	/* rx path */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX    UINT32_C(0x1)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
+		HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
+	/* The meter algorithm type. */
+	uint8_t	meter_type;
+	/* RFC 2697 (srTCM) */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
+		UINT32_C(0x0)
+	/* RFC 2698 (trTCM) */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
+		UINT32_C(0x1)
+	/* RFC 4115 (trTCM) */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
+		UINT32_C(0x2)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
+		HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
+	/* This value identifies a meter profile in CFA. */
+	uint16_t	meter_profile_id;
+	/*
+	 * A value of 0xfff is considered invalid and implies the
+	 * profile is not configured.
+	 */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
+		UINT32_C(0xffff)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
+		HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
+	/*
+	 * This field is reserved for the future use.
+	 * It shall be set to 0.
+	 */
+	uint32_t	reserved;
+	/* A meter rate specified in bytes-per-second. */
+	uint32_t	commit_rate;
+	/* The bandwidth value. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
+		UINT32_C(0xfffffff)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
+		0
+	/* The granularity of the value (bits or bytes). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
+		UINT32_C(0x10000000)
+	/* Value is in bits. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
+		(UINT32_C(0x0) << 28)
+	/* Value is in bytes. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
+		(UINT32_C(0x1) << 28)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
+		HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
+	/* bw_value_unit is 3 b */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
+		UINT32_C(0xe0000000)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
+		29
+	/* Value is in Mb or MB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
+		(UINT32_C(0x0) << 29)
+	/* Value is in Kb or KB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
+		(UINT32_C(0x2) << 29)
+	/* Value is in bits or bytes. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
+		(UINT32_C(0x4) << 29)
+	/* Value is in Gb or GB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
+		(UINT32_C(0x6) << 29)
+	/* Value is in 1/100th of a percentage of total bandwidth. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+		(UINT32_C(0x1) << 29)
+	/* Invalid unit */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+		(UINT32_C(0x7) << 29)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
+		HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+	/* A meter burst size specified in bytes. */
+	uint32_t	commit_burst;
+	/* The bandwidth value. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
+		UINT32_C(0xfffffff)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
+		0
+	/* The granularity of the value (bits or bytes). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
+		UINT32_C(0x10000000)
+	/* Value is in bits. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
+		(UINT32_C(0x0) << 28)
+	/* Value is in bytes. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
+		(UINT32_C(0x1) << 28)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
+		HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
+	/* bw_value_unit is 3 b */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
+		UINT32_C(0xe0000000)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
+		29
+	/* Value is in Mb or MB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
+		(UINT32_C(0x0) << 29)
+	/* Value is in Kb or KB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
+		(UINT32_C(0x2) << 29)
+	/* Value is in bits or bytes. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
+		(UINT32_C(0x4) << 29)
+	/* Value is in Gb or GB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
+		(UINT32_C(0x6) << 29)
+	/* Value is in 1/100th of a percentage of total bandwidth. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+		(UINT32_C(0x1) << 29)
+	/* Invalid unit */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
+		(UINT32_C(0x7) << 29)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
+		HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
+	/* A meter rate specified in bytes-per-second. */
+	uint32_t	excess_peak_rate;
+	/* The bandwidth value. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
+		UINT32_C(0xfffffff)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
+		0
+	/* The granularity of the value (bits or bytes). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
+		UINT32_C(0x10000000)
+	/* Value is in bits. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
+		(UINT32_C(0x0) << 28)
+	/* Value is in bytes. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
+		(UINT32_C(0x1) << 28)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
+		HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
+	/* bw_value_unit is 3 b */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
+		UINT32_C(0xe0000000)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
+		29
+	/* Value is in Mb or MB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
+		(UINT32_C(0x0) << 29)
+	/* Value is in Kb or KB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
+		(UINT32_C(0x2) << 29)
+	/* Value is in bits or bytes. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
+		(UINT32_C(0x4) << 29)
+	/* Value is in Gb or GB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
+		(UINT32_C(0x6) << 29)
+	/* Value is in 1/100th of a percentage of total bandwidth. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+		(UINT32_C(0x1) << 29)
+	/* Invalid unit */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+		(UINT32_C(0x7) << 29)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
+		HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+	/* A meter burst size specified in bytes. */
+	uint32_t	excess_peak_burst;
+	/* The bandwidth value. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
+		UINT32_C(0xfffffff)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
+		0
+	/* The granularity of the value (bits or bytes). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
+		UINT32_C(0x10000000)
+	/* Value is in bits. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
+		(UINT32_C(0x0) << 28)
+	/* Value is in bytes. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
+		(UINT32_C(0x1) << 28)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
+		HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
+	/* bw_value_unit is 3 b */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
+		UINT32_C(0xe0000000)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
+		29
+	/* Value is in Mb or MB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
+		(UINT32_C(0x0) << 29)
+	/* Value is in Kb or KB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
+		(UINT32_C(0x2) << 29)
+	/* Value is in bits or bytes. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
+		(UINT32_C(0x4) << 29)
+	/* Value is in Gb or GB (base 10). */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
+		(UINT32_C(0x6) << 29)
+	/* Value is in 1/100th of a percentage of total bandwidth. */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+		(UINT32_C(0x1) << 29)
+	/* Invalid unit */
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
+		(UINT32_C(0x7) << 29)
+	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
+		HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_cfg_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	uint8_t	unused_0[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __attribute__((packed));
+
+/*********************************
+ * hwrm_cfa_meter_instance_alloc *
+ *********************************/
+
+
+/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_alloc_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFE - Reserved for internal processors
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	uint8_t	flags;
+	/*
+	 * Enumeration denoting the RX, TX type of the resource.
+	 * This enumeration is used for resources that are similar for both
+	 * TX and RX paths of the chip.
+	 */
+	#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
+		UINT32_C(0x1)
+	/* tx path */
+	#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
+		UINT32_C(0x0)
+	/* rx path */
+	#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
+		UINT32_C(0x1)
+	#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
+		HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
+	uint8_t	unused_0;
+	/* This value identifies a meter profile in CFA. */
+	uint16_t	meter_profile_id;
+	/*
+	 * A value of 0xfff is considered invalid and implies the
+	 * profile is not configured.
+	 */
+	#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
+		UINT32_C(0xffff)
+	#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
+		HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
+	uint8_t	unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_alloc_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* This value identifies a meter instance in CFA. */
+	uint16_t	meter_instance_id;
+	/*
+	 * A value of 0xfff is considered invalid and implies the
+	 * instance is not configured.
+	 */
+	#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
+		UINT32_C(0xffff)
+	#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
+		HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
+	uint8_t	unused_0[5];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __attribute__((packed));
+
+/********************************
+ * hwrm_cfa_meter_instance_free *
+ ********************************/
+
+
+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_free_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFE - Reserved for internal processors
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	uint8_t	flags;
+	/*
+	 * Enumeration denoting the RX, TX type of the resource.
+	 * This enumeration is used for resources that are similar for both
+	 * TX and RX paths of the chip.
+	 */
+	#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH     UINT32_C(0x1)
+	/* tx path */
+	#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+		UINT32_C(0x0)
+	/* rx path */
+	#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
+		UINT32_C(0x1)
+	#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
+		HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+	uint8_t	unused_0;
+	/* This value identifies a meter instance in CFA. */
+	uint16_t	meter_instance_id;
+	/*
+	 * A value of 0xfff is considered invalid and implies the
+	 * instance is not configured.
+	 */
+	#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+		UINT32_C(0xffff)
+	#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
+		HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
+	uint8_t	unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_free_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	uint8_t	unused_0[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_decap_filter_alloc *
+ *******************************/
+
+
+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
+struct hwrm_cfa_decap_filter_alloc_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFE - Reserved for internal processors
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	uint32_t	flags;
+	/* ovs_tunnel is 1 b */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+		UINT32_C(0x1)
+	uint32_t	enables;
+	/*
+	 * This bit must be '1' for the tunnel_type field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+		UINT32_C(0x1)
+	/*
+	 * This bit must be '1' for the tunnel_id field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+		UINT32_C(0x2)
+	/*
+	 * This bit must be '1' for the src_macaddr field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
+		UINT32_C(0x4)
+	/*
+	 * This bit must be '1' for the dst_macaddr field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
+		UINT32_C(0x8)
+	/*
 	 * This bit must be '1' for the ovlan_vid field to be
 	 * configured.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
-		UINT32_C(0x10)
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
+		UINT32_C(0x10)
+	/*
+	 * This bit must be '1' for the ivlan_vid field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
+		UINT32_C(0x20)
+	/*
+	 * This bit must be '1' for the t_ovlan_vid field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+		UINT32_C(0x40)
+	/*
+	 * This bit must be '1' for the t_ivlan_vid field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+		UINT32_C(0x80)
+	/*
+	 * This bit must be '1' for the ethertype field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+		UINT32_C(0x100)
+	/*
+	 * This bit must be '1' for the src_ipaddr field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+		UINT32_C(0x200)
+	/*
+	 * This bit must be '1' for the dst_ipaddr field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+		UINT32_C(0x400)
+	/*
+	 * This bit must be '1' for the ipaddr_type field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
+		UINT32_C(0x800)
+	/*
+	 * This bit must be '1' for the ip_protocol field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
+		UINT32_C(0x1000)
+	/*
+	 * This bit must be '1' for the src_port field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
+		UINT32_C(0x2000)
+	/*
+	 * This bit must be '1' for the dst_port field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
+		UINT32_C(0x4000)
+	/*
+	 * This bit must be '1' for the dst_id field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
+		UINT32_C(0x8000)
+	/*
+	 * This bit must be '1' for the mirror_vnic_id field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
+		UINT32_C(0x10000)
+	/*
+	 * Tunnel identifier.
+	 * Virtual Network Identifier (VNI). Only valid with
+	 * tunnel_types VXLAN, NVGRE, and Geneve.
+	 * Only lower 24-bits of VNI field are used
+	 * in setting up the filter.
+	 */
+	uint32_t	tunnel_id;
+	/* Tunnel Type. */
+	uint8_t	tunnel_type;
+	/* Non-tunnel */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+		UINT32_C(0x0)
+	/* Virtual eXtensible Local Area Network (VXLAN) */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+		UINT32_C(0x1)
+	/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+		UINT32_C(0x2)
+	/* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+		UINT32_C(0x3)
+	/* IP in IP */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+		UINT32_C(0x4)
+	/* Generic Network Virtualization Encapsulation (Geneve) */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+		UINT32_C(0x5)
+	/* Multi-Protocol Lable Switching (MPLS) */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+		UINT32_C(0x6)
+	/* Stateless Transport Tunnel (STT) */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+		UINT32_C(0x7)
+	/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+		UINT32_C(0x8)
+	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+		UINT32_C(0x9)
+	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
+	/* Any tunneled traffic */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+		UINT32_C(0xff)
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+		HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+	uint8_t	unused_0;
+	uint16_t	unused_1;
+	/*
+	 * This value indicates the source MAC address in
+	 * the Ethernet header.
+	 */
+	uint8_t	src_macaddr[6];
+	uint8_t	unused_2[2];
 	/*
-	 * This bit must be '1' for the ivlan_vid field to be
-	 * configured.
+	 * This value indicates the destination MAC address in
+	 * the Ethernet header.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
-		UINT32_C(0x20)
+	uint8_t	dst_macaddr[6];
+	/*
+	 * This value indicates the VLAN ID of the outer VLAN tag
+	 * in the Ethernet header.
+	 */
+	uint16_t	ovlan_vid;
+	/*
+	 * This value indicates the VLAN ID of the inner VLAN tag
+	 * in the Ethernet header.
+	 */
+	uint16_t	ivlan_vid;
+	/*
+	 * This value indicates the VLAN ID of the outer VLAN tag
+	 * in the tunnel Ethernet header.
+	 */
+	uint16_t	t_ovlan_vid;
+	/*
+	 * This value indicates the VLAN ID of the inner VLAN tag
+	 * in the tunnel Ethernet header.
+	 */
+	uint16_t	t_ivlan_vid;
+	/* This value indicates the ethertype in the Ethernet header. */
+	uint16_t	ethertype;
+	/*
+	 * This value indicates the type of IP address.
+	 * 4 - IPv4
+	 * 6 - IPv6
+	 * All others are invalid.
+	 */
+	uint8_t	ip_addr_type;
+	/* invalid */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
+		UINT32_C(0x0)
+	/* IPv4 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
+		UINT32_C(0x4)
+	/* IPv6 */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
+		UINT32_C(0x6)
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
+		HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+	/*
+	 * The value of protocol filed in IP header.
+	 * Applies to UDP and TCP traffic.
+	 * 6 - TCP
+	 * 17 - UDP
+	 */
+	uint8_t	ip_protocol;
+	/* invalid */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
+		UINT32_C(0x0)
+	/* TCP */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
+		UINT32_C(0x6)
+	/* UDP */
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
+		UINT32_C(0x11)
+	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
+		HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
+	uint16_t	unused_3;
+	uint32_t	unused_4;
+	/*
+	 * The value of source IP address to be used in filtering.
+	 * For IPv4, first four bytes represent the IP address.
+	 */
+	uint32_t	src_ipaddr[4];
+	/*
+	 * The value of destination IP address to be used in filtering.
+	 * For IPv4, first four bytes represent the IP address.
+	 */
+	uint32_t	dst_ipaddr[4];
+	/*
+	 * The value of source port to be used in filtering.
+	 * Applies to UDP and TCP traffic.
+	 */
+	uint16_t	src_port;
+	/*
+	 * The value of destination port to be used in filtering.
+	 * Applies to UDP and TCP traffic.
+	 */
+	uint16_t	dst_port;
+	/*
+	 * If set, this value shall represent the
+	 * Logical VNIC ID of the destination VNIC for the RX
+	 * path.
+	 */
+	uint16_t	dst_id;
+	/*
+	 * If set, this value shall represent the L2 context that matches the L2
+	 * information of the decap filter.
+	 */
+	uint16_t	l2_ctxt_ref_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_alloc_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* This value is an opaque id into CFA data structures. */
+	uint32_t	decap_filter_id;
+	uint8_t	unused_0[3];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_cfa_decap_filter_free *
+ ******************************/
+
+
+/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
+struct hwrm_cfa_decap_filter_free_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFE - Reserved for internal processors
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/* This value is an opaque id into CFA data structures. */
+	uint32_t	decap_filter_id;
+	uint8_t	unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_free_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	uint8_t	unused_0[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_cfa_flow_alloc *
+ ***********************/
+
+
+/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
+struct hwrm_cfa_flow_alloc_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFE - Reserved for internal processors
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	uint16_t	flags;
+	/* tunnel is 1 b */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
+		UINT32_C(0x1)
+	/* num_vlan is 2 b */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
+		UINT32_C(0x6)
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT           1
+	/* no tags */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
+		(UINT32_C(0x0) << 1)
+	/* 1 tag */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
+		(UINT32_C(0x1) << 1)
+	/* 2 tags */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
+		(UINT32_C(0x2) << 1)
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
+		HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
+	/* Enumeration denoting the Flow Type. */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
+		UINT32_C(0x38)
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT           3
+	/* L2 flow */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
+		(UINT32_C(0x0) << 3)
+	/* IPV4 flow */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
+		(UINT32_C(0x1) << 3)
+	/* IPV6 flow */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
+		(UINT32_C(0x2) << 3)
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
+		HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
 	/*
-	 * This bit must be '1' for the t_ovlan_vid field to be
-	 * configured.
+	 * when set to 1, indicates TX flow offload for function specified in src_fid and
+	 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
+	 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
+	 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
+	 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
+	 * belong to the children VFs of the same PF to indicate VM to VM flow.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
 		UINT32_C(0x40)
 	/*
-	 * This bit must be '1' for the t_ivlan_vid field to be
-	 * configured.
+	 * when set to 1, indicates RX flow offload for function specified in dst_fid and
+	 * the src_fid should be set to invalid value.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
 		UINT32_C(0x80)
 	/*
-	 * This bit must be '1' for the ethertype field to be
-	 * configured.
+	 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
+	 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
+	 * This flag is only valid when the flow direction is RX.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
 		UINT32_C(0x100)
 	/*
-	 * This bit must be '1' for the src_ipaddr field to be
-	 * configured.
+	 * Tx Flow: vf fid.
+	 * Rx Flow: pf fid.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+	uint16_t	src_fid;
+	/* Tunnel handle valid when tunnel flag is set. */
+	uint32_t	tunnel_handle;
+	uint16_t	action_flags;
+	/*
+	 * Setting of this flag indicates drop action. If this flag is not set,
+	 * then it should be considered accept action.
+	 */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
+		UINT32_C(0x1)
+	/* recycle is 1 b */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
+		UINT32_C(0x2)
+	/*
+	 * Setting of this flag indicates drop action. If this flag is not set,
+	 * then it should be considered accept action.
+	 */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
+		UINT32_C(0x4)
+	/* meter is 1 b */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
+		UINT32_C(0x8)
+	/* tunnel is 1 b */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
+		UINT32_C(0x10)
+	/* nat_src is 1 b */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
+		UINT32_C(0x20)
+	/* nat_dest is 1 b */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
+		UINT32_C(0x40)
+	/* nat_ipv4_address is 1 b */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
+		UINT32_C(0x80)
+	/* l2_header_rewrite is 1 b */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
+		UINT32_C(0x100)
+	/* ttl_decrement is 1 b */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
 		UINT32_C(0x200)
 	/*
-	 * This bit must be '1' for the dst_ipaddr field to be
-	 * configured.
+	 * If set to 1 and flow direction is TX, it indicates decap of L2 header
+	 * and encap of tunnel header. If set to 1 and flow direction is RX, it
+	 * indicates decap of tunnel header and encap L2 header. The type of tunnel
+	 * is specified in the tunnel_type field.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
 		UINT32_C(0x400)
+	/* If set to 1, flow aging is enabled for this flow. */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
+		UINT32_C(0x800)
 	/*
-	 * This bit must be '1' for the ipaddr_type field to be
-	 * configured.
+	 * Tx Flow: pf or vf fid.
+	 * Rx Flow: vf fid.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
-		UINT32_C(0x800)
+	uint16_t	dst_fid;
+	/* VLAN tpid, valid when push_vlan flag is set. */
+	uint16_t	l2_rewrite_vlan_tpid;
+	/* VLAN tci, valid when push_vlan flag is set. */
+	uint16_t	l2_rewrite_vlan_tci;
+	/* Meter id, valid when meter flag is set. */
+	uint16_t	act_meter_id;
+	/* Flow with the same l2 context tcam key. */
+	uint16_t	ref_flow_handle;
+	/* This value sets the match value for the ethertype. */
+	uint16_t	ethertype;
+	/* valid when num tags is 1 or 2. */
+	uint16_t	outer_vlan_tci;
+	/* This value sets the match value for the Destination MAC address. */
+	uint16_t	dmac[3];
+	/* valid when num tags is 2. */
+	uint16_t	inner_vlan_tci;
+	/* This value sets the match value for the Source MAC address. */
+	uint16_t	smac[3];
+	/* The bit length of destination IP address mask. */
+	uint8_t	ip_dst_mask_len;
+	/* The bit length of source IP address mask. */
+	uint8_t	ip_src_mask_len;
+	/* The value of destination IPv4/IPv6 address. */
+	uint32_t	ip_dst[4];
+	/* The source IPv4/IPv6 address. */
+	uint32_t	ip_src[4];
 	/*
-	 * This bit must be '1' for the ip_protocol field to be
-	 * configured.
+	 * The value of source port.
+	 * Applies to UDP and TCP traffic.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
-		UINT32_C(0x1000)
+	uint16_t	l4_src_port;
 	/*
-	 * This bit must be '1' for the src_port field to be
-	 * configured.
+	 * The value of source port mask.
+	 * Applies to UDP and TCP traffic.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
-		UINT32_C(0x2000)
+	uint16_t	l4_src_port_mask;
 	/*
-	 * This bit must be '1' for the dst_port field to be
-	 * configured.
+	 * The value of destination port.
+	 * Applies to UDP and TCP traffic.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
-		UINT32_C(0x4000)
+	uint16_t	l4_dst_port;
 	/*
-	 * This bit must be '1' for the dst_id field to be
-	 * configured.
+	 * The value of destination port mask.
+	 * Applies to UDP and TCP traffic.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
-		UINT32_C(0x8000)
+	uint16_t	l4_dst_port_mask;
 	/*
-	 * This bit must be '1' for the mirror_vnic_id field to be
-	 * configured.
+	 * NAT IPv4/6 address based on address type flag.
+	 * 0 values are ignored.
 	 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
-		UINT32_C(0x10000)
+	uint32_t	nat_ip_address[4];
+	/* L2 header re-write Destination MAC address. */
+	uint16_t	l2_rewrite_dmac[3];
 	/*
-	 * Tunnel identifier.
-	 * Virtual Network Identifier (VNI). Only valid with
-	 * tunnel_types VXLAN, NVGRE, and Geneve.
-	 * Only lower 24-bits of VNI field are used
-	 * in setting up the filter.
+	 * The NAT source/destination port based on direction flag.
+	 * Applies to UDP and TCP traffic.
+	 * 0 values are ignored.
 	 */
-	uint32_t	tunnel_id;
+	uint16_t	nat_port;
+	/* L2 header re-write Source MAC address. */
+	uint16_t	l2_rewrite_smac[3];
+	/* The value of ip protocol. */
+	uint8_t	ip_proto;
 	/* Tunnel Type. */
 	uint8_t	tunnel_type;
 	/* Non-tunnel */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
 		UINT32_C(0x0)
 	/* Virtual eXtensible Local Area Network (VXLAN) */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
 		UINT32_C(0x1)
 	/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
 		UINT32_C(0x2)
 	/* Generic Routing Encapsulation (GRE) inside Ethernet payload */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
 		UINT32_C(0x3)
 	/* IP in IP */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
 		UINT32_C(0x4)
 	/* Generic Network Virtualization Encapsulation (Geneve) */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
 		UINT32_C(0x5)
 	/* Multi-Protocol Lable Switching (MPLS) */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
 		UINT32_C(0x6)
 	/* Stateless Transport Tunnel (STT) */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
 		UINT32_C(0x7)
 	/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
 		UINT32_C(0x8)
 	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
 		UINT32_C(0x9)
+	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
 	/* Any tunneled traffic */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
 		UINT32_C(0xff)
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
-		HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
-	uint8_t	unused_0;
-	uint16_t	unused_1;
+	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+		HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
+struct hwrm_cfa_flow_alloc_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* Flow record index. */
+	uint16_t	flow_handle;
+	uint8_t	unused_0[2];
 	/*
-	 * This value indicates the source MAC address in
-	 * the Ethernet header.
+	 * This is the ID of the flow associated with this
+	 * filter.
+	 * This value shall be used to match and associate the
+	 * flow identifier returned in completion records.
+	 * A value of 0xFFFFFFFF shall indicate no flow id.
+	 */
+	uint32_t	flow_id;
+	/* This value identifies a set of CFA data structures used for a flow. */
+	uint64_t	ext_flow_handle;
+	uint8_t	unused_1[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_flow_free *
+ **********************/
+
+
+/* hwrm_cfa_flow_free_input (size:256b/32B) */
+struct hwrm_cfa_flow_free_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
 	 */
-	uint8_t	src_macaddr[6];
-	uint8_t	unused_2[2];
+	uint16_t	cmpl_ring;
 	/*
-	 * This value indicates the destination MAC address in
-	 * the Ethernet header.
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
 	 */
-	uint8_t	dst_macaddr[6];
+	uint16_t	seq_id;
 	/*
-	 * This value indicates the VLAN ID of the outer VLAN tag
-	 * in the Ethernet header.
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFE - Reserved for internal processors
+	 * * 0xFFFF - HWRM
 	 */
-	uint16_t	ovlan_vid;
+	uint16_t	target_id;
 	/*
-	 * This value indicates the VLAN ID of the inner VLAN tag
-	 * in the Ethernet header.
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
 	 */
-	uint16_t	ivlan_vid;
+	uint64_t	resp_addr;
+	/* Flow record index. */
+	uint16_t	flow_handle;
+	uint8_t	unused_0[6];
+	/* This value identifies a set of CFA data structures used for a flow. */
+	uint64_t	ext_flow_handle;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_free_output (size:256b/32B) */
+struct hwrm_cfa_flow_free_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* packet is 64 b */
+	uint64_t	packet;
+	/* byte is 64 b */
+	uint64_t	byte;
+	uint8_t	unused_0[7];
 	/*
-	 * This value indicates the VLAN ID of the outer VLAN tag
-	 * in the tunnel Ethernet header.
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
 	 */
-	uint16_t	t_ovlan_vid;
+	uint8_t	valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_flow_info *
+ **********************/
+
+
+/* hwrm_cfa_flow_info_input (size:256b/32B) */
+struct hwrm_cfa_flow_info_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
 	/*
-	 * This value indicates the VLAN ID of the inner VLAN tag
-	 * in the tunnel Ethernet header.
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
 	 */
-	uint16_t	t_ivlan_vid;
-	/* This value indicates the ethertype in the Ethernet header. */
-	uint16_t	ethertype;
+	uint16_t	cmpl_ring;
 	/*
-	 * This value indicates the type of IP address.
-	 * 4 - IPv4
-	 * 6 - IPv6
-	 * All others are invalid.
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
 	 */
-	uint8_t	ip_addr_type;
-	/* invalid */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
-		UINT32_C(0x0)
-	/* IPv4 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
-		UINT32_C(0x4)
-	/* IPv6 */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
-		UINT32_C(0x6)
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
-		HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+	uint16_t	seq_id;
 	/*
-	 * The value of protocol filed in IP header.
-	 * Applies to UDP and TCP traffic.
-	 * 6 - TCP
-	 * 17 - UDP
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFE - Reserved for internal processors
+	 * * 0xFFFF - HWRM
 	 */
-	uint8_t	ip_protocol;
-	/* invalid */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
-		UINT32_C(0x0)
-	/* TCP */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
-		UINT32_C(0x6)
-	/* UDP */
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
-		UINT32_C(0x11)
-	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
-		HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
-	uint16_t	unused_3;
-	uint32_t	unused_4;
+	uint16_t	target_id;
 	/*
-	 * The value of source IP address to be used in filtering.
-	 * For IPv4, first four bytes represent the IP address.
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
 	 */
-	uint32_t	src_ipaddr[4];
+	uint64_t	resp_addr;
+	/* Flow record index. */
+	uint16_t	flow_handle;
+	/* Max flow handle */
+	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
+		UINT32_C(0xfff)
+	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT        0
+	/* CNP flow handle */
+	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
+		UINT32_C(0x1000)
+	/* RoCEv1 flow handle */
+	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
+		UINT32_C(0x2000)
+	/* RoCEv2 flow handle */
+	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
+		UINT32_C(0x4000)
+	/* Direction rx = 1 */
+	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
+		UINT32_C(0x8000)
+	uint8_t	unused_0[6];
+	/* This value identifies a set of CFA data structures used for a flow. */
+	uint64_t	ext_flow_handle;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_info_output (size:448b/56B) */
+struct hwrm_cfa_flow_info_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* flags is 8 b */
+	uint8_t	flags;
+	/* profile is 8 b */
+	uint8_t	profile;
+	/* src_fid is 16 b */
+	uint16_t	src_fid;
+	/* dst_fid is 16 b */
+	uint16_t	dst_fid;
+	/* l2_ctxt_id is 16 b */
+	uint16_t	l2_ctxt_id;
+	/* em_info is 64 b */
+	uint64_t	em_info;
+	/* tcam_info is 64 b */
+	uint64_t	tcam_info;
+	/* vfp_tcam_info is 64 b */
+	uint64_t	vfp_tcam_info;
+	/* ar_id is 16 b */
+	uint16_t	ar_id;
+	/* flow_handle is 16 b */
+	uint16_t	flow_handle;
+	/* tunnel_handle is 32 b */
+	uint32_t	tunnel_handle;
+	/* The flow aging timer for the flow, the unit is 100 milliseconds */
+	uint16_t	flow_timer;
+	uint8_t	unused_0[5];
 	/*
-	 * The value of destination IP address to be used in filtering.
-	 * For IPv4, first four bytes represent the IP address.
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
 	 */
-	uint32_t	dst_ipaddr[4];
+	uint8_t	valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_cfa_flow_flush *
+ ***********************/
+
+
+/* hwrm_cfa_flow_flush_input (size:192b/24B) */
+struct hwrm_cfa_flow_flush_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
 	/*
-	 * The value of source port to be used in filtering.
-	 * Applies to UDP and TCP traffic.
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
 	 */
-	uint16_t	src_port;
+	uint16_t	cmpl_ring;
 	/*
-	 * The value of destination port to be used in filtering.
-	 * Applies to UDP and TCP traffic.
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
 	 */
-	uint16_t	dst_port;
+	uint16_t	seq_id;
 	/*
-	 * If set, this value shall represent the
-	 * Logical VNIC ID of the destination VNIC for the RX
-	 * path.
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFE - Reserved for internal processors
+	 * * 0xFFFF - HWRM
 	 */
-	uint16_t	dst_id;
+	uint16_t	target_id;
 	/*
-	 * If set, this value shall represent the L2 context that matches the L2
-	 * information of the decap filter.
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
 	 */
-	uint16_t	l2_ctxt_ref_id;
+	uint64_t	resp_addr;
+	uint32_t	flags;
+	uint8_t	unused_0[4];
 } __attribute__((packed));
 
-/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_alloc_output {
+/* hwrm_cfa_flow_flush_output (size:128b/16B) */
+struct hwrm_cfa_flow_flush_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -23888,9 +25796,7 @@ struct hwrm_cfa_decap_filter_alloc_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* This value is an opaque id into CFA data structures. */
-	uint32_t	decap_filter_id;
-	uint8_t	unused_0[3];
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -23901,13 +25807,13 @@ struct hwrm_cfa_decap_filter_alloc_output {
 	uint8_t	valid;
 } __attribute__((packed));
 
-/******************************
- * hwrm_cfa_decap_filter_free *
- ******************************/
+/***********************
+ * hwrm_cfa_flow_stats *
+ ***********************/
 
 
-/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
-struct hwrm_cfa_decap_filter_free_input {
+/* hwrm_cfa_flow_stats_input (size:640b/80B) */
+struct hwrm_cfa_flow_stats_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -23935,13 +25841,53 @@ struct hwrm_cfa_decap_filter_free_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* This value is an opaque id into CFA data structures. */
-	uint32_t	decap_filter_id;
-	uint8_t	unused_0[4];
+	/* Flow handle. */
+	uint16_t	num_flows;
+	/* Flow handle. */
+	uint16_t	flow_handle_0;
+	/* Flow handle. */
+	uint16_t	flow_handle_1;
+	/* Flow handle. */
+	uint16_t	flow_handle_2;
+	/* Flow handle. */
+	uint16_t	flow_handle_3;
+	/* Flow handle. */
+	uint16_t	flow_handle_4;
+	/* Flow handle. */
+	uint16_t	flow_handle_5;
+	/* Flow handle. */
+	uint16_t	flow_handle_6;
+	/* Flow handle. */
+	uint16_t	flow_handle_7;
+	/* Flow handle. */
+	uint16_t	flow_handle_8;
+	/* Flow handle. */
+	uint16_t	flow_handle_9;
+	uint8_t	unused_0[2];
+	/* Flow ID of a flow. */
+	uint32_t	flow_id_0;
+	/* Flow ID of a flow. */
+	uint32_t	flow_id_1;
+	/* Flow ID of a flow. */
+	uint32_t	flow_id_2;
+	/* Flow ID of a flow. */
+	uint32_t	flow_id_3;
+	/* Flow ID of a flow. */
+	uint32_t	flow_id_4;
+	/* Flow ID of a flow. */
+	uint32_t	flow_id_5;
+	/* Flow ID of a flow. */
+	uint32_t	flow_id_6;
+	/* Flow ID of a flow. */
+	uint32_t	flow_id_7;
+	/* Flow ID of a flow. */
+	uint32_t	flow_id_8;
+	/* Flow ID of a flow. */
+	uint32_t	flow_id_9;
 } __attribute__((packed));
 
-/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_free_output {
+/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
+struct hwrm_cfa_flow_stats_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -23950,6 +25896,46 @@ struct hwrm_cfa_decap_filter_free_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
+	/* packet_0 is 64 b */
+	uint64_t	packet_0;
+	/* packet_1 is 64 b */
+	uint64_t	packet_1;
+	/* packet_2 is 64 b */
+	uint64_t	packet_2;
+	/* packet_3 is 64 b */
+	uint64_t	packet_3;
+	/* packet_4 is 64 b */
+	uint64_t	packet_4;
+	/* packet_5 is 64 b */
+	uint64_t	packet_5;
+	/* packet_6 is 64 b */
+	uint64_t	packet_6;
+	/* packet_7 is 64 b */
+	uint64_t	packet_7;
+	/* packet_8 is 64 b */
+	uint64_t	packet_8;
+	/* packet_9 is 64 b */
+	uint64_t	packet_9;
+	/* byte_0 is 64 b */
+	uint64_t	byte_0;
+	/* byte_1 is 64 b */
+	uint64_t	byte_1;
+	/* byte_2 is 64 b */
+	uint64_t	byte_2;
+	/* byte_3 is 64 b */
+	uint64_t	byte_3;
+	/* byte_4 is 64 b */
+	uint64_t	byte_4;
+	/* byte_5 is 64 b */
+	uint64_t	byte_5;
+	/* byte_6 is 64 b */
+	uint64_t	byte_6;
+	/* byte_7 is 64 b */
+	uint64_t	byte_7;
+	/* byte_8 is 64 b */
+	uint64_t	byte_8;
+	/* byte_9 is 64 b */
+	uint64_t	byte_9;
 	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
@@ -23961,13 +25947,13 @@ struct hwrm_cfa_decap_filter_free_output {
 	uint8_t	valid;
 } __attribute__((packed));
 
-/***********************
- * hwrm_cfa_flow_alloc *
- ***********************/
+/***********************************
+ * hwrm_cfa_flow_aging_timer_reset *
+ ***********************************/
 
 
-/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
-struct hwrm_cfa_flow_alloc_input {
+/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
+struct hwrm_cfa_flow_aging_timer_reset_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -23989,219 +25975,21 @@ struct hwrm_cfa_flow_alloc_input {
 	 */
 	uint16_t	target_id;
 	/*
-	 * A physical address pointer pointing to a host buffer that the
-	 * command's response data will be written. This can be either a host
-	 * physical address (HPA) or a guest physical address (GPA) and must
-	 * point to a physically contiguous block of memory.
-	 */
-	uint64_t	resp_addr;
-	uint16_t	flags;
-	/* tunnel is 1 b */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
-		UINT32_C(0x1)
-	/* num_vlan is 2 b */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
-		UINT32_C(0x6)
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT           1
-	/* no tags */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
-		(UINT32_C(0x0) << 1)
-	/* 1 tag */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
-		(UINT32_C(0x1) << 1)
-	/* 2 tags */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
-		(UINT32_C(0x2) << 1)
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
-		HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
-	/* Enumeration denoting the Flow Type. */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
-		UINT32_C(0x38)
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT           3
-	/* L2 flow */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
-		(UINT32_C(0x0) << 3)
-	/* IPV4 flow */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
-		(UINT32_C(0x1) << 3)
-	/* IPV6 flow */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
-		(UINT32_C(0x2) << 3)
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
-		HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
-	/*
-	 * when set to 1, indicates TX flow offload for function specified in src_fid and
-	 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
-	 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
-	 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
-	 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
-	 * belong to the children VFs of the same PF to indicate VM to VM flow.
-	 */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
-		UINT32_C(0x40)
-	/*
-	 * when set to 1, indicates RX flow offload for function specified in dst_fid and
-	 * the src_fid should be set to invalid value.
-	 */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
-		UINT32_C(0x80)
-	/*
-	 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
-	 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
-	 * This flag is only valid when the flow direction is RX.
-	 */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
-		UINT32_C(0x100)
-	/*
-	 * Tx Flow: vf fid.
-	 * Rx Flow: pf fid.
-	 */
-	uint16_t	src_fid;
-	/* Tunnel handle valid when tunnel flag is set. */
-	uint32_t	tunnel_handle;
-	uint16_t	action_flags;
-	/*
-	 * Setting of this flag indicates drop action. If this flag is not set,
-	 * then it should be considered accept action.
-	 */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
-		UINT32_C(0x1)
-	/* recycle is 1 b */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
-		UINT32_C(0x2)
-	/*
-	 * Setting of this flag indicates drop action. If this flag is not set,
-	 * then it should be considered accept action.
-	 */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
-		UINT32_C(0x4)
-	/* meter is 1 b */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
-		UINT32_C(0x8)
-	/* tunnel is 1 b */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
-		UINT32_C(0x10)
-	/* nat_src is 1 b */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
-		UINT32_C(0x20)
-	/* nat_dest is 1 b */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
-		UINT32_C(0x40)
-	/* nat_ipv4_address is 1 b */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
-		UINT32_C(0x80)
-	/* l2_header_rewrite is 1 b */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
-		UINT32_C(0x100)
-	/* ttl_decrement is 1 b */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
-		UINT32_C(0x200)
-	/*
-	 * If set to 1 and flow direction is TX, it indicates decap of L2 header
-	 * and encap of tunnel header. If set to 1 and flow direction is RX, it
-	 * indicates decap of tunnel header and encap L2 header. The type of tunnel
-	 * is specified in the tunnel_type field.
-	 */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
-		UINT32_C(0x400)
-	/*
-	 * Tx Flow: pf or vf fid.
-	 * Rx Flow: vf fid.
-	 */
-	uint16_t	dst_fid;
-	/* VLAN tpid, valid when push_vlan flag is set. */
-	uint16_t	l2_rewrite_vlan_tpid;
-	/* VLAN tci, valid when push_vlan flag is set. */
-	uint16_t	l2_rewrite_vlan_tci;
-	/* Meter id, valid when meter flag is set. */
-	uint16_t	act_meter_id;
-	/* Flow with the same l2 context tcam key. */
-	uint16_t	ref_flow_handle;
-	/* This value sets the match value for the ethertype. */
-	uint16_t	ethertype;
-	/* valid when num tags is 1 or 2. */
-	uint16_t	outer_vlan_tci;
-	/* This value sets the match value for the Destination MAC address. */
-	uint16_t	dmac[3];
-	/* valid when num tags is 2. */
-	uint16_t	inner_vlan_tci;
-	/* This value sets the match value for the Source MAC address. */
-	uint16_t	smac[3];
-	/* The bit length of destination IP address mask. */
-	uint8_t	ip_dst_mask_len;
-	/* The bit length of source IP address mask. */
-	uint8_t	ip_src_mask_len;
-	/* The value of destination IPv4/IPv6 address. */
-	uint32_t	ip_dst[4];
-	/* The source IPv4/IPv6 address. */
-	uint32_t	ip_src[4];
-	/*
-	 * The value of source port.
-	 * Applies to UDP and TCP traffic.
-	 */
-	uint16_t	l4_src_port;
-	/*
-	 * The value of source port mask.
-	 * Applies to UDP and TCP traffic.
-	 */
-	uint16_t	l4_src_port_mask;
-	/*
-	 * The value of destination port.
-	 * Applies to UDP and TCP traffic.
-	 */
-	uint16_t	l4_dst_port;
-	/*
-	 * The value of destination port mask.
-	 * Applies to UDP and TCP traffic.
-	 */
-	uint16_t	l4_dst_port_mask;
-	/*
-	 * NAT IPv4/6 address based on address type flag.
-	 * 0 values are ignored.
-	 */
-	uint32_t	nat_ip_address[4];
-	/* L2 header re-write Destination MAC address. */
-	uint16_t	l2_rewrite_dmac[3];
-	/*
-	 * The NAT source/destination port based on direction flag.
-	 * Applies to UDP and TCP traffic.
-	 * 0 values are ignored.
-	 */
-	uint16_t	nat_port;
-	/* L2 header re-write Source MAC address. */
-	uint16_t	l2_rewrite_smac[3];
-	/* The value of ip protocol. */
-	uint8_t	ip_proto;
-	/* Tunnel Type. */
-	uint8_t	tunnel_type;
-	/* Non-tunnel */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
-	/* Virtual eXtensible Local Area Network (VXLAN) */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN     UINT32_C(0x1)
-	/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE     UINT32_C(0x2)
-	/* Generic Routing Encapsulation (GRE) inside Ethernet payload */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE     UINT32_C(0x3)
-	/* IP in IP */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP      UINT32_C(0x4)
-	/* Generic Network Virtualization Encapsulation (Geneve) */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE    UINT32_C(0x5)
-	/* Multi-Protocol Lable Switching (MPLS) */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS      UINT32_C(0x6)
-	/* Stateless Transport Tunnel (STT) */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT       UINT32_C(0x7)
-	/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE     UINT32_C(0x8)
-	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4  UINT32_C(0x9)
-	/* Any tunneled traffic */
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
-	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
-		HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/* Flow record index. */
+	uint16_t	flow_handle;
+	uint8_t	unused_0[6];
+	/* This value identifies a set of CFA data structures used for a flow. */
+	uint64_t	ext_flow_handle;
 } __attribute__((packed));
 
-/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
-struct hwrm_cfa_flow_alloc_output {
+/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
+struct hwrm_cfa_flow_aging_timer_reset_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -24210,20 +25998,7 @@ struct hwrm_cfa_flow_alloc_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Flow record index. */
-	uint16_t	flow_handle;
-	uint8_t	unused_0[2];
-	/*
-	 * This is the ID of the flow associated with this
-	 * filter.
-	 * This value shall be used to match and associate the
-	 * flow identifier returned in completion records.
-	 * A value of 0xFFFFFFFF shall indicate no flow id.
-	 */
-	uint32_t	flow_id;
-	/* This value identifies a set of CFA data structures used for a flow. */
-	uint64_t	ext_flow_handle;
-	uint8_t	unused_1[7];
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -24234,13 +26009,13 @@ struct hwrm_cfa_flow_alloc_output {
 	uint8_t	valid;
 } __attribute__((packed));
 
-/**********************
- * hwrm_cfa_flow_free *
- **********************/
+/***************************
+ * hwrm_cfa_flow_aging_cfg *
+ ***************************/
 
 
-/* hwrm_cfa_flow_free_input (size:256b/32B) */
-struct hwrm_cfa_flow_free_input {
+/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
+struct hwrm_cfa_flow_aging_cfg_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -24268,15 +26043,38 @@ struct hwrm_cfa_flow_free_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Flow record index. */
-	uint16_t	flow_handle;
-	uint8_t	unused_0[6];
-	/* This value identifies a set of CFA data structures used for a flow. */
-	uint64_t	ext_flow_handle;
+	/* The bit field to enable per flow aging configuration. */
+	uint16_t	enables;
+	/* This bit must be '1' for the tcp flow timer field to be configured */
+	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
+		UINT32_C(0x1)
+	/* This bit must be '1' for the tcp finish timer field to be configured */
+	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
+		UINT32_C(0x2)
+	/* This bit must be '1' for the udp flow timer field to be configured */
+	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
+		UINT32_C(0x4)
+	/* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+	uint8_t	flags;
+	/* Enumeration denoting the RX, TX type of the resource. */
+	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH     UINT32_C(0x1)
+	/* tx path */
+	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX    UINT32_C(0x0)
+	/* rx path */
+	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX    UINT32_C(0x1)
+	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
+		HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
+	uint8_t	unused_0;
+	/* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
+	uint32_t	tcp_flow_timer;
+	/* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
+	uint32_t	tcp_fin_timer;
+	/* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
+	uint32_t	udp_flow_timer;
 } __attribute__((packed));
 
-/* hwrm_cfa_flow_free_output (size:256b/32B) */
-struct hwrm_cfa_flow_free_output {
+/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
+struct hwrm_cfa_flow_aging_cfg_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -24285,10 +26083,6 @@ struct hwrm_cfa_flow_free_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* packet is 64 b */
-	uint64_t	packet;
-	/* byte is 64 b */
-	uint64_t	byte;
 	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
@@ -24300,13 +26094,13 @@ struct hwrm_cfa_flow_free_output {
 	uint8_t	valid;
 } __attribute__((packed));
 
-/***********************
- * hwrm_cfa_flow_flush *
- ***********************/
+/****************************
+ * hwrm_cfa_flow_aging_qcfg *
+ ****************************/
 
 
-/* hwrm_cfa_flow_flush_input (size:192b/24B) */
-struct hwrm_cfa_flow_flush_input {
+/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcfg_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -24334,12 +26128,21 @@ struct hwrm_cfa_flow_flush_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint32_t	flags;
-	uint8_t	unused_0[4];
+	/* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+	uint8_t	flags;
+	/* Enumeration denoting the RX, TX type of the resource. */
+	#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH     UINT32_C(0x1)
+	/* tx path */
+	#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX    UINT32_C(0x0)
+	/* rx path */
+	#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX    UINT32_C(0x1)
+	#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
+		HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
+	uint8_t	unused_0[7];
 } __attribute__((packed));
 
-/* hwrm_cfa_flow_flush_output (size:128b/16B) */
-struct hwrm_cfa_flow_flush_output {
+/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcfg_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -24348,7 +26151,13 @@ struct hwrm_cfa_flow_flush_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint8_t	unused_0[7];
+	/* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
+	uint32_t	tcp_flow_timer;
+	/* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+	uint32_t	tcp_fin_timer;
+	/* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
+	uint32_t	udp_flow_timer;
+	uint8_t	unused_0[3];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -24359,13 +26168,13 @@ struct hwrm_cfa_flow_flush_output {
 	uint8_t	valid;
 } __attribute__((packed));
 
-/***********************
- * hwrm_cfa_flow_stats *
- ***********************/
+/*****************************
+ * hwrm_cfa_flow_aging_qcaps *
+ *****************************/
 
 
-/* hwrm_cfa_flow_stats_input (size:640b/80B) */
-struct hwrm_cfa_flow_stats_input {
+/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcaps_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -24393,53 +26202,21 @@ struct hwrm_cfa_flow_stats_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Flow handle. */
-	uint16_t	num_flows;
-	/* Flow handle. */
-	uint16_t	flow_handle_0;
-	/* Flow handle. */
-	uint16_t	flow_handle_1;
-	/* Flow handle. */
-	uint16_t	flow_handle_2;
-	/* Flow handle. */
-	uint16_t	flow_handle_3;
-	/* Flow handle. */
-	uint16_t	flow_handle_4;
-	/* Flow handle. */
-	uint16_t	flow_handle_5;
-	/* Flow handle. */
-	uint16_t	flow_handle_6;
-	/* Flow handle. */
-	uint16_t	flow_handle_7;
-	/* Flow handle. */
-	uint16_t	flow_handle_8;
-	/* Flow handle. */
-	uint16_t	flow_handle_9;
-	uint8_t	unused_0[2];
-	/* Flow ID of a flow. */
-	uint32_t	flow_id_0;
-	/* Flow ID of a flow. */
-	uint32_t	flow_id_1;
-	/* Flow ID of a flow. */
-	uint32_t	flow_id_2;
-	/* Flow ID of a flow. */
-	uint32_t	flow_id_3;
-	/* Flow ID of a flow. */
-	uint32_t	flow_id_4;
-	/* Flow ID of a flow. */
-	uint32_t	flow_id_5;
-	/* Flow ID of a flow. */
-	uint32_t	flow_id_6;
-	/* Flow ID of a flow. */
-	uint32_t	flow_id_7;
-	/* Flow ID of a flow. */
-	uint32_t	flow_id_8;
-	/* Flow ID of a flow. */
-	uint32_t	flow_id_9;
+	/* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+	uint8_t	flags;
+	/* Enumeration denoting the RX, TX type of the resource. */
+	#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH     UINT32_C(0x1)
+	/* tx path */
+	#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX    UINT32_C(0x0)
+	/* rx path */
+	#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX    UINT32_C(0x1)
+	#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
+		HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
+	uint8_t	unused_0[7];
 } __attribute__((packed));
 
-/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
-struct hwrm_cfa_flow_stats_output {
+/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
+struct hwrm_cfa_flow_aging_qcaps_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -24448,46 +26225,14 @@ struct hwrm_cfa_flow_stats_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* packet_0 is 64 b */
-	uint64_t	packet_0;
-	/* packet_1 is 64 b */
-	uint64_t	packet_1;
-	/* packet_2 is 64 b */
-	uint64_t	packet_2;
-	/* packet_3 is 64 b */
-	uint64_t	packet_3;
-	/* packet_4 is 64 b */
-	uint64_t	packet_4;
-	/* packet_5 is 64 b */
-	uint64_t	packet_5;
-	/* packet_6 is 64 b */
-	uint64_t	packet_6;
-	/* packet_7 is 64 b */
-	uint64_t	packet_7;
-	/* packet_8 is 64 b */
-	uint64_t	packet_8;
-	/* packet_9 is 64 b */
-	uint64_t	packet_9;
-	/* byte_0 is 64 b */
-	uint64_t	byte_0;
-	/* byte_1 is 64 b */
-	uint64_t	byte_1;
-	/* byte_2 is 64 b */
-	uint64_t	byte_2;
-	/* byte_3 is 64 b */
-	uint64_t	byte_3;
-	/* byte_4 is 64 b */
-	uint64_t	byte_4;
-	/* byte_5 is 64 b */
-	uint64_t	byte_5;
-	/* byte_6 is 64 b */
-	uint64_t	byte_6;
-	/* byte_7 is 64 b */
-	uint64_t	byte_7;
-	/* byte_8 is 64 b */
-	uint64_t	byte_8;
-	/* byte_9 is 64 b */
-	uint64_t	byte_9;
+	/* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
+	uint32_t	max_tcp_flow_timer;
+	/* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+	uint32_t	max_tcp_fin_timer;
+	/* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
+	uint32_t	max_udp_flow_timer;
+	/* The maximum aging flows that HW can support. */
+	uint32_t	max_aging_flows;
 	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
@@ -24706,6 +26451,12 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
 	/* Any tunneled traffic */
 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
 		UINT32_C(0x800)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
+		UINT32_C(0x1000)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
+		UINT32_C(0x2000)
 	uint8_t	unused_0[3];
 	/*
 	 * This field is used in Output records to indicate that the output
@@ -24765,8 +26516,14 @@ struct hwrm_tunnel_dst_port_query_input {
 	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
 		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
-		HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1
+		HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
 	uint8_t	unused_0[7];
 } __attribute__((packed));
 
@@ -24857,8 +26614,14 @@ struct hwrm_tunnel_dst_port_alloc_input {
 	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
 		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
-		HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1
+		HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
 	uint8_t	unused_0;
 	/*
 	 * This field represents the value of L4 destination port used
@@ -24948,8 +26711,14 @@ struct hwrm_tunnel_dst_port_free_input {
 	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
 		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
-		HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1
+		HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
 	uint8_t	unused_0;
 	/*
 	 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
@@ -25025,6 +26794,52 @@ struct ctx_hw_stats {
 	uint64_t	tpa_aborts;
 } __attribute__((packed));
 
+/* Periodic Engine statistics context DMA to host. */
+/* ctx_eng_stats (size:512b/64B) */
+struct ctx_eng_stats {
+	/*
+	 * Count of data bytes into the Engine.
+	 * This includes any user supplied prefix,
+	 * but does not include any predefined
+	 * prefix data.
+	 */
+	uint64_t	eng_bytes_in;
+	/* Count of data bytes out of the Engine. */
+	uint64_t	eng_bytes_out;
+	/*
+	 * Count, in 4-byte (dword) units, of bytes
+	 * that are input as auxillary data.
+	 * This includes the aux_cmd data.
+	 */
+	uint64_t	aux_bytes_in;
+	/*
+	 * Count, in 4-byte (dword) units, of bytes
+	 * that are output as auxillary data.
+	 * This count is the buffer space for aux_data
+	 * output provided in the RQE, not the actual
+	 * aux_data written
+	 */
+	uint64_t	aux_bytes_out;
+	/* Count of number of commands executed. */
+	uint64_t	commands;
+	/*
+	 * Count of number of error commands.
+	 * These are the commands with a
+	 * non-zero status value.
+	 */
+	uint64_t	error_commands;
+	/*
+	 * Compression/Encryption Engine usage,
+	 * the unit is count of clock cycles
+	 */
+	uint64_t	cce_engine_usage;
+	/*
+	 * De-Compression/De-cryption Engine usage,
+	 * the unit is count of clock cycles
+	 */
+	uint64_t	cdd_engine_usage;
+} __attribute__((packed));
+
 /***********************
  * hwrm_stat_ctx_alloc *
  ***********************/
@@ -25081,7 +26896,7 @@ struct hwrm_stat_ctx_alloc_input {
 	 * than offloaded RoCE traffic shall not be included in this
 	 * statistic context.
 	 * When this bit is set to '0', the statistics context shall be
-	 * used for the network traffic other than offloaded RoCE traffic.
+	 * used for network traffic or engine traffic.
 	 */
 	#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE     UINT32_C(0x1)
 	uint8_t	unused_0[3];
@@ -25272,6 +27087,107 @@ struct hwrm_stat_ctx_query_output {
 	uint8_t	valid;
 } __attribute__((packed));
 
+/***************************
+ * hwrm_stat_ctx_eng_query *
+ ***************************/
+
+
+/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
+struct hwrm_stat_ctx_eng_query_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFE - Reserved for internal processors
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/* ID of the statistics context that is being queried. */
+	uint32_t	stat_ctx_id;
+	uint8_t	unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
+struct hwrm_stat_ctx_eng_query_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/*
+	 * Count of data bytes into the Engine.
+	 * This includes any user supplied prefix,
+	 * but does not include any predefined
+	 * prefix data.
+	 */
+	uint64_t	eng_bytes_in;
+	/* Count of data bytes out of the Engine. */
+	uint64_t	eng_bytes_out;
+	/*
+	 * Count, in 4-byte (dword) units, of bytes
+	 * that are input as auxillary data.
+	 * This includes the aux_cmd data.
+	 */
+	uint64_t	aux_bytes_in;
+	/*
+	 * Count, in 4-byte (dword) units, of bytes
+	 * that are output as auxillary data.
+	 * This count is the buffer space for aux_data
+	 * output provided in the RQE, not the actual
+	 * aux_data written
+	 */
+	uint64_t	aux_bytes_out;
+	/* Count of number of commands executed. */
+	uint64_t	commands;
+	/*
+	 * Count of number of error commands.
+	 * These are the commands with a
+	 * non-zero status value.
+	 */
+	uint64_t	error_commands;
+	/*
+	 * Compression/Encryption Engine usage,
+	 * the unit is count of clock cycles
+	 */
+	uint64_t	cce_engine_usage;
+	/*
+	 * De-Compression/De-cryption Engine usage,
+	 * the unit is count of clock cycles
+	 */
+	uint64_t	cdd_engine_usage;
+	uint8_t	unused_0[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __attribute__((packed));
+
 /***************************
  * hwrm_stat_ctx_clr_stats *
  ***************************/
-- 
2.17.1


  parent reply index

Thread overview: 75+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 01/11] net/bnxt: move tx bd checking to header file Ajit Khaparde
2019-05-23 11:44   ` Maxime Coquelin
2019-05-21 21:39 ` [dpdk-dev] [PATCH 02/11] net/bnxt: compute and store scattered RX status Ajit Khaparde
2019-05-23 11:47   ` Maxime Coquelin
2019-05-21 21:39 ` [dpdk-dev] [PATCH 03/11] net/bnxt: implement vector mode driver Ajit Khaparde
2019-05-23 12:18   ` Maxime Coquelin
2019-05-23 19:23     ` Lance Richardson
2019-05-21 21:39 ` [dpdk-dev] [PATCH 04/11] net/bnxt: fix double counting VLAN tags Ajit Khaparde
2019-05-23 12:21   ` Maxime Coquelin
2019-05-23 18:53     ` Lance Richardson
2019-05-21 21:39 ` [dpdk-dev] [PATCH 05/11] net/bnxt: fix RSS reta indirection table update Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 06/11] net/bnxt: use reta update mask and translate qid to grp id Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 07/11] net/bnxt: fix reta query op Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 08/11] net/bnxt: update HWRM API Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 09/11] net/bnxt: update HWRM version Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 10/11] net/bnxt: HWRM version update Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 11/11] net/bnxt: update release notes for bnxt Ajit Khaparde
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
2019-05-24 14:49   ` [dpdk-dev] [PATCH v2 01/10] net/bnxt: move tx bd checking to header file Lance Richardson
2019-05-27  9:36     ` Ferruh Yigit
2019-05-27 15:24       ` Ferruh Yigit
2019-05-27 18:50         ` Lance Richardson
2019-05-24 14:49   ` [dpdk-dev] [PATCH v2 02/10] net/bnxt: compute and store scattered RX status Lance Richardson
2019-05-24 14:49   ` [dpdk-dev] [PATCH v2 03/10] net/bnxt: implement vector mode driver Lance Richardson
2019-05-28  9:05     ` Ferruh Yigit
2019-05-28  9:08     ` Ferruh Yigit
2019-05-28 11:23       ` Lance Richardson
2019-05-24 14:49   ` [dpdk-dev] [PATCH v2 04/10] net/bnxt: fix RSS reta indirection table update Lance Richardson
2019-05-24 14:49   ` [dpdk-dev] [PATCH v2 05/10] net/bnxt: use reta update mask and translate qid to grp id Lance Richardson
2019-05-24 14:49   ` [dpdk-dev] [PATCH v2 06/10] net/bnxt: fix reta query op Lance Richardson
2019-05-24 14:49   ` [dpdk-dev] [PATCH v2 07/10] net/bnxt: update HWRM API Lance Richardson
2019-05-24 14:49   ` [dpdk-dev] [PATCH v2 08/10] net/bnxt: update HWRM version Lance Richardson
2019-05-24 14:49   ` [dpdk-dev] [PATCH v2 09/10] net/bnxt: HWRM version update Lance Richardson
2019-05-28  9:12     ` Ferruh Yigit
2019-05-28 15:06       ` Lance Richardson
2019-05-24 14:49   ` [dpdk-dev] [PATCH v2 10/10] net/bnxt: update release notes for bnxt Lance Richardson
2019-05-28  9:15     ` Ferruh Yigit
2019-05-28  9:19   ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Ferruh Yigit
2019-05-28 15:11     ` Lance Richardson
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 0/8] " Lance Richardson
2019-05-28 19:23   ` [dpdk-dev] [PATCH v3 1/8] net/bnxt: update release notes for bnxt Lance Richardson
2019-05-28 19:23   ` [dpdk-dev] [PATCH v3 2/8] net/bnxt: move Tx bd checking to header file Lance Richardson
2019-05-28 19:23   ` [dpdk-dev] [PATCH v3 3/8] net/bnxt: compute and store scattered Rx status Lance Richardson
2019-05-28 19:23   ` [dpdk-dev] [PATCH v3 4/8] net/bnxt: implement vector mode driver Lance Richardson
2019-05-29  6:48     ` Maxime Coquelin
2019-05-29 13:19       ` Lance Richardson
2019-05-28 19:23   ` [dpdk-dev] [PATCH v3 5/8] net/bnxt: fix RSS RETA indirection table ops Lance Richardson
2019-05-28 19:23   ` [dpdk-dev] [PATCH v3 6/8] net/bnxt: update HWRM API to version 1.10.0.19 Lance Richardson
2019-05-28 19:23   ` [dpdk-dev] [PATCH v3 7/8] net/bnxt: update HWRM API to version 1.10.0.48 Lance Richardson
2019-05-28 19:23   ` [dpdk-dev] [PATCH v3 8/8] net/bnxt: update HWRM API to version 1.10.0.74 Lance Richardson
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 0/8] bnxt patchset Lance Richardson
2019-05-29 15:02   ` [dpdk-dev] [PATCH v4 1/8] net/bnxt: update release notes for bnxt Lance Richardson
2019-05-29 18:16     ` Kevin Traynor
2019-05-29 20:28       ` Lance Richardson
2019-05-29 20:35         ` Lance Richardson
2019-05-29 20:38           ` Lance Richardson
2019-05-29 15:02   ` [dpdk-dev] [PATCH v4 2/8] net/bnxt: move Tx bd checking to header file Lance Richardson
2019-05-29 15:02   ` [dpdk-dev] [PATCH v4 3/8] net/bnxt: compute and store scattered Rx status Lance Richardson
2019-05-29 15:02   ` [dpdk-dev] [PATCH v4 4/8] net/bnxt: implement vector mode driver Lance Richardson
2019-05-29 15:02   ` [dpdk-dev] [PATCH v4 5/8] net/bnxt: fix RSS RETA indirection table ops Lance Richardson
2019-05-29 15:02   ` Lance Richardson [this message]
2019-05-29 15:02   ` [dpdk-dev] [PATCH v4 7/8] net/bnxt: update HWRM API to version 1.10.0.48 Lance Richardson
2019-05-29 15:02   ` [dpdk-dev] [PATCH v4 8/8] net/bnxt: update HWRM API to version 1.10.0.74 Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Lance Richardson
2019-05-29 21:02   ` [dpdk-dev] [PATCH v5 1/8] net/bnxt: update release notes for bnxt Lance Richardson
2019-05-29 21:02   ` [dpdk-dev] [PATCH v5 2/8] net/bnxt: move Tx bd checking to header file Lance Richardson
2019-05-29 21:02   ` [dpdk-dev] [PATCH v5 3/8] net/bnxt: compute and store scattered Rx status Lance Richardson
2019-05-29 21:02   ` [dpdk-dev] [PATCH v5 4/8] net/bnxt: implement vector mode driver Lance Richardson
2019-05-29 21:02   ` [dpdk-dev] [PATCH v5 5/8] net/bnxt: fix RSS RETA indirection table ops Lance Richardson
2019-05-29 21:02   ` [dpdk-dev] [PATCH v5 6/8] net/bnxt: update HWRM API to version 1.10.0.19 Lance Richardson
2019-05-29 21:02   ` [dpdk-dev] [PATCH v5 7/8] net/bnxt: update HWRM API to version 1.10.0.48 Lance Richardson
2019-05-29 21:02   ` [dpdk-dev] [PATCH v5 8/8] net/bnxt: update HWRM API to version 1.10.0.74 Lance Richardson
2019-06-04 16:07   ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Ferruh Yigit
2019-06-14 15:34     ` Ferruh Yigit

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