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From: <pbhagavatula@marvell.com>
To: <jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>
Cc: <dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>
Subject: [dpdk-dev]  [PATCH 13/44] event/octeontx2: add xstats support
Date: Sun, 2 Jun 2019 00:23:23 +0530
Message-ID: <20190601185355.370-14-pbhagavatula@marvell.com> (raw)
In-Reply-To: <20190601185355.370-1-pbhagavatula@marvell.com>

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Add support for retrieving statistics from SSO GWS and GGRP.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/event/octeontx2/otx2_evdev.c       |   5 +
 drivers/event/octeontx2/otx2_evdev_stats.h | 242 +++++++++++++++++++++
 2 files changed, 247 insertions(+)
 create mode 100644 drivers/event/octeontx2/otx2_evdev_stats.h

diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c
index 7adde59a3..ff9f905b3 100644
--- a/drivers/event/octeontx2/otx2_evdev.c
+++ b/drivers/event/octeontx2/otx2_evdev.c
@@ -12,6 +12,7 @@
 #include <rte_mbuf_pool_ops.h>
 #include <rte_pci.h>
 
+#include "otx2_evdev_stats.h"
 #include "otx2_evdev.h"
 #include "otx2_irq.h"
 
@@ -758,6 +759,10 @@ static struct rte_eventdev_ops otx2_sso_ops = {
 	.port_unlink      = otx2_sso_port_unlink,
 	.timeout_ticks    = otx2_sso_timeout_ticks,
 
+	.xstats_get       = otx2_sso_xstats_get,
+	.xstats_reset     = otx2_sso_xstats_reset,
+	.xstats_get_names = otx2_sso_xstats_get_names,
+
 	.dump             = otx2_sso_dump,
 };
 
diff --git a/drivers/event/octeontx2/otx2_evdev_stats.h b/drivers/event/octeontx2/otx2_evdev_stats.h
new file mode 100644
index 000000000..df76a1333
--- /dev/null
+++ b/drivers/event/octeontx2/otx2_evdev_stats.h
@@ -0,0 +1,242 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#ifndef __OTX2_EVDEV_STATS_H__
+#define __OTX2_EVDEV_STATS_H__
+
+#include "otx2_evdev.h"
+
+struct otx2_sso_xstats_name {
+	const char name[RTE_EVENT_DEV_XSTATS_NAME_SIZE];
+	const size_t offset;
+	const uint64_t mask;
+	const uint8_t shift;
+	uint64_t reset_snap[OTX2_SSO_MAX_VHGRP];
+};
+
+static struct otx2_sso_xstats_name sso_hws_xstats[] = {
+	{"last_grp_serviced",	offsetof(struct sso_hws_stats, arbitration),
+				0x3FF, 0, {0} },
+	{"affinity_arbitration_credits",
+				offsetof(struct sso_hws_stats, arbitration),
+				0xF, 16, {0} },
+};
+
+static struct otx2_sso_xstats_name sso_grp_xstats[] = {
+	{"wrk_sched",		offsetof(struct sso_grp_stats, ws_pc), ~0x0, 0,
+				{0} },
+	{"xaq_dram",		offsetof(struct sso_grp_stats, ext_pc), ~0x0,
+				0, {0} },
+	{"add_wrk",		offsetof(struct sso_grp_stats, wa_pc), ~0x0, 0,
+				{0} },
+	{"tag_switch_req",	offsetof(struct sso_grp_stats, ts_pc), ~0x0, 0,
+				{0} },
+	{"desched_req",		offsetof(struct sso_grp_stats, ds_pc), ~0x0, 0,
+				{0} },
+	{"desched_wrk",		offsetof(struct sso_grp_stats, dq_pc), ~0x0, 0,
+				{0} },
+	{"xaq_cached",		offsetof(struct sso_grp_stats, aw_status), 0x3,
+				0, {0} },
+	{"work_inflight",	offsetof(struct sso_grp_stats, aw_status), 0x3F,
+				16, {0} },
+	{"inuse_pages",		offsetof(struct sso_grp_stats, page_cnt),
+				0xFFFFFFFF, 0, {0} },
+};
+
+#define OTX2_SSO_NUM_HWS_XSTATS RTE_DIM(sso_hws_xstats)
+#define OTX2_SSO_NUM_GRP_XSTATS RTE_DIM(sso_grp_xstats)
+
+#define OTX2_SSO_NUM_XSTATS (OTX2_SSO_NUM_HWS_XSTATS + OTX2_SSO_NUM_GRP_XSTATS)
+
+static int
+otx2_sso_xstats_get(const struct rte_eventdev *event_dev,
+		    enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,
+		    const unsigned int ids[], uint64_t values[], unsigned int n)
+{
+	struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
+	struct otx2_sso_xstats_name *xstats;
+	struct otx2_sso_xstats_name *xstat;
+	struct otx2_mbox *mbox = dev->mbox;
+	uint32_t xstats_mode_count = 0;
+	uint32_t start_offset = 0;
+	unsigned int i;
+	uint64_t value;
+	void *req_rsp;
+	int rc;
+
+	switch (mode) {
+	case RTE_EVENT_DEV_XSTATS_DEVICE:
+		break;
+	case RTE_EVENT_DEV_XSTATS_PORT:
+		if (queue_port_id >= (signed int)dev->nb_event_ports)
+			goto invalid_value;
+
+		xstats_mode_count = OTX2_SSO_NUM_HWS_XSTATS;
+		xstats = sso_hws_xstats;
+
+		req_rsp = otx2_mbox_alloc_msg_sso_hws_get_stats(mbox);
+			((struct sso_info_req *)req_rsp)->hws = queue_port_id;
+		rc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);
+		if (rc < 0)
+			goto invalid_value;
+
+		break;
+	case RTE_EVENT_DEV_XSTATS_QUEUE:
+		if (queue_port_id >= (signed int)dev->nb_event_queues)
+			goto invalid_value;
+
+		xstats_mode_count = OTX2_SSO_NUM_GRP_XSTATS;
+		start_offset = OTX2_SSO_NUM_HWS_XSTATS;
+		xstats = sso_grp_xstats;
+
+		req_rsp = otx2_mbox_alloc_msg_sso_grp_get_stats(mbox);
+			((struct sso_info_req *)req_rsp)->grp = queue_port_id;
+		rc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);
+		if (rc < 0)
+			goto invalid_value;
+
+		break;
+	default:
+		otx2_err("Invalid mode received");
+		goto invalid_value;
+	};
+
+	for (i = 0; i < n && i < xstats_mode_count; i++) {
+		xstat = &xstats[ids[i] - start_offset];
+		value = *(uint64_t *)((char *)req_rsp + xstat->offset);
+		value = (value >> xstat->shift) & xstat->mask;
+
+		values[i] = value;
+		values[i] -= xstat->reset_snap[queue_port_id];
+	}
+
+	return i;
+invalid_value:
+	return -EINVAL;
+}
+
+static int
+otx2_sso_xstats_reset(struct rte_eventdev *event_dev,
+		      enum rte_event_dev_xstats_mode mode,
+		      int16_t queue_port_id, const uint32_t ids[], uint32_t n)
+{
+	struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
+	struct otx2_sso_xstats_name *xstats;
+	struct otx2_sso_xstats_name *xstat;
+	struct otx2_mbox *mbox = dev->mbox;
+	uint32_t xstats_mode_count = 0;
+	uint32_t start_offset = 0;
+	unsigned int i;
+	uint64_t value;
+	void *req_rsp;
+	int rc;
+
+	switch (mode) {
+	case RTE_EVENT_DEV_XSTATS_DEVICE:
+		return 0;
+	case RTE_EVENT_DEV_XSTATS_PORT:
+		if (queue_port_id >= (signed int)dev->nb_event_ports)
+			goto invalid_value;
+
+		xstats_mode_count = OTX2_SSO_NUM_HWS_XSTATS;
+		xstats = sso_hws_xstats;
+
+		req_rsp = otx2_mbox_alloc_msg_sso_hws_get_stats(mbox);
+		((struct sso_info_req *)req_rsp)->hws = queue_port_id;
+		rc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);
+		if (rc < 0)
+			goto invalid_value;
+
+		break;
+	case RTE_EVENT_DEV_XSTATS_QUEUE:
+		if (queue_port_id >= (signed int)dev->nb_event_queues)
+			goto invalid_value;
+
+		xstats_mode_count = OTX2_SSO_NUM_GRP_XSTATS;
+		start_offset = OTX2_SSO_NUM_HWS_XSTATS;
+		xstats = sso_grp_xstats;
+
+		req_rsp = otx2_mbox_alloc_msg_sso_grp_get_stats(mbox);
+			((struct sso_info_req *)req_rsp)->grp = queue_port_id;
+		rc = otx2_mbox_process_msg(mbox, (void *)&req_rsp);
+		if (rc < 0)
+			goto invalid_value;
+
+		break;
+	default:
+		otx2_err("Invalid mode received");
+		goto invalid_value;
+	};
+
+	for (i = 0; i < n && i < xstats_mode_count; i++) {
+		xstat = &xstats[ids[i] - start_offset];
+		value = *(uint64_t *)((char *)req_rsp + xstat->offset);
+		value = (value >> xstat->shift) & xstat->mask;
+
+		xstat->reset_snap[queue_port_id] =  value;
+	}
+	return i;
+invalid_value:
+	return -EINVAL;
+}
+
+static int
+otx2_sso_xstats_get_names(const struct rte_eventdev *event_dev,
+			  enum rte_event_dev_xstats_mode mode,
+			  uint8_t queue_port_id,
+			  struct rte_event_dev_xstats_name *xstats_names,
+			  unsigned int *ids, unsigned int size)
+{
+	struct rte_event_dev_xstats_name xstats_names_copy[OTX2_SSO_NUM_XSTATS];
+	struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
+	uint32_t xstats_mode_count = 0;
+	uint32_t start_offset = 0;
+	unsigned int xidx = 0;
+	unsigned int i;
+
+	for (i = 0; i < OTX2_SSO_NUM_HWS_XSTATS; i++) {
+		snprintf(xstats_names_copy[i].name,
+			 sizeof(xstats_names_copy[i].name), "%s",
+			 sso_hws_xstats[i].name);
+	}
+
+	for (; i < OTX2_SSO_NUM_XSTATS; i++) {
+		snprintf(xstats_names_copy[i].name,
+			 sizeof(xstats_names_copy[i].name), "%s",
+			 sso_grp_xstats[i - OTX2_SSO_NUM_HWS_XSTATS].name);
+	}
+
+	switch (mode) {
+	case RTE_EVENT_DEV_XSTATS_DEVICE:
+		break;
+	case RTE_EVENT_DEV_XSTATS_PORT:
+		if (queue_port_id >= (signed int)dev->nb_event_ports)
+			break;
+		xstats_mode_count = OTX2_SSO_NUM_HWS_XSTATS;
+		break;
+	case RTE_EVENT_DEV_XSTATS_QUEUE:
+		if (queue_port_id >= (signed int)dev->nb_event_queues)
+			break;
+		xstats_mode_count = OTX2_SSO_NUM_GRP_XSTATS;
+		start_offset = OTX2_SSO_NUM_HWS_XSTATS;
+		break;
+	default:
+		otx2_err("Invalid mode received");
+		return -EINVAL;
+	};
+
+	if (xstats_mode_count > size || !ids || !xstats_names)
+		return xstats_mode_count;
+
+	for (i = 0; i < xstats_mode_count; i++) {
+		xidx = i + start_offset;
+		strncpy(xstats_names[i].name, xstats_names_copy[xidx].name,
+			sizeof(xstats_names[i].name));
+		ids[i] = xidx;
+	}
+
+	return i;
+}
+
+#endif
-- 
2.21.0


  parent reply index

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-01 18:53 [dpdk-dev] [PATCH 00/44] OCTEON TX2 event device driver pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 01/44] event/octeontx2: add build infra and device probe pbhagavatula
2019-06-17  7:50   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 02/44] event/octeontx2: add init and fini for octeontx2 SSO object pbhagavatula
2019-06-17  7:52   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 03/44] event/octeontx2: add device capabilities function pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 04/44] event/octeontx2: add device configure function pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 05/44] event/octeontx2: add event queue config functions pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 06/44] event/octeontx2: allocate event inflight buffers pbhagavatula
2019-06-17  7:56   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 07/44] event/octeontx2: add devargs for inflight buffer count pbhagavatula
2019-06-17  7:58   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 08/44] event/octeontx2: add event port config functions pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 09/44] event/octeontx2: support linking queues to ports pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 10/44] event/octeontx2: support dequeue timeout tick conversion pbhagavatula
2019-06-17  8:01   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 11/44] event/octeontx2: add SSO GWS and GGRP IRQ handlers pbhagavatula
2019-06-17  8:04   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 12/44] event/octeontx2: add register dump functions pbhagavatula
2019-06-01 18:53 ` pbhagavatula [this message]
2019-06-01 18:53 ` [dpdk-dev] [PATCH 14/44] event/octeontx2: add SSO HW device operations pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 15/44] event/octeontx2: add worker enqueue functions pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 16/44] event/octeontx2: add worker dequeue functions pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 17/44] event/octeontx2: add octeontx2 SSO dual workslot mode pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 18/44] event/octeontx2: add SSO dual GWS HW device operations pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 19/44] event/octeontx2: add worker dual GWS enqueue functions pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 20/44] event/octeontx2: add worker dual GWS dequeue functions pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 21/44] event/octeontx2: add devargs to force legacy mode pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 22/44] event/octeontx2: add device start function pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 23/44] event/octeontx2: add devargs to control SSO GGRP QoS pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 24/44] event/octeontx2: add device stop and close functions pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 25/44] event/octeontx2: add SSO selftest pbhagavatula
2019-06-17  8:18   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 26/44] doc: add Marvell OCTEON TX2 event device documentation pbhagavatula
2019-06-17  8:15   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 27/44] event/octeontx2: add event timer support pbhagavatula
2019-06-17  8:20   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 28/44] event/octeontx2: add timer adapter capabilities pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 29/44] event/octeontx2: create and free timer adapter pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 30/44] event/octeontx2: allow TIM to optimize config pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 31/44] event/octeontx2: add devargs to disable NPA pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 32/44] event/octeontx2: add devargs to modify chunk slots pbhagavatula
2019-06-17  8:24   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 33/44] event/octeontx2: add TIM IRQ handlers pbhagavatula
2019-06-17  8:25   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 34/44] event/octeontx2: allow adapters to resize inflight buffers pbhagavatula
2019-06-17  8:27   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 35/44] event/octeontx2: add timer adapter info get function pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 36/44] event/octeontx2: add TIM bucket operations pbhagavatula
2019-06-17  8:31   ` Jerin Jacob Kollanukkaran
2019-06-01 18:53 ` [dpdk-dev] [PATCH 37/44] event/octeontx2: add event timer arm routine pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 38/44] event/octeontx2: add event timer arm timeout burst pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 39/44] event/octeontx2: add event timer cancel function pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 40/44] event/octeontx2: add event timer stats get and reset pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 41/44] event/octeontx2: add even timer adapter start and stop pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 42/44] event/octeontx2: add devargs to limit timer adapters pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 43/44] event/octeontx2: add devargs to control adapter parameters pbhagavatula
2019-06-01 18:53 ` [dpdk-dev] [PATCH 44/44] doc: update Marvell OCTEON TX2 eventdev documentation pbhagavatula

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