From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 378A9C47404 for ; Mon, 7 Oct 2019 16:29:41 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id D193C206C0 for ; Mon, 7 Oct 2019 16:29:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D193C206C0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BD3131D14E; Mon, 7 Oct 2019 18:29:09 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 860B61C20B for ; Mon, 7 Oct 2019 18:29:03 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 09:29:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,268,1566889200"; d="scan'208";a="393082026" Received: from silpixa00398673.ir.intel.com (HELO silpixa00398673.ger.corp.intel.com) ([10.237.223.136]) by fmsmga005.fm.intel.com with ESMTP; 07 Oct 2019 09:29:01 -0700 From: Fan Zhang To: dev@dpdk.org Cc: konstantin.ananyev@intel.com, declan.doherty@intel.com, akhil.goyal@nxp.com, Fan Zhang Date: Mon, 7 Oct 2019 17:28:44 +0100 Message-Id: <20191007162850.60552-5-roy.fan.zhang@intel.com> X-Mailer: git-send-email 2.14.5 In-Reply-To: <20191007162850.60552-1-roy.fan.zhang@intel.com> References: <20190906131330.40185-1-roy.fan.zhang@intel.com> <20191007162850.60552-1-roy.fan.zhang@intel.com> Subject: [dpdk-dev] [PATCH v2 04/10] app/test: add security cpu crypto perftest X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Since crypto perf application does not support rte_security, this patch adds a simple GCM CPU crypto performance test to crypto unittest application. The test includes different key and data sizes test with single buffer and SGL buffer test items and will display the throughput as well as cycle count performance information. Signed-off-by: Fan Zhang --- app/test/test_security_cpu_crypto.c | 201 ++++++++++++++++++++++++++++++++++++ 1 file changed, 201 insertions(+) diff --git a/app/test/test_security_cpu_crypto.c b/app/test/test_security_cpu_crypto.c index d345922b2..ca9a8dae6 100644 --- a/app/test/test_security_cpu_crypto.c +++ b/app/test/test_security_cpu_crypto.c @@ -23,6 +23,7 @@ #define CPU_CRYPTO_TEST_MAX_AAD_LENGTH 16 #define MAX_NB_SIGMENTS 4 +#define CACHE_WARM_ITER 2048 enum buffer_assemble_option { SGL_MAX_SEG, @@ -560,5 +561,205 @@ test_security_cpu_crypto_aesni_gcm(void) return unit_test_suite_runner(&security_cpu_crypto_aesgcm_testsuite); } + +static inline void +gen_rand(uint8_t *data, uint32_t len) +{ + uint32_t i; + + for (i = 0; i < len; i++) + data[i] = (uint8_t)rte_rand(); +} + +static inline void +switch_aead_enc_to_dec(struct aead_test_data *tdata, + struct cpu_crypto_test_case *tcase, + enum buffer_assemble_option sgl_option) +{ + uint32_t i; + uint8_t *dst = tdata->ciphertext.data; + + switch (sgl_option) { + case SGL_ONE_SEG: + memcpy(dst, tcase->seg_buf[0].seg, tcase->seg_buf[0].seg_len); + tdata->ciphertext.len = tcase->seg_buf[0].seg_len; + break; + case SGL_MAX_SEG: + tdata->ciphertext.len = 0; + for (i = 0; i < MAX_NB_SIGMENTS; i++) { + memcpy(dst, tcase->seg_buf[i].seg, + tcase->seg_buf[i].seg_len); + tdata->ciphertext.len += tcase->seg_buf[i].seg_len; + } + break; + } + + memcpy(tdata->auth_tag.data, tcase->digest, tdata->auth_tag.len); +} + +static int +cpu_crypto_test_aead_perf(enum buffer_assemble_option sgl_option, + uint32_t key_sz) +{ + struct aead_test_data tdata = {0}; + struct cpu_crypto_testsuite_params *ts_params = &testsuite_params; + struct cpu_crypto_unittest_params *ut_params = &unittest_params; + struct cpu_crypto_test_obj *obj = &ut_params->test_obj; + struct cpu_crypto_test_case *tcase; + uint64_t hz = rte_get_tsc_hz(), time_start, time_now; + double rate, cycles_per_buf; + uint32_t test_data_szs[] = {64, 128, 256, 512, 1024, 2048}; + uint32_t i, j; + uint8_t aad[16]; + int ret; + + tdata.key.len = key_sz; + gen_rand(tdata.key.data, tdata.key.len); + tdata.algo = RTE_CRYPTO_AEAD_AES_GCM; + tdata.aad.data = aad; + + ut_params->sess = create_aead_session(ts_params->ctx, + ts_params->session_priv_mpool, + RTE_CRYPTO_AEAD_OP_DECRYPT, + &tdata, + 0); + if (!ut_params->sess) + return -1; + + ret = allocate_buf(MAX_NUM_OPS_INFLIGHT); + if (ret) + return ret; + + for (i = 0; i < RTE_DIM(test_data_szs); i++) { + for (j = 0; j < MAX_NUM_OPS_INFLIGHT; j++) { + tdata.plaintext.len = test_data_szs[i]; + gen_rand(tdata.plaintext.data, + tdata.plaintext.len); + + tdata.aad.len = 12; + gen_rand(tdata.aad.data, tdata.aad.len); + + tdata.auth_tag.len = 16; + + tdata.iv.len = 16; + gen_rand(tdata.iv.data, tdata.iv.len); + + tcase = ut_params->test_datas[j]; + ret = assemble_aead_buf(tcase, obj, j, + RTE_CRYPTO_AEAD_OP_ENCRYPT, + &tdata, sgl_option, 0); + if (ret < 0) { + printf("Test is not supported by the driver\n"); + return ret; + } + } + + /* warm up cache */ + for (j = 0; j < CACHE_WARM_ITER; j++) + run_test(ts_params->ctx, ut_params->sess, obj, + MAX_NUM_OPS_INFLIGHT); + + time_start = rte_rdtsc(); + + run_test(ts_params->ctx, ut_params->sess, obj, + MAX_NUM_OPS_INFLIGHT); + + time_now = rte_rdtsc(); + + rate = time_now - time_start; + cycles_per_buf = rate / MAX_NUM_OPS_INFLIGHT; + + rate = ((hz / cycles_per_buf)) / 1000000; + + printf("AES-GCM-%u(%4uB) Enc %03.3fMpps (%03.3fGbps) ", + key_sz * 8, test_data_szs[i], rate, + rate * test_data_szs[i] * 8 / 1000); + printf("cycles per buf %03.3f per byte %03.3f\n", + cycles_per_buf, + cycles_per_buf / test_data_szs[i]); + + for (j = 0; j < MAX_NUM_OPS_INFLIGHT; j++) { + tcase = ut_params->test_datas[j]; + + switch_aead_enc_to_dec(&tdata, tcase, sgl_option); + ret = assemble_aead_buf(tcase, obj, j, + RTE_CRYPTO_AEAD_OP_DECRYPT, + &tdata, sgl_option, 0); + if (ret < 0) { + printf("Test is not supported by the driver\n"); + return ret; + } + } + + time_start = rte_get_timer_cycles(); + + run_test(ts_params->ctx, ut_params->sess, obj, + MAX_NUM_OPS_INFLIGHT); + + time_now = rte_get_timer_cycles(); + + rate = time_now - time_start; + cycles_per_buf = rate / MAX_NUM_OPS_INFLIGHT; + + rate = ((hz / cycles_per_buf)) / 1000000; + + printf("AES-GCM-%u(%4uB) Dec %03.3fMpps (%03.3fGbps) ", + key_sz * 8, test_data_szs[i], rate, + rate * test_data_szs[i] * 8 / 1000); + printf("cycles per buf %03.3f per byte %03.3f\n", + cycles_per_buf, + cycles_per_buf / test_data_szs[i]); + } + + return 0; +} + +/* test-perfix/key-size/sgl-type */ +#define all_gcm_perf_test_cases(type) \ + TEST_EXPAND(_128, 16, type) \ + TEST_EXPAND(_192, 24, type) \ + TEST_EXPAND(_256, 32, type) + +#define TEST_EXPAND(a, b, c) \ +static int \ +cpu_crypto_gcm_perf##a##_##c(void) \ +{ \ + return cpu_crypto_test_aead_perf(c, b); \ +} \ + +all_gcm_perf_test_cases(SGL_ONE_SEG) +all_gcm_perf_test_cases(SGL_MAX_SEG) +#undef TEST_EXPAND + +static struct unit_test_suite security_cpu_crypto_aesgcm_perf_testsuite = { + .suite_name = "Security CPU Crypto AESNI-GCM Perf Test Suite", + .setup = testsuite_setup, + .teardown = testsuite_teardown, + .unit_test_cases = { +#define TEST_EXPAND(a, b, c) \ + TEST_CASE_ST(ut_setup, ut_teardown, \ + cpu_crypto_gcm_perf##a##_##c), \ + + all_gcm_perf_test_cases(SGL_ONE_SEG) + all_gcm_perf_test_cases(SGL_MAX_SEG) +#undef TEST_EXPAND + + TEST_CASES_END() /**< NULL terminate unit test array */ + }, +}; + +static int +test_security_cpu_crypto_aesni_gcm_perf(void) +{ + gbl_driver_id = rte_cryptodev_driver_id_get( + RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD)); + + return unit_test_suite_runner( + &security_cpu_crypto_aesgcm_perf_testsuite); +} + REGISTER_TEST_COMMAND(security_aesni_gcm_autotest, test_security_cpu_crypto_aesni_gcm); + +REGISTER_TEST_COMMAND(security_aesni_gcm_perftest, + test_security_cpu_crypto_aesni_gcm_perf); -- 2.14.5