From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, HK_RANDOM_FROM,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D79FC33C9E for ; Wed, 15 Jan 2020 00:58:01 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id E5BFE24671 for ; Wed, 15 Jan 2020 00:58:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E5BFE24671 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2A20D1C123; Wed, 15 Jan 2020 01:57:39 +0100 (CET) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 4884B1C0D5 for ; Wed, 15 Jan 2020 01:57:31 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Jan 2020 16:57:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,320,1574150400"; d="scan'208";a="424844024" Received: from npg-dpdk-haiyue-1.sh.intel.com ([10.67.119.213]) by fmsmga006.fm.intel.com with ESMTP; 14 Jan 2020 16:57:29 -0800 From: Haiyue Wang To: dev@dpdk.org, xiaolong.ye@intel.com, qi.z.zhang@intel.com, qiming.yang@intel.com Cc: Haiyue Wang Date: Wed, 15 Jan 2020 08:50:28 +0800 Message-Id: <20200115005028.21026-5-haiyue.wang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200115005028.21026-1-haiyue.wang@intel.com> References: <20200115005028.21026-1-haiyue.wang@intel.com> Subject: [dpdk-dev] [PATCH v3 4/4] net/ice/base: osdep.h clean up X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove the unused definitions, rewrite the IO data read/write helpers, and put the common definitions related to RTE defines under the macro __INTEL_NET_BASE_OSDEP__, so it works like OS(RTE) dependency. Signed-off-by: Haiyue Wang --- drivers/net/ice/base/ice_osdep.h | 132 ++++++++++++++++--------------- 1 file changed, 67 insertions(+), 65 deletions(-) diff --git a/drivers/net/ice/base/ice_osdep.h b/drivers/net/ice/base/ice_osdep.h index 27c1830c5..45b9f3617 100644 --- a/drivers/net/ice/base/ice_osdep.h +++ b/drivers/net/ice/base/ice_osdep.h @@ -26,6 +26,9 @@ #include "../ice_logs.h" +#ifndef __INTEL_NET_BASE_OSDEP__ +#define __INTEL_NET_BASE_OSDEP__ + #define INLINE inline #define STATIC static @@ -38,17 +41,6 @@ typedef int32_t s32; typedef uint64_t u64; typedef uint64_t s64; -#define __iomem -#define hw_dbg(hw, S, A...) do {} while (0) -#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) -#define lower_32_bits(n) ((u32)(n)) -#define low_16_bits(x) ((x) & 0xFFFF) -#define high_16_bits(x) (((x) & 0xFFFF0000) >> 16) - -#ifndef ETH_ADDR_LEN -#define ETH_ADDR_LEN 6 -#endif - #ifndef __le16 #define __le16 uint16_t #endif @@ -68,6 +60,65 @@ typedef uint64_t s64; #define __be64 uint64_t #endif +#define min(a, b) RTE_MIN(a, b) +#define max(a, b) RTE_MAX(a, b) + +#define FIELD_SIZEOF(t, f) RTE_SIZEOF_FIELD(t, f) +#define ARRAY_SIZE(arr) RTE_DIM(arr) + +#define CPU_TO_LE16(o) rte_cpu_to_le_16(o) +#define CPU_TO_LE32(s) rte_cpu_to_le_32(s) +#define CPU_TO_LE64(h) rte_cpu_to_le_64(h) +#define LE16_TO_CPU(a) rte_le_to_cpu_16(a) +#define LE32_TO_CPU(c) rte_le_to_cpu_32(c) +#define LE64_TO_CPU(k) rte_le_to_cpu_64(k) + +#define CPU_TO_BE16(o) rte_cpu_to_be_16(o) +#define CPU_TO_BE32(o) rte_cpu_to_be_32(o) +#define CPU_TO_BE64(o) rte_cpu_to_be_64(o) + +#define NTOHS(a) rte_be_to_cpu_16(a) +#define NTOHL(a) rte_be_to_cpu_32(a) +#define HTONS(a) rte_cpu_to_be_16(a) +#define HTONL(a) rte_cpu_to_be_32(a) + +static __rte_always_inline uint32_t +readl(volatile void *addr) +{ + return rte_le_to_cpu_32(rte_read32(addr)); +} + +static __rte_always_inline void +writel(uint32_t value, volatile void *addr) +{ + rte_write32(rte_cpu_to_le_32(value), addr); +} + +static __rte_always_inline void +writel_relaxed(uint32_t value, volatile void *addr) +{ + rte_write32_relaxed(rte_cpu_to_le_32(value), addr); +} + +static __rte_always_inline uint64_t +readq(volatile void *addr) +{ + return rte_le_to_cpu_64(rte_read64(addr)); +} + +static __rte_always_inline void +writeq(uint64_t value, volatile void *addr) +{ + rte_write64(rte_cpu_to_le_64(value), addr); +} + +#define wr32(a, reg, value) writel((value), (a)->hw_addr + (reg)) +#define rd32(a, reg) readl((a)->hw_addr + (reg)) +#define wr64(a, reg, value) writeq((value), (a)->hw_addr + (reg)) +#define rd64(a, reg) readq((a)->hw_addr + (reg)) + +#endif /* __INTEL_NET_BASE_OSDEP__ */ + #ifndef __always_unused #define __always_unused __attribute__((unused)) #endif @@ -82,21 +133,8 @@ typedef uint64_t s64; #define BIT_ULL(a) (1ULL << (a)) #endif -#define FALSE 0 -#define TRUE 1 -#define false 0 -#define true 1 - -#define min(a, b) RTE_MIN(a, b) -#define max(a, b) RTE_MAX(a, b) - -#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) -#define FIELD_SIZEOF(t, f) (sizeof(((t *)0)->f)) #define MAKEMASK(m, s) ((m) << (s)) -#define DEBUGOUT(S, A...) PMD_DRV_LOG_RAW(DEBUG, S, ##A) -#define DEBUGFUNC(F) PMD_DRV_LOG_RAW(DEBUG, F) - #define ice_debug(h, m, s, ...) \ do { \ if (((m) & (h)->debug_mask)) \ @@ -123,37 +161,16 @@ do { \ #define SNPRINTF ice_snprintf #endif -#define ICE_PCI_REG(reg) rte_read32(reg) -#define ICE_PCI_REG_ADDR(a, reg) \ - ((volatile uint32_t *)((char *)(a)->hw_addr + (reg))) -#define ICE_PCI_REG64(reg) rte_read64(reg) -#define ICE_PCI_REG_ADDR64(a, reg) \ - ((volatile uint64_t *)((char *)(a)->hw_addr + (reg))) -static inline uint32_t ice_read_addr(volatile void *addr) -{ - return rte_le_to_cpu_32(ICE_PCI_REG(addr)); -} - -static inline uint64_t ice_read_addr64(volatile void *addr) -{ - return rte_le_to_cpu_64(ICE_PCI_REG64(addr)); -} +#define ICE_PCI_REG_WRITE(reg, value) writel(value, reg) -#define ICE_PCI_REG_WRITE(reg, value) \ - rte_write32((rte_cpu_to_le_32(value)), reg) +#define ICE_READ_REG(hw, reg) rd32(hw, reg) +#define ICE_WRITE_REG(hw, reg, value) wr32(hw, reg, value) #define ice_flush(a) ICE_READ_REG((a), GLGEN_STAT) #define icevf_flush(a) ICE_READ_REG((a), VFGEN_RSTAT) -#define ICE_READ_REG(hw, reg) ice_read_addr(ICE_PCI_REG_ADDR((hw), (reg))) -#define ICE_WRITE_REG(hw, reg, value) \ - ICE_PCI_REG_WRITE(ICE_PCI_REG_ADDR((hw), (reg)), (value)) - -#define rd32(a, reg) ice_read_addr(ICE_PCI_REG_ADDR((a), (reg))) -#define wr32(a, reg, value) \ - ICE_PCI_REG_WRITE(ICE_PCI_REG_ADDR((a), (reg)), (value)) -#define flush(a) ice_read_addr(ICE_PCI_REG_ADDR((a), (GLGEN_STAT))) + +#define flush(a) ICE_READ_REG((a), GLGEN_STAT) #define div64_long(n, d) ((n) / (d)) -#define rd64(a, reg) ice_read_addr64(ICE_PCI_REG_ADDR64((a), (reg))) #define BITS_PER_BYTE 8 @@ -178,21 +195,6 @@ struct ice_virt_mem { #define ice_memcpy(a, b, c, d) rte_memcpy((a), (b), (c)) #define ice_memdup(a, b, c, d) rte_memcpy(ice_malloc(a, c), b, c) -#define CPU_TO_BE16(o) rte_cpu_to_be_16(o) -#define CPU_TO_BE32(o) rte_cpu_to_be_32(o) -#define CPU_TO_BE64(o) rte_cpu_to_be_64(o) -#define CPU_TO_LE16(o) rte_cpu_to_le_16(o) -#define CPU_TO_LE32(s) rte_cpu_to_le_32(s) -#define CPU_TO_LE64(h) rte_cpu_to_le_64(h) -#define LE16_TO_CPU(a) rte_le_to_cpu_16(a) -#define LE32_TO_CPU(c) rte_le_to_cpu_32(c) -#define LE64_TO_CPU(k) rte_le_to_cpu_64(k) - -#define NTOHS(a) rte_be_to_cpu_16(a) -#define NTOHL(a) rte_be_to_cpu_32(a) -#define HTONS(a) rte_cpu_to_be_16(a) -#define HTONL(a) rte_cpu_to_be_32(a) - /* SW spinlock */ struct ice_lock { rte_spinlock_t spinlock; -- 2.17.1