From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 268A6C33CB1 for ; Tue, 14 Jan 2020 12:30:07 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id B49DB2467D for ; Tue, 14 Jan 2020 12:30:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B49DB2467D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A34F61C0D7; Tue, 14 Jan 2020 13:30:05 +0100 (CET) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 15E2F1C0D4 for ; Tue, 14 Jan 2020 13:30:03 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Jan 2020 04:30:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,432,1571727600"; d="scan'208";a="248418144" Received: from fyigit-mobl.ger.corp.intel.com (HELO [10.237.221.35]) ([10.237.221.35]) by fmsmga001.fm.intel.com with ESMTP; 14 Jan 2020 04:30:01 -0800 To: Selwin Sebastian , dev@dpdk.org Cc: thomas@monjalon.net, david.marchand@redhat.com References: <20200114173019.14097-1-Selwin.Sebastian@amd.com> From: Ferruh Yigit Autocrypt: addr=ferruh.yigit@intel.com; prefer-encrypt=mutual; keydata= mQINBFXZCFABEADCujshBOAaqPZpwShdkzkyGpJ15lmxiSr3jVMqOtQS/sB3FYLT0/d3+bvy qbL9YnlbPyRvZfnP3pXiKwkRoR1RJwEo2BOf6hxdzTmLRtGtwWzI9MwrUPj6n/ldiD58VAGQ +iR1I/z9UBUN/ZMksElA2D7Jgg7vZ78iKwNnd+vLBD6I61kVrZ45Vjo3r+pPOByUBXOUlxp9 GWEKKIrJ4eogqkVNSixN16VYK7xR+5OUkBYUO+sE6etSxCr7BahMPKxH+XPlZZjKrxciaWQb +dElz3Ab4Opl+ZT/bK2huX+W+NJBEBVzjTkhjSTjcyRdxvS1gwWRuXqAml/sh+KQjPV1PPHF YK5LcqLkle+OKTCa82OvUb7cr+ALxATIZXQkgmn+zFT8UzSS3aiBBohg3BtbTIWy51jNlYdy ezUZ4UxKSsFuUTPt+JjHQBvF7WKbmNGS3fCid5Iag4tWOfZoqiCNzxApkVugltxoc6rG2TyX CmI2rP0mQ0GOsGXA3+3c1MCdQFzdIn/5tLBZyKy4F54UFo35eOX8/g7OaE+xrgY/4bZjpxC1 1pd66AAtKb3aNXpHvIfkVV6NYloo52H+FUE5ZDPNCGD0/btFGPWmWRmkPybzColTy7fmPaGz cBcEEqHK4T0aY4UJmE7Ylvg255Kz7s6wGZe6IR3N0cKNv++O7QARAQABtCVGZXJydWggWWln aXQgPGZlcnJ1aC55aWdpdEBpbnRlbC5jb20+iQJUBBMBCgA+AhsDAh4BAheABQsJCAcDBRUK CQgLBRYCAwEAFiEE0jZTh0IuwoTjmYHH+TPrQ98TYR8FAl1meboFCQlupOoACgkQ+TPrQ98T YR9ACBAAv2tomhyxY0Tp9Up7mNGLfEdBu/7joB/vIdqMRv63ojkwr9orQq5V16V/25+JEAD0 60cKodBDM6HdUvqLHatS8fooWRueSXHKYwJ3vxyB2tWDyZrLzLI1jxEvunGodoIzUOtum0Ce gPynnfQCelXBja0BwLXJMplM6TY1wXX22ap0ZViC0m714U5U4LQpzjabtFtjT8qOUR6L7hfy YQ72PBuktGb00UR/N5UrR6GqB0x4W41aZBHXfUQnvWIMmmCrRUJX36hOTYBzh+x86ULgg7H2 1499tA4o6rvE13FiGccplBNWCAIroAe/G11rdoN5NBgYVXu++38gTa/MBmIt6zRi6ch15oLA Ln2vHOdqhrgDuxjhMpG2bpNE36DG/V9WWyWdIRlz3NYPCDM/S3anbHlhjStXHOz1uHOnerXM 1jEjcsvmj1vSyYoQMyRcRJmBZLrekvgZeh7nJzbPHxtth8M7AoqiZ/o/BpYU+0xZ+J5/szWZ aYxxmIRu5ejFf+Wn9s5eXNHmyqxBidpCWvcbKYDBnkw2+Y9E5YTpL0mS0dCCOlrO7gca27ux ybtbj84aaW1g0CfIlUnOtHgMCmz6zPXThb+A8H8j3O6qmPoVqT3qnq3Uhy6GOoH8Fdu2Vchh TWiF5yo+pvUagQP6LpslffufSnu+RKAagkj7/RSuZV25Ag0EV9ZMvgEQAKc0Db17xNqtSwEv mfp4tkddwW9XA0tWWKtY4KUdd/jijYqc3fDD54ESYpV8QWj0xK4YM0dLxnDU2IYxjEshSB1T qAatVWz9WtBYvzalsyTqMKP3w34FciuL7orXP4AibPtrHuIXWQOBECcVZTTOdZYGAzaYzxiA ONzF9eTiwIqe9/oaOjTwTLnOarHt16QApTYQSnxDUQljeNvKYt1lZE/gAUUxNLWsYyTT+22/ vU0GDUahsJxs1+f1yEr+OGrFiEAmqrzpF0lCS3f/3HVTU6rS9cK3glVUeaTF4+1SK5ZNO35p iVQCwphmxa+dwTG/DvvHYCtgOZorTJ+OHfvCnSVjsM4kcXGjJPy3JZmUtyL9UxEbYlrffGPQ I3gLXIGD5AN5XdAXFCjjaID/KR1c9RHd7Oaw0Pdcq9UtMLgM1vdX8RlDuMGPrj5sQrRVbgYH fVU/TQCk1C9KhzOwg4Ap2T3tE1umY/DqrXQgsgH71PXFucVjOyHMYXXugLT8YQ0gcBPHy9mZ qw5mgOI5lCl6d4uCcUT0l/OEtPG/rA1lxz8ctdFBVOQOxCvwRG2QCgcJ/UTn5vlivul+cThi 6ERPvjqjblLncQtRg8izj2qgmwQkvfj+h7Ex88bI8iWtu5+I3K3LmNz/UxHBSWEmUnkg4fJl Rr7oItHsZ0ia6wWQ8lQnABEBAAGJAjwEGAEKACYCGwwWIQTSNlOHQi7ChOOZgcf5M+tD3xNh HwUCXWZ5wAUJB3FgggAKCRD5M+tD3xNhH2O+D/9OEz62YuJQLuIuOfL67eFTIB5/1+0j8Tsu o2psca1PUQ61SZJZOMl6VwNxpdvEaolVdrpnSxUF31kPEvR0Igy8HysQ11pj8AcgH0a9FrvU /8k2Roccd2ZIdpNLkirGFZR7LtRw41Kt1Jg+lafI0efkiHKMT/6D/P1EUp1RxOBNtWGV2hrd 0Yg9ds+VMphHHU69fDH02SwgpvXwG8Qm14Zi5WQ66R4CtTkHuYtA63sS17vMl8fDuTCtvfPF HzvdJLIhDYN3Mm1oMjKLlq4PUdYh68Fiwm+boJoBUFGuregJFlO3hM7uHBDhSEnXQr5mqpPM 6R/7Q5BjAxrwVBisH0yQGjsWlnysRWNfExAE2sRePSl0or9q19ddkRYltl6X4FDUXy2DTXa9 a+Fw4e1EvmcF3PjmTYs9IE3Vc64CRQXkhujcN4ZZh5lvOpU8WgyDxFq7bavFnSS6kx7Tk29/ wNJBp+cf9qsQxLbqhW5kfORuZGecus0TLcmpZEFKKjTJBK9gELRBB/zoN3j41hlEl7uTUXTI JQFLhpsFlEdKLujyvT/aCwP3XWT+B2uZDKrMAElF6ltpTxI53JYi22WO7NH7MR16Fhi4R6vh FHNBOkiAhUpoXRZXaCR6+X4qwA8CwHGqHRBfYFSU/Ulq1ZLR+S3hNj2mbnSx0lBs1eEqe2vh cA== Message-ID: <79a6489b-8a0c-cf8f-6016-63fcafff4b32@intel.com> Date: Tue, 14 Jan 2020 12:30:00 +0000 MIME-Version: 1.0 In-Reply-To: <20200114173019.14097-1-Selwin.Sebastian@amd.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v3] drivers: add a HW quirk for register definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 1/14/2020 5:30 PM, Selwin Sebastian wrote: > V1000/R1000 processors are using the same PCI ids for the network > device as SNOWYOWL processor but has altered register definitions > for determining the window settings for the indirect PCS access. > Add support to check for this hardware and if found use the new > register values. > > Added a new routine rte_pci_search_device to pci driver to search > for a device. > > Signed-off-by: Selwin Sebastian > --- > drivers/bus/pci/pci_common.c | 17 +++++++++++++++++ > drivers/bus/pci/rte_bus_pci.h | 12 ++++++++++++ > drivers/net/axgbe/axgbe_common.h | 2 ++ > drivers/net/axgbe/axgbe_ethdev.c | 18 +++++++++++++++--- > 4 files changed, 46 insertions(+), 3 deletions(-) > > diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c > index 3f5542076..e991a2580 100644 > --- a/drivers/bus/pci/pci_common.c > +++ b/drivers/bus/pci/pci_common.c > @@ -393,6 +393,23 @@ rte_pci_add_device(struct rte_pci_device *pci_dev) > TAILQ_INSERT_TAIL(&rte_pci_bus.device_list, pci_dev, next); > } > > +/* Search for a specific device in PCI bus */ > + > +int > +rte_pci_search_device(int vendor_id, int device_id) > +{ > + struct rte_pci_device *pdev; > + pdev = TAILQ_FIRST(&rte_pci_bus.device_list); > + > + while (pdev != NULL) { > + if (pdev->id.vendor_id == vendor_id && > + pdev->id.device_id == device_id) > + return true; > + pdev = TAILQ_NEXT(pdev, next); > + } > + return false; > +} Overall this is what I was asking, thanks. A few details on the implementation, What do you think returning the "struct rte_pci_device *", having it NULL meaning device not found? Also you can provide the "struct rte_pci_id" as input, instead of the just vendor and device id? Can be multiple ways to search the device in the bus, what about changing the API name to 'rte_pci_search_device_by_id()' to clarify this search is by id? What about having the API to use the existing 'pci_find_device' function, 'cmp' function becomes simple and I think it makes the logic simpler but that is open to discussion I guess. > + > /* Insert a device into a predefined position in PCI bus */ > void > rte_pci_insert_device(struct rte_pci_device *exist_pci_dev, > diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h > index 29bea6d70..42b6c7e03 100644 > --- a/drivers/bus/pci/rte_bus_pci.h > +++ b/drivers/bus/pci/rte_bus_pci.h > @@ -354,6 +354,18 @@ void rte_pci_ioport_read(struct rte_pci_ioport *p, > void rte_pci_ioport_write(struct rte_pci_ioport *p, > const void *data, size_t len, off_t offset); > > +/* > + * Search for a specific device in pci bus > + * > + * @param vendor_id > + * vendor_id of the device to search > + * @param device_id > + * device_id of the device to search > + * @return > + * 1 on success, 0 on failure > + */ > +int rte_pci_search_device(int vendor_id, int device_id); There are a few process details to follow, - Need to put the API to .map file, so it can be called by other libraries or application. - New APIs need to be experimental at least one release, this is done by: -- put '__rte_experimental' to the API decleration -- put API in .map file into the EXPERIMENTAL section > + > #ifdef __cplusplus > } > #endif > diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h > index 34f60f156..4a3fbac16 100644 > --- a/drivers/net/axgbe/axgbe_common.h > +++ b/drivers/net/axgbe/axgbe_common.h > @@ -841,6 +841,8 @@ > #define PCS_V1_WINDOW_SELECT 0x03fc > #define PCS_V2_WINDOW_DEF 0x9060 > #define PCS_V2_WINDOW_SELECT 0x9064 > +#define PCS_V2_RV_WINDOW_DEF 0x1060 > +#define PCS_V2_RV_WINDOW_SELECT 0x1064 > > /* PCS register entry bit positions and sizes */ > #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6 > diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c > index d1f160e79..01975236b 100644 > --- a/drivers/net/axgbe/axgbe_ethdev.c > +++ b/drivers/net/axgbe/axgbe_ethdev.c > @@ -29,6 +29,7 @@ static int axgbe_dev_info_get(struct rte_eth_dev *dev, > > /* The set of PCI devices this driver supports */ > #define AMD_PCI_VENDOR_ID 0x1022 > +#define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0 > #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 > #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459 > > @@ -605,6 +606,18 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) > pci_dev = RTE_DEV_TO_PCI(eth_dev->device); > pdata->pci_dev = pci_dev; > > + /* > + * Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE > + */ > + if (rte_pci_search_device(AMD_PCI_VENDOR_ID, > + AMD_PCI_RV_ROOT_COMPLEX_ID)) { > + pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; > + pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; > + } else { > + pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; > + pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; > + } > + > pdata->xgmac_regs = > (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; > pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs > @@ -620,14 +633,13 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) > pdata->vdata = &axgbe_v2b; > > /* Configure the PCS indirect addressing support */ > - reg = XPCS32_IOREAD(pdata, PCS_V2_WINDOW_DEF); > + reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); > pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); > pdata->xpcs_window <<= 6; > pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); > pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); > pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; > - pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; > - pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; > + > PMD_INIT_LOG(DEBUG, > "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, > pdata->xpcs_window_size, pdata->xpcs_window_mask); >