From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC8B9C10DCE for ; Fri, 13 Mar 2020 12:57:30 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id 4C0852073E for ; Fri, 13 Mar 2020 12:57:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=intel.onmicrosoft.com header.i=@intel.onmicrosoft.com header.b="E3w88/Sy" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4C0852073E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 664971BF97; Fri, 13 Mar 2020 13:57:29 +0100 (CET) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 902D22BE3 for ; Fri, 13 Mar 2020 13:57:27 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Mar 2020 05:57:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,548,1574150400"; d="scan'208";a="266720414" Received: from orsmsx103.amr.corp.intel.com ([10.22.225.130]) by fmsmga004.fm.intel.com with ESMTP; 13 Mar 2020 05:57:26 -0700 Received: from ORSEDG002.ED.cps.intel.com (10.7.248.5) by ORSMSX103.amr.corp.intel.com (10.22.225.130) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 13 Mar 2020 05:57:25 -0700 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (104.47.70.105) by edgegateway.intel.com (134.134.137.101) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 13 Mar 2020 05:57:25 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=H2grfowvOoNQdwSRwxH2XD0cIkkPihJHBdV3oJuwzY1d8Gi3ew2DvH8dQgY/Sg4HmMelzoxDVOFoSVUzst6bKstzmVUm1o96NAzUt1U2vQjqd2lRkmlgh3mW0qFKsPdr8TqPkr9WH4HBm60e3owhZTUH7E23fQGfzFzFjaJcA10EAbdSSkVS9Wrcl8iqGeNyc87l5LZCpNYxuLor5baovUYY/apc1PFmjCJBCITh2HZnfdeW9CnYL0TPlO21taTYvn/vmC89cmxIsSe4b7dqQCH1PL2pP/YKGgwJAS/r8HVrvkQsnOAy8BJizaFvV3b7PkPL+d4KA5tJRIEqsxkd8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OhX4gC23OfISrnDyDhRIizRAnigpn4d0ualOjze6fYA=; b=iaZ3EMRBcR6Q9PCz404VYBFy0MwcZT1uBeqYSJGqAiyrjMsLzhs5C9D6GLrWVktqVNoDr5eNCHmep/9MQiQL9ZsKEq0ojKjC5VyLZsXf142vM74grt/j9jItwcNanyjXJZwXdgjjhubXupZjatzuJtUyqAyC47AcVtmolahBLRUTBZ5dBMzSZnoTR3FzAZOPLIzre53kN1x1iftNiTUdd+xAhHUGrpn2NA23NXATmmnlg0M74265/GexK0pyh/KRdxVl48UYYOhAOAoaCkJ1CvOztj9cMY2qxm/S2gkWnxfTxnMxEaxT3GstgLoNP9hYngSR00hP+r7qIbjWcc+TNQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OhX4gC23OfISrnDyDhRIizRAnigpn4d0ualOjze6fYA=; b=E3w88/Sysys5H1GZPajqKi8k9CiE7laNEycqFbjY0JGoAdCB9z5X50ICB5lxO+GYm8byxhQaBgkTVTPtUZQA+xVPFPaFHRkakkopyKz6mnGpa+gxmZj/Rtl7J7jm6HKIZhOvo3GTOXF3oydr0Q+bqF1N3qJqzxn6NgmjRHkiaAw= Received: from BN6PR11MB1796.namprd11.prod.outlook.com (2603:10b6:404:103::8) by BN6PR11MB4052.namprd11.prod.outlook.com (2603:10b6:405:7a::37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2814.18; Fri, 13 Mar 2020 12:57:23 +0000 Received: from BN6PR11MB1796.namprd11.prod.outlook.com ([fe80::4519:125f:2122:de07]) by BN6PR11MB1796.namprd11.prod.outlook.com ([fe80::4519:125f:2122:de07%3]) with mapi id 15.20.2793.018; Fri, 13 Mar 2020 12:57:23 +0000 From: "Trahe, Fiona" To: "Dybkowski, AdamX" , "dev@dpdk.org" , "akhil.goyal@nxp.com" CC: "Trahe, Fiona" Thread-Topic: [PATCH 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT Thread-Index: AQHV+Hh5hTtq7TWIwUmZRvngzrdqSqhGe5hw Date: Fri, 13 Mar 2020 12:57:23 +0000 Message-ID: References: <20200312141335.13392-1-adamx.dybkowski@intel.com> <20200312141335.13392-2-adamx.dybkowski@intel.com> In-Reply-To: <20200312141335.13392-2-adamx.dybkowski@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: spf=none (sender IP is ) smtp.mailfrom=fiona.trahe@intel.com; x-originating-ip: [192.198.151.180] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 666f9488-caf6-49c2-60da-08d7c74e1315 x-ms-traffictypediagnostic: BN6PR11MB4052: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3826; x-forefront-prvs: 034119E4F6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(136003)(396003)(376002)(346002)(39860400002)(366004)(199004)(6506007)(53546011)(7696005)(2906002)(81166006)(8676002)(478600001)(110136005)(66556008)(66446008)(66476007)(81156014)(8936002)(64756008)(76116006)(66946007)(316002)(4326008)(71200400001)(186003)(9686003)(55016002)(107886003)(86362001)(52536014)(33656002)(5660300002)(26005)(21314003); DIR:OUT; SFP:1102; SCL:1; SRVR:BN6PR11MB4052; H:BN6PR11MB1796.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: iq/gaOUvfloKvy+zf7D2HiPNAd3gQQzZcMV2oOMLdXRGMhXmxhuYGvgsRzphaHr1Nga3BtOuiid8VSZ7BeHhFIhxm8qz1zvuradSiM6CGcm7AiJ5IfSVz+Sd0fS3TcZPisphKTXH42eAD9QaJSGUvqYCP0XF++ShFxBqjqa9P49MONPdv6MXgnNpdE3F1oUu+hnOqCLZvW0fK1YZIDTYyGJg/SNPplDv6qrbUqT8sGPIKZ79X0Ifm0ZI7iKEta5qT3lVtg5fuxMvZRbWl0mOkDvfGtynTvhOmkAoTHDmkMAr2RFm6cppwYJx/ymCTH3qTbSvyRtvmLhFuo+doQUfBEv4Ea+7ZH0BYDVntwHbx15aGBK4RIy9lv03J3QGJRwjjqw2imnWaHKwM4+GxqnRIIQehtgWApLfiWgbqdboyrGHJTxCSTz3xrvxaA7EGcoVUpKTRaFwSROVkLc3S/DuI5EhXTBHH0SjITat00ekHfM= x-ms-exchange-antispam-messagedata: hRG+ea51RZXphfKrIXa5lYC9HM/RQ/rXXIctqZuPRa723M0Mr8926K2AyPWcpf4b3sw3PKQgOdlAcigMGReM2oL17BJwBpjfkOKQ5NlmUV1I0V47nDC2E8Aflwy7b+vuLz10PSmV8ec5Y1MQw88ujQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 666f9488-caf6-49c2-60da-08d7c74e1315 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Mar 2020 12:57:23.5220 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Yoe4s7InnSShAqgVAyNgwKV2m5sZnRcRyzIIVFPd5dqcNID/+hphhvk/89zeYFQPz/I3FfDlgXQ6GqFYP1JNSg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB4052 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Adam, > -----Original Message----- > From: Dybkowski, AdamX > Sent: Thursday, March 12, 2020 2:14 PM > To: dev@dpdk.org; Trahe, Fiona ; akhil.goyal@nxp.c= om > Cc: Dybkowski, AdamX > Subject: [PATCH 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 = QAT >=20 > This patch adds handling of mixed hash-cipher algorithms > available on GEN2 QAT in particular firmware versions. > Also the documentation is updated to show the mixed crypto > algorithms are supported on QAT GEN2. >=20 > Signed-off-by: Adam Dybkowski > --- > doc/guides/cryptodevs/qat.rst | 9 ++++----- > doc/guides/rel_notes/release_20_05.rst | 7 +++++++ > drivers/crypto/qat/qat_sym_pmd.c | 23 +++++++++++++++++++++++ > drivers/crypto/qat/qat_sym_pmd.h | 5 +++++ > drivers/crypto/qat/qat_sym_session.c | 17 +++++++++++------ > 5 files changed, 50 insertions(+), 11 deletions(-) >=20 > diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rs= t > index 06985e319..2e0dc1b00 100644 > --- a/doc/guides/cryptodevs/qat.rst > +++ b/doc/guides/cryptodevs/qat.rst > @@ -82,18 +82,17 @@ All the usual chains are supported and also some mixe= d chains: > +------------------+-----------+-------------+----------+----------+ > | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC | > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ > - | NULL CIPHER | Y | 3 | 3 | Y | > + | NULL CIPHER | Y | 2&3 | 2&3 | Y | > +------------------+-----------+-------------+----------+----------+ > - | SNOW3G UEA2 | 3 | Y | 3 | 3 | > + | SNOW3G UEA2 | 2&3 | Y | 2&3 | 2&3 | > +------------------+-----------+-------------+----------+----------+ > - | ZUC EEA3 | 3 | 3 | 2&3 | 3 | > + | ZUC EEA3 | 2&3 | 2&3 | 2&3 | 2&3 | > +------------------+-----------+-------------+----------+----------+ > - | AES CTR | Y | 3 | 3 | Y | > + | AES CTR | Y | 2&3 | 2&3 | Y | > +------------------+-----------+-------------+----------+----------+ >=20 > * The combinations marked as "Y" are supported on all QAT hardware versi= ons. > * The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardwa= re only. > -* The combinations marked as "3" are supported on GEN3 QAT hardware only= . >=20 >=20 > Limitations > diff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_note= s/release_20_05.rst > index 2190eaf85..bdfa64973 100644 > --- a/doc/guides/rel_notes/release_20_05.rst > +++ b/doc/guides/rel_notes/release_20_05.rst > @@ -56,6 +56,13 @@ New Features > Also, make sure to start the actual text at the margin. > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >=20 > +* **Added handling of mixed crypto algorithms in QAT PMD for GEN2.** > + > + Enabled handling of mixed algorithms in encrypted digest hash-cipher > + (generation) and cipher-hash (verification) requests in QAT PMD > + when running on GEN2 QAT hardware with particular firmware versions > + (GEN3 support was added in DPDK 20.02). > + >=20 > Removed Items > ------------- > diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sy= m_pmd.c > index 666ede726..69b11ec78 100644 > --- a/drivers/crypto/qat/qat_sym_pmd.c > +++ b/drivers/crypto/qat/qat_sym_pmd.c > @@ -14,6 +14,8 @@ > #include "qat_sym_session.h" > #include "qat_sym_pmd.h" >=20 > +#define MIXED_CRYPTO_MIN_FW_VER 0x04090000 > + > uint8_t cryptodev_qat_driver_id; >=20 > static const struct rte_cryptodev_capabilities qat_gen1_sym_capabilities= [] =3D { > @@ -187,6 +189,27 @@ static int qat_sym_qp_setup(struct rte_cryptodev *de= v, uint16_t qp_id, > qat_sgl_dst); > } >=20 > + /* Get fw version from QAT (GEN2), skip if we've got it already */ > + if (qp->qat_dev_gen =3D=3D QAT_GEN2 && !(qat_private->internal_capabili= ties > + & QAT_SYM_CAP_VALID)) { > + ret =3D qat_cq_get_fw_version(qp); > + > + if (ret < 0) > + return ret; [Fiona] if this fails, then need to clean up the ring before returning > + > + if (ret !=3D 0) > + QAT_LOG(DEBUG, "QAT firmware version: %d.%d.%d", > + (ret >> 24) & 0xff, > + (ret >> 16) & 0xff, > + (ret >> 8) & 0xff); [Fiona] add debug log with "unknown firmware version" in else case > + > + /* set capabilities based on the fw version */ > + qat_private->internal_capabilities =3D QAT_SYM_CAP_VALID | > + ((ret >=3D MIXED_CRYPTO_MIN_FW_VER) ? > + QAT_SYM_CAP_MIXED_CRYPTO : 0); > + ret =3D 0; > + } > + > return ret; > } >=20 > diff --git a/drivers/crypto/qat/qat_sym_pmd.h b/drivers/crypto/qat/qat_sy= m_pmd.h > index a32c25abc..a5a31e512 100644 > --- a/drivers/crypto/qat/qat_sym_pmd.h > +++ b/drivers/crypto/qat/qat_sym_pmd.h > @@ -15,6 +15,10 @@ > /** Intel(R) QAT Symmetric Crypto PMD driver name */ > #define CRYPTODEV_NAME_QAT_SYM_PMD crypto_qat >=20 > +/* Internal capabilities */ > +#define QAT_SYM_CAP_MIXED_CRYPTO (1 << 0) > +#define QAT_SYM_CAP_VALID (1 << 31) > + > extern uint8_t cryptodev_qat_driver_id; >=20 > /** private data structure for a QAT device. > @@ -29,6 +33,7 @@ struct qat_sym_dev_private { > const struct rte_cryptodev_capabilities *qat_dev_capabilities; > /* QAT device symmetric crypto capabilities */ > uint16_t min_enq_burst_threshold; > + uint32_t internal_capabilities; /* see flags QAT_SYM_CAP_xxx */ > }; >=20 > int > diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qa= t_sym_session.c > index 4359f2f0b..bf6af60aa 100644 > --- a/drivers/crypto/qat/qat_sym_session.c > +++ b/drivers/crypto/qat/qat_sym_session.c > @@ -459,18 +459,23 @@ qat_sym_session_set_ext_hash_flags(struct qat_sym_s= ession *session, > } >=20 > static void > -qat_sym_session_handle_mixed(struct qat_sym_session *session) > +qat_sym_session_handle_mixed(const struct rte_cryptodev *dev, > + struct qat_sym_session *session) > { > + const struct qat_sym_dev_private *qat_private =3D dev->data->dev_privat= e; > + enum qat_device_gen min_dev_gen =3D (qat_private->internal_capabilities= & > + QAT_SYM_CAP_MIXED_CRYPTO) ? QAT_GEN2 : QAT_GEN3; > + > if (session->qat_hash_alg =3D=3D ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &= & > session->qat_cipher_alg !=3D > ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) { > - session->min_qat_dev_gen =3D QAT_GEN3; > + session->min_qat_dev_gen =3D min_dev_gen; > qat_sym_session_set_ext_hash_flags(session, > 1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS); > } else if (session->qat_hash_alg =3D=3D ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UI= A2 && > session->qat_cipher_alg !=3D > ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) { > - session->min_qat_dev_gen =3D QAT_GEN3; > + session->min_qat_dev_gen =3D min_dev_gen; > qat_sym_session_set_ext_hash_flags(session, > 1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS); > } else if ((session->aes_cmac || > @@ -479,7 +484,7 @@ qat_sym_session_handle_mixed(struct qat_sym_session *= session) > ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 || > session->qat_cipher_alg =3D=3D > ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) { > - session->min_qat_dev_gen =3D QAT_GEN3; > + session->min_qat_dev_gen =3D min_dev_gen; > qat_sym_session_set_ext_hash_flags(session, 0); > } > } > @@ -532,7 +537,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *= dev, > if (ret < 0) > return ret; > /* Special handling of mixed hash+cipher algorithms */ > - qat_sym_session_handle_mixed(session); > + qat_sym_session_handle_mixed(dev, session); > } > break; > case ICP_QAT_FW_LA_CMD_HASH_CIPHER: > @@ -551,7 +556,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *= dev, > if (ret < 0) > return ret; > /* Special handling of mixed hash+cipher algorithms */ > - qat_sym_session_handle_mixed(session); > + qat_sym_session_handle_mixed(dev, session); > } > break; > case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM: > -- > 2.17.1