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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 1kF/sdMBQQsJzENl9gIP6qSCvHjtLLxvQ2bfNyGi78X1/4oEahvgq8gSPTdWBgn/q3hrKy1ObcnGnAUpFFO4aHJ0ph3I20MwE/Po4rOhakwd2a1f8VveO/Nu1AjdDxyWMztqGDxdELqufyMQLK3xBj+fBMwKyLWyJaD0Pn595lRIDj9kQV4+aYDNuVxY9UrW23+Se+xcpnEWm3BJqy/qLcy2nJc6tOQ0ygAxzsDUsBONRgDipfgTZEE0O590zVPEX7r9NLIe5jgtnpO64EPSeQjnDs0cQ6qdkUdi5c3mTfMSbhMynCFnFTTML9M4yXp121LXuGcNeSxLRwCYpFAWgw9MeAUsKoDcT/+fIe7D/eYPtpBtztGOo9I1glg72yxI6/lraXOHBrgSpanZXfhMEltTMYIgTMujG8iKyujWHl8= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 5f4aeec2-abf1-4d31-e378-08d70aa3a30f X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jul 2019 10:43:42.6789 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB3048 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-07-17_03:2019-07-17,2019-07-17 signatures=0 Subject: Re: [dpdk-dev] [RFC PATCH v3 2/3] eal: add mask and unmask interrupt APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > I think, it vary from the perspective of IRQ Chip(or controller) vs > > NIC > > register(Source) PoV. > > Since the API starts from rte_intr_* it is more of controller so _ack_ > > make sense Other reason for ack: > > 1) It will enforce that it needs to be called form ISR > > 2) It would be have been really correct to unmask if VFIO+MSIx+Linux > > supports it > > 3) if it is ack, no need to add unmask counterpart, the _mask_ API > > >=20 > Just curious, what you mean by irq controller? Ack/mask/unmask PIOs all g= o Programmable Interrupt Controller. Like Intel 8259A, GIC from ARM etc The drivers in linux/drivers/irqchip/ > to the NIC. It is the NIC that asserts/de-asserts irq.. >=20 > > > > > > Besides the name, are we agreeing that we want these? > > > - Unmask if INTx > > > > Yes > > > > > - Nothing if MSI/MSI-X > > Yes for MSI over VFIO > > No for MSI over UIO/igb_uio > > >=20 > I guess I was not clear. For MSI/MSI-X, we do not want to do mask/unmask > regardless of vfio-pci/igb_uio. Below is my comment about > linux/windows/freebsd from an earlier email. Do you disagree? I am sure > there are plenty of kernel NIC driver guys here. Please correct me if I a= m > mistaken... For some reason, igb_uio kernel driver mask the interrupt for MSIx. We need to ack or unmask if needs to work with MSIX + IGB_UIO. See=20 pci_uio_alloc_resource() if (dev->kdrv =3D=3D RTE_KDRV_IGB_UIO) dev->intr_handle.type =3D RTE_INTR_HANDLE_UIO;=20 else { dev->intr_handle.type =3D RTE_INTR_HANDLE_UIO_INTX; igbuio_pci_irqcontrol() for masking in kernel. So it is more of making inline with igb_uio kernel driver AND not break The existing drivers which was using rte_intr_enable in ISR with MSIX+IGB_U= IO I do agree with that for edge trigged interrupt mask may not require from k= ernel. But I am not sure why it is added in igb_uio kernel driver. May be it is j= ust legacy. Anyway this wont change schematics, when igb_uio kenrel fixed then the coun= ter Part can be changed in rte_intr_ack(). Ie. it is transparent to drivers. >=20 > > I don't have very strong opinion unmask vs ack. I prefer to have ack > > due the reasons stated above. > > If you really have strong opinion on using unmask, we will stick with > > that to make forward progress. > > Let us know. > > >=20 > I have no strong opinion either. OK. Lets stick with rte_intr_ack(). >=20 > Thanks.. > -Hyong