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DIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR1801MB1942; H:CY4PR1801MB1863.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: /AyAsFTG1jWK0Tv+/zU2UW2wZo+wBNQ/316PIKT7nvMI1guHKtZH3vDu5cIQqPhxxSzUYqScPQ98nSwfGWIypirC+18YzesZr41eKVSNQFDs/XLb3ah7zpFvVW2lATLbC00RkTdXGMcG7K2uUBk/sWCg1f5m+5knH33s6a0IEU3X7LB28zogCjbi8E9NL6C7+xQB3Fp/N6F/ULjnKS1hG4jeCKIbGnk5XNvjQVxKQB9gmkizW3+LNeNpHuKOXmPtLkbs/z3SOS98hG+zUB7eAYPxb3Ycnuft9mvwpQl1C5rLzsGao5roA7l9xWtOFuVEIoHirA5oHSJ70sWcprJNn2o9PGlaUTrFB+YQ5ZTiUzuJ0iBz1xKO4I5nBEdvpQi3PsII5zJqMH4cUViKkks17SmcU/TShw/itiURDWs4IJk= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 692e2faf-9fa6-4b15-a99a-08d701026f36 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Jul 2019 04:37:06.2111 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pbhagavatula@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1801MB1942 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-07-05_01:, , signatures=0 Subject: Re: [dpdk-dev] [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >-----Original Message----- >From: dev On Behalf Of Honnappa >Nagarahalli >Sent: Friday, July 5, 2019 9:51 AM >To: Jerin Jacob Kollanukkaran ; Phil Yang (Arm >Technology China) ; dev@dpdk.org >Cc: thomas@monjalon.net; hemant.agrawal@nxp.com; Gavin Hu (Arm >Technology China) ; Honnappa Nagarahalli >; nd ; >gage.eads@intel.com; nd >Subject: Re: [dpdk-dev] [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit >atomic compare exchange > > > >> > > Subject: [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic >compare >> > > exchange >> > > >> > > Add 128-bit atomic compare exchange on aarch64. >> > > >> > > Signed-off-by: Phil Yang >> > > Tested-by: Honnappa Nagarahalli > >> > > Reviewed-by: Honnappa Nagarahalli > >> > > --- >> > > v3: >> > > 1. Avoid duplication code with macro. (Jerin Jocob) 2. Make invalid >> > > memory order to strongest barrier. (Jerin Jocob) 3. Update >> > > doc/guides/prog_guide/env_abstraction_layer.rst. (Eads Gage) 4. >Fix >> > > 32-bit x86 builds issue. (Eads Gage) 5. Correct documentation >issues >> > > in UT. (Eads Gage) >> > > >> > > .../common/include/arch/arm/rte_atomic_64.h | 165 >> > > +++++++++++++++++++++ >> > > .../common/include/arch/x86/rte_atomic_64.h | 12 -- >> > > lib/librte_eal/common/include/generic/rte_atomic.h | 17 ++- >> > > 3 files changed, 181 insertions(+), 13 deletions(-) >> > > >> > > diff --git >a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h >> > > b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h >> > > index 97060e4..2080c4d 100644 >> > > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h >> > > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h >> > > @@ -1,5 +1,6 @@ >> > > /* SPDX-License-Identifier: BSD-3-Clause >> > > * Copyright(c) 2015 Cavium, Inc >> > > + * Copyright(c) 2019 Arm Limited >> > > */ >> > > >> > > #ifndef _RTE_ATOMIC_ARM64_H_ >> > > @@ -14,6 +15,9 @@ extern "C" { >> > > #endif >> > > >> > > #include "generic/rte_atomic.h" >> > > +#include >> > > +#include >> > > +#include >> > > >> > > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define >> > > dmb(opt) asm volatile("dmb " #opt : : : "memory") @@ -40,6 >+44,167 >> > > @@ extern "C" { >> > > >> > > #define rte_cio_rmb() dmb(oshld) >> > > >> > > +/*------------------------ 128 bit atomic operations >> > > +-------------------------*/ >> > > + >> > > +#define RTE_HAS_ACQ(mo) ((mo) !=3D __ATOMIC_RELAXED && >(mo) !=3D >> > > +__ATOMIC_RELEASE) #define RTE_HAS_RLS(mo) ((mo) =3D=3D >> > __ATOMIC_RELEASE >> > > || \ >> > > + (mo) =3D=3D __ATOMIC_ACQ_REL || \ >> > > + (mo) =3D=3D __ATOMIC_SEQ_CST) >> > > + >> > > +#define RTE_MO_LOAD(mo) (RTE_HAS_ACQ((mo)) \ >> > > + ? __ATOMIC_ACQUIRE : __ATOMIC_RELAXED) #define >> > > RTE_MO_STORE(mo) >> > > +(RTE_HAS_RLS((mo)) \ >> > > + ? __ATOMIC_RELEASE : __ATOMIC_RELAXED) >> > > + >> > > +#ifdef __ARM_FEATURE_ATOMICS >> > > +#define __ATOMIC128_CAS_OP(cas_op_name, op_string) >> \ >> > > +static inline rte_int128_t = \ >> > > +cas_op_name(rte_int128_t *dst, rte_int128_t old, = \ >> > > + rte_int128_t updated) = \ >> > > +{ = \ >> > > + /* caspX instructions register pair must start from even- >numbered >> > > + * register at operand 1. >> > > + * So, specify registers for local variables here. >> > > + */ = \ >> > > + register uint64_t x0 __asm("x0") =3D (uint64_t)old.val[0]; = \ >> > >> > I understand CASP limitation on register has to be even and odd. >> > Is there anyway to remove explicit x0 register allocation and choose >> > compiler to decide the register. Some reason with optimize(03) gcc >> > makes correctly but not clang. >> > >> > Hardcoding to specific register makes compiler to not optimize the >> > stuff, especially if it is inline function. >> >> It look like the limitation fixed recently in gcc. >> https://patches.linaro.org/patch/147991/ >> >> Not sure about old gcc and clang. ARM compiler experts may know >the exact >> status >> >We could use syntax as follows, an example is in [1] >static inline rte_int128_t >__rte_casp(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated, >int mo) >{ > __asm__ volatile("caspl %0, %H0, %1, %H1, [%2]" > : "+r" (old) > : "r" (updated), "r" (dst) > : "memory"); > return old; >} We have used this format for mempool/octeontx2 but clang wasn't too happy. dpdk/drivers/mempool/octeontx2/otx2_mempool_ops.c:151:15: error: value size= does not match register size specified by the constraint and modifier [-We= rror,-Wasm-operand-widths] [t0] "=3D&r" (t0), [t1] "=3D&r" (t1), [t2] "=3D&r" (t2), ^ dpdk/drivers/mempool/octeontx2/otx2_mempool_ops.c:82:9: note: use constrain= t modifier "w" "casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\n" Had to change it to hand coded asm http://patches.dpdk.org/patch/56110/ > >[1] https://godbolt.org/z/EUJnuG