From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03DCEC4321A for ; Tue, 11 Jun 2019 16:31:00 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id 976E52089E for ; Tue, 11 Jun 2019 16:30:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 976E52089E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E0FB41D08C; Tue, 11 Jun 2019 18:30:58 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 089D91C580 for ; Tue, 11 Jun 2019 18:30:57 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Jun 2019 09:30:56 -0700 X-ExtLoop1: 1 Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga006.fm.intel.com with ESMTP; 11 Jun 2019 09:30:55 -0700 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 11 Jun 2019 09:30:55 -0700 Received: from fmsmsx120.amr.corp.intel.com ([169.254.15.191]) by fmsmsx124.amr.corp.intel.com ([169.254.8.120]) with mapi id 14.03.0415.000; Tue, 11 Jun 2019 09:30:55 -0700 From: "Stillwell Jr, Paul M" To: "Rong, Leyi" , "Zhang, Qi Z" CC: "dev@dpdk.org" Thread-Topic: [PATCH v2 30/66] net/ice/base: add some minor features Thread-Index: AQHVIG3uUAIZctCwpUKJfx/2gNdOkqaWpQNQ Date: Tue, 11 Jun 2019 16:30:55 +0000 Message-ID: References: <20190604054248.68510-1-leyi.rong@intel.com> <20190611155221.2703-1-leyi.rong@intel.com> <20190611155221.2703-31-leyi.rong@intel.com> In-Reply-To: <20190611155221.2703-31-leyi.rong@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYmVlMGM3NjItYTFkYi00ODA0LTg0YzEtM2JmNWU5NzkyMDVlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoib3BnN3VNQ09Nb2xIb09zZlV1YUw0NmQzZDBwaGNFQlpzTHBnRmdFRFdrUVYyYWsyaVRDQ1J6eVwvc0J4WDNOQ0kifQ== x-originating-ip: [10.1.200.108] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 30/66] net/ice/base: add some minor features X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Rong, Leyi > Sent: Tuesday, June 11, 2019 8:52 AM > To: Zhang, Qi Z > Cc: dev@dpdk.org; Rong, Leyi ; Stillwell Jr, Paul M > > Subject: [PATCH v2 30/66] net/ice/base: add some minor features >=20 > 1. Disable TX pacing option. > 2. Use a different ICE_DBG bit for firmware log messages. > 3. Always set prefena when configuring a RX queue. > 4. make FDID available for FlexDescriptor. >=20 I think this should be split into separate patches. > Signed-off-by: Paul M Stillwell Jr > Signed-off-by: Leyi Rong > --- > drivers/net/ice/base/ice_common.c | 44 +++++++++++++--------------- > drivers/net/ice/base/ice_fdir.c | 2 +- > drivers/net/ice/base/ice_lan_tx_rx.h | 3 +- > drivers/net/ice/base/ice_type.h | 2 +- > 4 files changed, 25 insertions(+), 26 deletions(-) >=20 > diff --git a/drivers/net/ice/base/ice_common.c > b/drivers/net/ice/base/ice_common.c > index 6e5a60a38..89c922bed 100644 > --- a/drivers/net/ice/base/ice_common.c > +++ b/drivers/net/ice/base/ice_common.c > @@ -449,11 +449,7 @@ ice_aq_set_mac_cfg(struct ice_hw *hw, u16 > max_frame_size, struct ice_sq_cd *cd) { > u16 fc_threshold_val, tx_timer_val; > struct ice_aqc_set_mac_cfg *cmd; > - struct ice_port_info *pi; > struct ice_aq_desc desc; > - enum ice_status status; > - u8 port_num =3D 0; > - bool link_up; > u32 reg_val; >=20 > cmd =3D &desc.params.set_mac_cfg; > @@ -465,21 +461,6 @@ ice_aq_set_mac_cfg(struct ice_hw *hw, u16 > max_frame_size, struct ice_sq_cd *cd) >=20 > cmd->max_frame_size =3D CPU_TO_LE16(max_frame_size); >=20 > - /* Retrieve the current data_pacing value in FW*/ > - pi =3D &hw->port_info[port_num]; > - > - /* We turn on the get_link_info so that ice_update_link_info(...) > - * can be called. > - */ > - pi->phy.get_link_info =3D 1; > - > - status =3D ice_get_link_status(pi, &link_up); > - > - if (status) > - return status; > - > - cmd->params =3D pi->phy.link_info.pacing; > - > /* We read back the transmit timer and fc threshold value of > * LFC. Thus, we will use index =3D > * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. > @@ -544,7 +525,15 @@ static void ice_cleanup_fltr_mgmt_struct(struct > ice_hw *hw) > } > recps =3D hw->switch_info->recp_list; > for (i =3D 0; i < ICE_MAX_NUM_RECIPES; i++) { > + struct ice_recp_grp_entry *rg_entry, *tmprg_entry; > + > recps[i].root_rid =3D i; > + LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry, > + &recps[i].rg_list, > ice_recp_grp_entry, > + l_entry) { > + LIST_DEL(&rg_entry->l_entry); > + ice_free(hw, rg_entry); > + } >=20 > if (recps[i].adv_rule) { > struct ice_adv_fltr_mgmt_list_entry *tmp_entry; > @@ -571,6 +560,8 @@ static void ice_cleanup_fltr_mgmt_struct(struct > ice_hw *hw) > ice_free(hw, lst_itr); > } > } > + if (recps[i].root_buf) > + ice_free(hw, recps[i].root_buf); > } > ice_rm_all_sw_replay_rule_info(hw); > ice_free(hw, sw->recp_list); > @@ -789,10 +780,10 @@ static enum ice_status ice_cfg_fw_log(struct > ice_hw *hw, bool enable) > */ > void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void > *buf) { > - ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg Start ]\n"); > - ice_debug_array(hw, ICE_DBG_AQ_MSG, 16, 1, (u8 *)buf, > + ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); > + ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, > LE16_TO_CPU(desc->datalen)); > - ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg End ]\n"); > + ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); > } >=20 > /** > @@ -1213,6 +1204,7 @@ static const struct ice_ctx_ele ice_rlan_ctx_info[]= =3D > { > ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), > ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), > ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), > + ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), > { 0 } > }; >=20 > @@ -1223,7 +1215,8 @@ static const struct ice_ctx_ele ice_rlan_ctx_info[]= =3D > { > * @rxq_index: the index of the Rx queue > * > * Converts rxq context from sparse to dense structure and then writes > - * it to HW register space > + * it to HW register space and enables the hardware to prefetch > + descriptors > + * instead of only fetching them on demand > */ > enum ice_status > ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, @@ - > 1231,6 +1224,11 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct > ice_rlan_ctx *rlan_ctx, { > u8 ctx_buf[ICE_RXQ_CTX_SZ] =3D { 0 }; >=20 > + if (!rlan_ctx) > + return ICE_ERR_BAD_PTR; > + > + rlan_ctx->prefena =3D 1; > + > ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); > return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); } diff --git > a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index > 4bc8e6dcb..bde676a8f 100644 > --- a/drivers/net/ice/base/ice_fdir.c > +++ b/drivers/net/ice/base/ice_fdir.c > @@ -186,7 +186,7 @@ ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx > *fd_fltr_ctx) > fd_fltr_ctx->desc_prof_prio =3D > ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO; > fd_fltr_ctx->desc_prof =3D ICE_FXD_FLTR_QW1_PROF_ZERO; > fd_fltr_ctx->swap =3D ICE_FXD_FLTR_QW1_SWAP_SET; > - fd_fltr_ctx->fdid_prio =3D ICE_FXD_FLTR_QW1_FDID_PRI_ZERO; > + fd_fltr_ctx->fdid_prio =3D ICE_FXD_FLTR_QW1_FDID_PRI_ONE; > fd_fltr_ctx->fdid_mdid =3D ICE_FXD_FLTR_QW1_FDID_MDID_FD; > fd_fltr_ctx->fdid =3D ICE_FXD_FLTR_QW1_FDID_ZERO; } diff --git > a/drivers/net/ice/base/ice_lan_tx_rx.h > b/drivers/net/ice/base/ice_lan_tx_rx.h > index 8c9902994..fa2309bf1 100644 > --- a/drivers/net/ice/base/ice_lan_tx_rx.h > +++ b/drivers/net/ice/base/ice_lan_tx_rx.h > @@ -162,7 +162,7 @@ struct ice_fltr_desc { >=20 > #define ICE_FXD_FLTR_QW1_FDID_PRI_S 25 > #define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << > ICE_FXD_FLTR_QW1_FDID_PRI_S) > -#define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO 0x0ULL > +#define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL >=20 > #define ICE_FXD_FLTR_QW1_FDID_MDID_S 28 > #define ICE_FXD_FLTR_QW1_FDID_MDID_M (0xFULL << > ICE_FXD_FLTR_QW1_FDID_MDID_S) > @@ -807,6 +807,7 @@ struct ice_rlan_ctx { > u8 tphdata_ena; > u8 tphhead_ena; > u16 lrxqthresh; /* bigger than needed, see above for reason */ > + u8 prefena; /* NOTE: normally must be set to 1 at init */ > }; >=20 > struct ice_ctx_ele { > diff --git a/drivers/net/ice/base/ice_type.h > b/drivers/net/ice/base/ice_type.h index 477f34595..116cfe647 100644 > --- a/drivers/net/ice/base/ice_type.h > +++ b/drivers/net/ice/base/ice_type.h > @@ -82,7 +82,7 @@ static inline u32 ice_round_to_num(u32 N, u32 R) > /* debug masks - set these bits in hw->debug_mask to control output */ > #define ICE_DBG_INIT BIT_ULL(1) > #define ICE_DBG_RELEASE BIT_ULL(2) > - > +#define ICE_DBG_FW_LOG BIT_ULL(3) > #define ICE_DBG_LINK BIT_ULL(4) > #define ICE_DBG_PHY BIT_ULL(5) > #define ICE_DBG_QCTX BIT_ULL(6) > -- > 2.17.1