From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8256CC43613 for ; Mon, 24 Jun 2019 16:12:51 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id 14B5120652 for ; Mon, 24 Jun 2019 16:12:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.b="ACkowDg7" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 14B5120652 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EE4821B974; Mon, 24 Jun 2019 18:12:49 +0200 (CEST) Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-eopbgr130059.outbound.protection.outlook.com [40.107.13.59]) by dpdk.org (Postfix) with ESMTP id 9E0051B964 for ; Mon, 24 Jun 2019 18:12:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=C6O3bFzHS+a7d3RLF4chXscy258i/7ZFy9jUOtvmZsE=; b=ACkowDg7CelwKsEv+KSDX/whXpFTKEKu/ZB+iFJQPA90pC/OMSt0X/Fs05w0g8xTUitdaPj4o5eHnt1qFSvbeJcaDljfLqUYobtq9E3MQeAaV/GEOn8jyWukc2Xcm3YO2hlfW9DZWvMrH5R8gR0HWmcbUE67gkdMwTfDYYqKBF8= Received: from VE1PR08MB5149.eurprd08.prod.outlook.com (20.179.30.152) by VE1PR08MB4944.eurprd08.prod.outlook.com (10.255.158.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2008.16; Mon, 24 Jun 2019 16:12:47 +0000 Received: from VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::a89e:33:fbda:ed35]) by VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::a89e:33:fbda:ed35%4]) with mapi id 15.20.2008.014; Mon, 24 Jun 2019 16:12:47 +0000 From: Honnappa Nagarahalli To: "Phil Yang (Arm Technology China)" , "jerinj@marvell.com" , "dev@dpdk.org" CC: "thomas@monjalon.net" , "hemant.agrawal@nxp.com" , "Gavin Hu (Arm Technology China)" , Honnappa Nagarahalli , nd , "gage.eads@intel.com" , nd Thread-Topic: [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare exchange Thread-Index: AdUqVpABcLyZ0lTxQfaR61ir9fMMZQAS9vkAAAEUrzA= Date: Mon, 24 Jun 2019 16:12:47 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: 12139ed9-ae3d-48fc-88cb-55f82483b9d5.0 x-checkrecipientchecked: true authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; x-originating-ip: [217.140.111.135] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d730ca43-8f10-425c-bc29-08d6f8becc3d x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020); SRVR:VE1PR08MB4944; x-ms-traffictypediagnostic: VE1PR08MB4944: x-ms-exchange-purlcount: 1 x-ld-processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr nodisclaimer: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1728; x-forefront-prvs: 007814487B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(136003)(396003)(346002)(366004)(376002)(199004)(189003)(14454004)(14444005)(256004)(72206003)(6246003)(33656002)(229853002)(52536014)(7736002)(6436002)(4326008)(110136005)(7696005)(53936002)(74316002)(6306002)(81166006)(81156014)(2501003)(66446008)(64756008)(66556008)(66476007)(8676002)(54906003)(26005)(316002)(5660300002)(76116006)(8936002)(99286004)(66946007)(73956011)(76176011)(6506007)(186003)(486006)(478600001)(66066001)(966005)(2906002)(476003)(11346002)(9686003)(446003)(305945005)(55016002)(102836004)(3846002)(71190400001)(71200400001)(6116002)(2201001)(86362001)(68736007)(25786009); DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB4944; H:VE1PR08MB5149.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: oZf+vDBNf2jHSBmcb0Jz8FDbuA1251w3B/HN5I/bGbn0LDYM5Dd/ebP9+MC6wN+2TqhYHoprUNhuQ1626G47ZL2yLGB6Ovb+koohln0TRUXRFuojo7wlKBoXLVjrpTXSVnp9XN5JA+o1YrC3qr9YHddxzgLT4kKxHs18UmRbhS5SuFtGOJN5SC5va80USqn2qbf1EgBoi32NAxukI0wCdxJAp8dwnBKlPEgJtvW2D7oTBEiOg8YNcQg8xuSIETdR4dn70jfBkyp/TN+Y1s5DqbecgsByGbuuqGNzXKyu3MuwscyZeQAgEzwHBh9EWVlGKIwZzcGAJt+ZGUrYZYY6f7bQzVfk1HuBr1CQu3XB3Qplz/EL0EI3/yI/qQYb49rj/OYmuWoDyhpdJGLCYy0zBITEr/sLmhU+QSpwH9agX9w= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: d730ca43-8f10-425c-bc29-08d6f8becc3d X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Jun 2019 16:12:47.2307 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Honnappa.Nagarahalli@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4944 Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > > > > > Add 128-bit atomic compare exchange on aarch64. > > > > > > Signed-off-by: Phil Yang > > > Reviewed-by: Honnappa Nagarahalli > > > Tested-by: Honnappa Nagarahalli > > > --- > > > This patch depends on 'eal/stack: fix 'pointer-sign' warning' > > > http://patchwork.dpdk.org/patch/54840/ > > > > > > + > > > +#ifdef __ARM_FEATURE_ATOMICS > > > +static inline rte_int128_t > > > +__rte_casp(rte_int128_t *dst, rte_int128_t old, rte_int128_t > > > +updated, int mo) { > > > > Better to change to "const int mo". > > > > > + > > > + /* caspX instructions register pair must start from even-numbered > > > + * register at operand 1. > > > + * So, specify registers for local variables here. > > > + */ > > > + register uint64_t x0 __asm("x0") =3D (uint64_t)old.val[0]; > > > + register uint64_t x1 __asm("x1") =3D (uint64_t)old.val[1]; > > > + register uint64_t x2 __asm("x2") =3D (uint64_t)updated.val[0]; > > > + register uint64_t x3 __asm("x3") =3D (uint64_t)updated.val[1]; > > > + > > > + if (mo =3D=3D __ATOMIC_RELAXED) { > > > + asm volatile( > > > + "casp %[old0], %[old1], %[upd0], %[upd1], > > > [%[dst]]" > > > + : [old0] "+r" (x0), > > > + [old1] "+r" (x1) > > > + : [upd0] "r" (x2), > > > + [upd1] "r" (x3), > > > + [dst] "r" (dst) > > > + : "memory"); > > > + } else if (mo =3D=3D __ATOMIC_ACQUIRE) { > > > + asm volatile( > > > + "caspa %[old0], %[old1], %[upd0], %[upd1], > > > [%[dst]]" > > > + : [old0] "+r" (x0), > > > + [old1] "+r" (x1) > > > + : [upd0] "r" (x2), > > > + [upd1] "r" (x3), > > > + [dst] "r" (dst) > > > + : "memory"); > > > + } else if (mo =3D=3D __ATOMIC_ACQ_REL) { > > > + asm volatile( > > > + "caspal %[old0], %[old1], %[upd0], %[upd1], > > > [%[dst]]" > > > + : [old0] "+r" (x0), > > > + [old1] "+r" (x1) > > > + : [upd0] "r" (x2), > > > + [upd1] "r" (x3), > > > + [dst] "r" (dst) > > > + : "memory"); > > > + } else if (mo =3D=3D __ATOMIC_RELEASE) { > > > + asm volatile( > > > + "caspl %[old0], %[old1], %[upd0], %[upd1], > > > [%[dst]]" > > > + : [old0] "+r" (x0), > > > + [old1] "+r" (x1) > > > + : [upd0] "r" (x2), > > > + [upd1] "r" (x3), > > > + [dst] "r" (dst) > > > + : "memory"); > > > > I think, This duplication code can be avoid with macro and > > casp/capsa/casal/caspl as argument. > > > > > + } else { > > > + rte_panic("Invalid memory order\n"); > > > > > > rte_panic should be removed from library. In this case, I think, > > invalid mo can go for strongest barrier. It is added here to capture programming errors. Memory order can be passed = during compilation or during run time. 'rte_panic' supports both of these. Adding code with strongest memory order will mask the programming error. > > > > > + } > > > + > > > + old.val[0] =3D x0; > > > + old.val[1] =3D x1; > > > + > > > + return old; > > > +} > > > +#else