From mboxrd@z Thu Jan 1 00:00:00 1970 From: Honnappa Nagarahalli Subject: Re: [PATCH v2 3/3] test/ring_perf: replace sync builtins with atomic builtins Date: Mon, 1 Apr 2019 16:24:24 +0000 Message-ID: References: <1546508946-12552-1-git-send-email-phil.yang@arm.com> <1553856998-25394-4-git-send-email-phil.yang@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Cc: "david.hunt@intel.com" , "reshma.pattan@intel.com" , "Gavin Hu (Arm Technology China)" , "Phil Yang (Arm Technology China)" , nd , Honnappa Nagarahalli , "olivier.matz@6wind.com" , nd To: "Phil Yang (Arm Technology China)" , "dev@dpdk.org" , "thomas@monjalon.net" Return-path: Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-eopbgr130085.outbound.protection.outlook.com [40.107.13.85]) by dpdk.org (Postfix) with ESMTP id 408605323 for ; Mon, 1 Apr 2019 18:24:26 +0200 (CEST) In-Reply-To: <1553856998-25394-4-git-send-email-phil.yang@arm.com> Content-Language: en-US List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c index > ebb3939..e851c1a 100644 > --- a/app/test/test_ring_perf.c > +++ b/app/test/test_ring_perf.c > @@ -160,7 +160,11 @@ enqueue_bulk(void *p) > unsigned i; > void *burst[MAX_BURST] =3D {0}; >=20 > - if ( __sync_add_and_fetch(&lcore_count, 1) !=3D 2 ) > +#ifdef RTE_USE_C11_MEM_MODEL > + if (__atomic_add_fetch(&lcore_count, 1, __ATOMIC_RELAXED) !=3D 2) > #else > + if (__sync_add_and_fetch(&lcore_count, 1) !=3D 2) #endif > while(lcore_count !=3D 2) > rte_pause(); Since, rte_ring library has both C11 and non-C11 implementations, condition= al compilation should be fine here. >=20 > @@ -196,7 +200,11 @@ dequeue_bulk(void *p) > unsigned i; > void *burst[MAX_BURST] =3D {0}; >=20 > - if ( __sync_add_and_fetch(&lcore_count, 1) !=3D 2 ) > +#ifdef RTE_USE_C11_MEM_MODEL > + if (__atomic_add_fetch(&lcore_count, 1, __ATOMIC_RELAXED) !=3D 2) > #else > + if (__sync_add_and_fetch(&lcore_count, 1) !=3D 2) #endif > while(lcore_count !=3D 2) > rte_pause(); >=20 > -- > 2.7.4