From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45430C10DCE for ; Fri, 13 Mar 2020 10:55:56 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id D683220724 for ; Fri, 13 Mar 2020 10:55:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=accelercomm-com.20150623.gappssmtp.com header.i=@accelercomm-com.20150623.gappssmtp.com header.b="EzdcB8Wu" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D683220724 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=accelercomm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 96B091BFA5; Fri, 13 Mar 2020 11:55:54 +0100 (CET) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by dpdk.org (Postfix) with ESMTP id 36D591BF97 for ; Fri, 13 Mar 2020 11:55:53 +0100 (CET) Received: by mail-wr1-f67.google.com with SMTP id z15so11488638wrl.1 for ; Fri, 13 Mar 2020 03:55:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=accelercomm-com.20150623.gappssmtp.com; s=20150623; h=subject:to:references:from:message-id:date:user-agent:mime-version :in-reply-to:content-transfer-encoding:content-language; bh=FjfU7lLEYIX8JxKaaM3XU4MUMV1boOSmqk8PakBzX1I=; b=EzdcB8WuZiotvjNXjbmsMIRxoPZD1qIY4mRbIsKbkvDGwEgQetMdhMi9ntdZXUv9Dn lqDGuRxVbMVJIEg5cEY1LNOM55wyaPlc6JXroVzdC3cwOstAeKvLOVTT/uu1x4bFIY1k QE+N98xXEVGdJE+KSrJj8L63JwgskELi/VZaAdLFRbSPhPT1DmtM4M76iqhAfV851aUU zbph5nw8oqyByzE11PYj0vyY/zt00Vb/l/7hCXbH13WXZLpOx5zhUlTLHNtuLokjA+Hj Y3xTngEYYwSpdIATFZp9tsWYWgIT77aDcwnxsS3OZzyLREGemo1sTywRdHuBfTNMX+ty zavg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-transfer-encoding :content-language; bh=FjfU7lLEYIX8JxKaaM3XU4MUMV1boOSmqk8PakBzX1I=; b=Q9j7CTLWjdrstNlUfIudoY2YwC63W0yF4WB/PmKQAldrStogdfG/gutQu5L8ZTF56H WDf/L9b7VAnnt8/VlN6FlJfrdpXJZelksMJV8ADH8KIb6RQZKozr319a1IOgjihuDR89 2P+rV1uVvfYNquTuGjgVtvKCL+pKIhO+vpggHK3FJi3LjxrQDv/04WKhfpwpa2MNsCYO +C3M6zdOy2Gvd6QXxP+pfL/MDhXs1+fIusxkBkD2JFXWMgd9Jhdn0Fpw7DQvAXVQfAQW p54U75gWqe9ZcbJtfJv1Xn1LeI9/1mQvBPncQNBjPjWaNovwirJ2ZtL1k5u/laBa3/GH LHxA== X-Gm-Message-State: ANhLgQ3QKCDjKqLrT/2ZeLH+uUFr552G9L+tj/ykZOMxGT3YKJZ3t3nP uheY7fAOeZqQ7VMpRRVujAlFRAHHxc0= X-Google-Smtp-Source: ADFU+vtitYLMUxYNJS1PKQsFsOywkkmcuggnm9ND7KjfBI/7Qr3qCi/+OZluxMPTS6hdEZ9yYYJtkQ== X-Received: by 2002:a5d:61c9:: with SMTP id q9mr17885168wrv.164.1584096952224; Fri, 13 Mar 2020 03:55:52 -0700 (PDT) Received: from [192.168.1.189] ([89.21.231.54]) by smtp.gmail.com with ESMTPSA id q3sm15444580wmj.38.2020.03.13.03.55.51 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Mar 2020 03:55:51 -0700 (PDT) To: dev@dpdk.org References: <1582778348-113547-15-git-send-email-nicolas.chautru@intel.com> <1583348102-13253-1-git-send-email-nicolas.chautru@intel.com> <1583348102-13253-6-git-send-email-nicolas.chautru@intel.com> From: Dave Burley Message-ID: Date: Fri, 13 Mar 2020 10:55:51 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <1583348102-13253-6-git-send-email-nicolas.chautru@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Subject: Re: [dpdk-dev] [PATCH v3 05/14] test-bbdev: rename FPGA LTE macros to be more explicit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Acked-by: Dave Burley On 04/03/2020 18:54, Nicolas Chautru wrote: > From: Nic Chautru > > Self-contained and cosmetic renaming of macro > so that to be more explicit for future extension. > > Signed-off-by: Nic Chautru > --- > app/test-bbdev/test_bbdev_perf.c | 51 +++++++++++++++------------------------- > 1 file changed, 19 insertions(+), 32 deletions(-) > > diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c > index d46966d..aa8bb71 100644 > --- a/app/test-bbdev/test_bbdev_perf.c > +++ b/app/test-bbdev/test_bbdev_perf.c > @@ -18,10 +18,6 @@ > #include > #include > > -#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC > -#include > -#endif > - > #include "main.h" > #include "test_bbdev_vector.h" > > @@ -31,15 +27,16 @@ > #define TEST_REPETITIONS 1000 > > #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC > -#define FPGA_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf") > -#define FPGA_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf") > -#define VF_UL_QUEUE_VALUE 4 > -#define VF_DL_QUEUE_VALUE 4 > -#define UL_BANDWIDTH 3 > -#define DL_BANDWIDTH 3 > -#define UL_LOAD_BALANCE 128 > -#define DL_LOAD_BALANCE 128 > -#define FLR_TIMEOUT 610 > +#include > +#define FPGA_LTE_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf") > +#define FPGA_LTE_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf") > +#define VF_UL_4G_QUEUE_VALUE 4 > +#define VF_DL_4G_QUEUE_VALUE 4 > +#define UL_4G_BANDWIDTH 3 > +#define DL_4G_BANDWIDTH 3 > +#define UL_4G_LOAD_BALANCE 128 > +#define DL_4G_LOAD_BALANCE 128 > +#define FLR_4G_TIMEOUT 610 > #endif > > #define OPS_CACHE_SIZE 256U > @@ -521,11 +518,11 @@ typedef int (test_case_function)(struct active_device *ad, > */ > #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC > if ((get_init_device() == true) && > - (!strcmp(info->drv.driver_name, FPGA_PF_DRIVER_NAME))) { > + (!strcmp(info->drv.driver_name, FPGA_LTE_PF_DRIVER_NAME))) { > struct fpga_lte_fec_conf conf; > unsigned int i; > > - printf("Configure FPGA FEC Driver %s with default values\n", > + printf("Configure FPGA LTE FEC Driver %s with default values\n", > info->drv.driver_name); > > /* clear default configuration before initialization */ > @@ -539,22 +536,22 @@ typedef int (test_case_function)(struct active_device *ad, > > for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) { > /* Number of UL queues per VF (fpga supports 8 VFs) */ > - conf.vf_ul_queues_number[i] = VF_UL_QUEUE_VALUE; > + conf.vf_ul_queues_number[i] = VF_UL_4G_QUEUE_VALUE; > /* Number of DL queues per VF (fpga supports 8 VFs) */ > - conf.vf_dl_queues_number[i] = VF_DL_QUEUE_VALUE; > + conf.vf_dl_queues_number[i] = VF_DL_4G_QUEUE_VALUE; > } > > /* UL bandwidth. Needed for schedule algorithm */ > - conf.ul_bandwidth = UL_BANDWIDTH; > + conf.ul_bandwidth = UL_4G_BANDWIDTH; > /* DL bandwidth */ > - conf.dl_bandwidth = DL_BANDWIDTH; > + conf.dl_bandwidth = DL_4G_BANDWIDTH; > > /* UL & DL load Balance Factor to 64 */ > - conf.ul_load_balance = UL_LOAD_BALANCE; > - conf.dl_load_balance = DL_LOAD_BALANCE; > + conf.ul_load_balance = UL_4G_LOAD_BALANCE; > + conf.dl_load_balance = DL_4G_LOAD_BALANCE; > > /**< FLR timeout value */ > - conf.flr_time_out = FLR_TIMEOUT; > + conf.flr_time_out = FLR_4G_TIMEOUT; > > /* setup FPGA PF with configuration information */ > ret = fpga_lte_fec_configure(info->dev_name, &conf); > @@ -2862,11 +2859,6 @@ typedef int (test_case_function)(struct active_device *ad, > > start_time = rte_rdtsc_precise(); > > - /* > - * printf("Latency Debug %d\n", > - * ops_enq[0]->ldpc_enc.cb_params.z_c); REMOVEME > - */ > - > enq = rte_bbdev_enqueue_ldpc_enc_ops(dev_id, queue_id, > &ops_enq[enq], burst_sz); > TEST_ASSERT(enq == burst_sz, > @@ -2892,11 +2884,6 @@ typedef int (test_case_function)(struct active_device *ad, > TEST_ASSERT_SUCCESS(ret, "Validation failed!"); > } > > - /* > - * printf("Ready to free - deq %d num_to_process %d\n", FIXME > - * deq, num_to_process); > - * printf("cache %d\n", ops_enq[0]->mempool->cache_size); > - */ > rte_bbdev_enc_op_free_bulk(ops_enq, deq); > dequeued += deq; > }