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[46.138.85.91]) by smtp.googlemail.com with ESMTPSA id d9sm487076ljq.54.2021.08.17.22.21.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Aug 2021 22:21:32 -0700 (PDT) Subject: Re: [PATCH v8 01/34] opp: Add dev_pm_opp_sync() helper To: Viresh Kumar Cc: Thierry Reding , Jonathan Hunter , Ulf Hansson , Viresh Kumar , Stephen Boyd , Peter De Schrijver , Mikko Perttunen , Peter Chen , Mark Brown , Lee Jones , =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= , Nishanth Menon , Vignesh Raghavendra , Richard Weinberger , Miquel Raynal , Lucas Stach , Stefan Agner , Adrian Hunter , Mauro Carvalho Chehab , Rob Herring , Michael Turquette , linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-staging@lists.linux.dev, linux-spi@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mtd@lists.infradead.org, linux-mmc@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org References: <20210817012754.8710-1-digetx@gmail.com> <20210817012754.8710-2-digetx@gmail.com> <20210817075515.vyyv7z37e6jcrhsl@vireshk-i7> <710261d9-7ae3-5155-c0a2-f8aed2408d0b@gmail.com> <20210818035533.ieqkexltfvvf2p4n@vireshk-i7> <5b2a80c1-9743-e633-6257-ede94c8a274c@gmail.com> <20210818043131.7klajx6drvvkftoc@vireshk-i7> <20210818045307.4brb6cafkh3adjth@vireshk-i7> From: Dmitry Osipenko Message-ID: <080469b3-612b-3a34-86e5-7037a64de2fe@gmail.com> Date: Wed, 18 Aug 2021 08:21:30 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210818045307.4brb6cafkh3adjth@vireshk-i7> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" 18.08.2021 07:53, Viresh Kumar пишет: > On 18-08-21, 07:37, Dmitry Osipenko wrote: >> This will set voltage level without having an actively used hardware. >> Take a 3d driver for example, if you set the rate on probe and >> rpm-resume will never be called, then the voltage will be set high, >> while hardware is kept suspended if userspace will never wake it up by >> executing a 3d job. > > What exactly are we looking to achieve with this stuff ? Cache the > current performance state with genpd (based on the state bootloader's > has set) ? Yes, GENPD will cache the perf state across suspend/resume and initially cached value is out of sync with h/w. > Or anything else as well ? Nothing else. But let me clarify it all again. Initially the performance state of all GENPDs is 0 for all devices. The clock rate is preinitialized for all devices to a some default rate by clk driver, or by bootloader or by assigned-clocks in DT. When device is rpm-resumed, the resume callback of a device driver enables the clock. Before clock is enabled, the voltage needs to be configured in accordance to the clk rate. So now we have a GENPD with pstate=0 on a first rpm-resume, which doesn't match the h/w configuration. Calling dev_pm_opp_sync() sets the pstate in accordance to the h/w config. In a previous v7 I proposed to preset the rpm_pstate of GENPD (perf level that is restored before device is rpm-resumed) from PD's attach_dev callback, but Ulf didn't like that because it requires to use and modify GENPD 'private' variables from a PD driver. We decided that will be better to make device drivers to explicitly sync the perf state, which I implemented in this v8.