From: "Sharma, Shashank" <shashank.sharma@intel.com>
To: Uma Shankar <uma.shankar@intel.com>,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com
Subject: Re: [v6 10/13] drm/i915: Enable infoframes on GLK+ for HDR
Date: Fri, 29 Mar 2019 18:01:55 +0530 [thread overview]
Message-ID: <0a7bba29-9fc9-5161-0353-c33871a609d2@intel.com> (raw)
In-Reply-To: <1553078906-5991-11-git-send-email-uma.shankar@intel.com>
On 3/20/2019 4:18 PM, Uma Shankar wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> This patch enables infoframes on GLK+ to be
> used to send HDR metadata to HDMI sink.
>
> v2: Addressed Shashank's review comment.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_hdmi.c | 18 +++++++++++++-----
> 2 files changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 31a3020..fe931e7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4718,6 +4718,7 @@ enum {
> #define VIDEO_DIP_FREQ_MASK (3 << 16)
> /* HSW and later: */
> #define DRM_DIP_ENABLE (1 << 28)
> +#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
> #define PSR_VSC_BIT_7_SET (1 << 27)
> #define VSC_SELECT_MASK (0x3 << 25)
> #define VSC_SELECT_SHIFT 25
> @@ -8156,6 +8157,7 @@ enum {
> #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
> #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
> #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
> +#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
> #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
> #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
> #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
> @@ -8169,6 +8171,7 @@ enum {
> #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
> #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
> #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
> +#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
> #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
> #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
> #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
> @@ -8194,6 +8197,7 @@ enum {
> #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
> #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
> #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
> +#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
> #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
> #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index e4bc7fc..8decafd 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -134,6 +134,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
> return VIDEO_DIP_ENABLE_SPD_HSW;
> case HDMI_INFOFRAME_TYPE_VENDOR:
> return VIDEO_DIP_ENABLE_VS_HSW;
> + case HDMI_INFOFRAME_TYPE_DRM:
> + return VIDEO_DIP_ENABLE_DRM_GLK;
> default:
> MISSING_CASE(type);
> return 0;
> @@ -159,6 +161,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
> return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
> case HDMI_INFOFRAME_TYPE_VENDOR:
> return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
> + case HDMI_INFOFRAME_TYPE_DRM:
> + return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
> default:
> MISSING_CASE(type);
> return INVALID_MMIO_REG;
> @@ -545,7 +549,8 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
>
> return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
> VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
> - VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
> + VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
> + VIDEO_DIP_ENABLE_DRM_GLK);
I think this should also be GEN check protected, as
hsw_infoframes_enabled will be called by many platforms, and before GLK
they cant support DRM_IF.
> }
>
> static const u8 infoframe_type_to_idx[] = {
> @@ -1177,7 +1182,8 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
>
> val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
> VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
> - VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
> + VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
> + VIDEO_DIP_ENABLE_DRM_GLK);
Same here.
- Shashank
>
> if (!enable) {
> I915_WRITE(reg, val);
> @@ -1200,9 +1206,11 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
> intel_write_infoframe(encoder, crtc_state,
> HDMI_INFOFRAME_TYPE_VENDOR,
> &crtc_state->infoframes.hdmi);
> - intel_write_infoframe(encoder, crtc_state,
> - HDMI_INFOFRAME_TYPE_DRM,
> - &crtc_state->infoframes.drm);
> + if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
> + conn_state->hdr_metadata_changed)
> + intel_write_infoframe(encoder, crtc_state,
> + HDMI_INFOFRAME_TYPE_DRM,
> + &crtc_state->infoframes.drm);
> }
>
> void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
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next prev parent reply other threads:[~2019-03-29 12:31 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-20 10:48 [v6 00/13] Add HDR Metadata Parsing and handling in DRM layer Uma Shankar
2019-03-20 10:48 ` [v6 01/13] drm: Add HDR source metadata property Uma Shankar
2019-03-21 11:30 ` Brian Starkey
2019-03-29 6:13 ` Shankar, Uma
2019-03-20 10:48 ` [v6 02/13] drm: Parse HDR metadata info from EDID Uma Shankar
2019-03-29 11:41 ` Sharma, Shashank
2019-03-20 10:48 ` [v6 03/13] drm: Parse Colorimetry data block " Uma Shankar
2019-03-21 11:17 ` Brian Starkey
2019-03-29 6:16 ` Shankar, Uma
2019-03-20 10:48 ` [v6 04/13] drm/i915: Attach HDR metadata property to connector Uma Shankar
2019-03-20 10:48 ` [v6 05/13] drm: Implement HDR output metadata set and get property handling Uma Shankar
2019-03-21 11:46 ` Brian Starkey
2019-03-29 6:21 ` Shankar, Uma
2019-03-20 10:48 ` [v6 06/13] drm: Enable HDR infoframe support Uma Shankar
2019-03-21 11:41 ` Brian Starkey
2019-03-29 6:24 ` Shankar, Uma
2019-03-20 10:48 ` [v6 07/13] drm/i915: Write HDR infoframe and send to panel Uma Shankar
2019-03-29 11:48 ` Sharma, Shashank
2019-03-20 10:48 ` [v6 08/13] drm/i915: [DO NOT MERGE] hack for glk board outputs Uma Shankar
2019-03-20 10:48 ` [v6 09/13] drm/i915: Add HLG EOTF Uma Shankar
2019-03-20 10:48 ` [v6 10/13] drm/i915: Enable infoframes on GLK+ for HDR Uma Shankar
2019-03-29 12:31 ` Sharma, Shashank [this message]
2019-03-20 10:48 ` [v6 11/13] drm/i915:Enabled Modeset when HDR Infoframe changes Uma Shankar
2019-03-29 12:56 ` Sharma, Shashank
2019-03-20 10:48 ` [v6 12/13] drm/i915: Set Infoframe for non modeset case for HDR Uma Shankar
2019-03-29 12:14 ` Sharma, Shashank
2019-03-29 14:04 ` Ville Syrjälä
2019-04-02 16:27 ` Shankar, Uma
2019-03-20 10:48 ` [v6 13/13] video/hdmi: Add const variants for drm infoframe Uma Shankar
2019-03-21 12:00 ` Brian Starkey
2019-03-29 6:29 ` Shankar, Uma
2019-03-29 12:22 ` Sharma, Shashank
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