From: Yongqiang Niu <yongqiang.niu@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH v1, 10/18] drm/mediatek: add gmc_bits for ovl private data
Date: Wed, 13 Mar 2019 16:25:55 +0800 [thread overview]
Message-ID: <1552465563-6940-11-git-send-email-yongqiang.niu@mediatek.com> (raw)
In-Reply-To: <1552465563-6940-1-git-send-email-yongqiang.niu@mediatek.com>
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This patch add gmc_bits for ovl private data
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 28d1911..afb313c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -39,7 +39,9 @@
#define DISP_REG_OVL_ADDR_MT8173 0x0f40
#define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
-#define OVL_RDMA_MEM_GMC 0x40402020
+#define GMC_THRESHOLD_BITS 16
+#define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4)
+#define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8)
#define OVL_CON_BYTE_SWAP BIT(24)
#define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
@@ -57,6 +59,7 @@
struct mtk_disp_ovl_data {
unsigned int addr;
+ unsigned int gmc_bits;
bool fmt_rgb565_is_0;
};
@@ -140,9 +143,23 @@ static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
{
unsigned int reg;
+ unsigned int gmc_thrshd_l;
+ unsigned int gmc_thrshd_h;
+ unsigned int gmc_value;
+ struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
- writel(OVL_RDMA_MEM_GMC, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
+
+ gmc_thrshd_l = GMC_THRESHOLD_LOW >>
+ (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
+ gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
+ (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
+ if (ovl->data->gmc_bits == 10)
+ gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16;
+ else
+ gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
+ gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
+ writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
reg = reg | BIT(idx);
@@ -324,11 +341,13 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
.addr = DISP_REG_OVL_ADDR_MT2701,
+ .gmc_bits = 8,
.fmt_rgb565_is_0 = false,
};
static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
.addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 8,
.fmt_rgb565_is_0 = true,
};
--
1.8.1.1.dirty
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next prev parent reply other threads:[~2019-03-13 8:31 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-13 8:25 [RESEND PATCH v1, 00/18] add drm support for MT8183 Yongqiang Niu
2019-03-13 8:25 ` [RESEND PATCH v1, 01/18] drm/mediatek: update dt-bindings for mt8183 Yongqiang Niu
2019-03-13 8:25 ` [RESEND PATCH v1, 02/18] drm/mediatek: add mutex mod and sof into ddp private data Yongqiang Niu
2019-03-13 8:25 ` [RESEND PATCH v1, 03/18] drm/mediatek: redefine mtk_ddp_sout_sel Yongqiang Niu
2019-03-13 8:25 ` [RESEND PATCH v1, 04/18] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel Yongqiang Niu
2019-03-13 8:25 ` [RESEND PATCH v1, 05/18] drm/mediatek: add ddp component CCORR Yongqiang Niu
2019-03-13 8:25 ` [RESEND PATCH v1, 06/18] drm/mediatek: add mmsys private data for ddp path config Yongqiang Niu
2019-03-13 8:25 ` [RESEND PATCH v1, 07/18] drm/mediatek: add commponent OVL0_2L Yongqiang Niu
2019-03-13 8:25 ` [RESEND PATCH v1, 08/18] drm/mediatek: add component OVL1_2L Yongqiang Niu
2019-03-13 8:25 ` [RESEND PATCH v1, 09/18] drm/mediatek: add component DITHER Yongqiang Niu
2019-03-13 8:25 ` Yongqiang Niu [this message]
2019-03-13 8:25 ` [RESEND PATCH v1, 11/18] drm/medaitek: add layer_nr for ovl private data Yongqiang Niu
2019-03-13 8:25 ` [RESEND PATCH v1, 12/18] drm/mediatek: add function to connect module with it's previous one Yongqiang Niu
2019-03-13 8:25 ` [RESEND PATCH v1, 13/18] drm/mediatek: add ddp write register common api Yongqiang Niu
2019-03-13 8:25 ` [RESEND PATCH v1, 14/18] drm/mediatek: add connect function for ovl Yongqiang Niu
2019-03-13 8:26 ` [RESEND PATCH v1, 15/18] drm/mediatek: add RDMA1 fifo size into RDMA private data Yongqiang Niu
2019-03-13 8:26 ` [RESEND PATCH v1, 16/18] drm/mediatek: add function mtk_ddp_comp_get_type Yongqiang Niu
2019-03-13 8:26 ` [RESEND PATCH v1, 17/18] drm/mediatek: add ovl0/ovl0_2l usecase Yongqiang Niu
2019-03-13 8:26 ` [RESEND PATCH v1, 18/18] drm/mediatek: add support for mediatek SOC MT8183 Yongqiang Niu
2019-03-13 10:49 ` [RESEND PATCH v1, 00/18] add drm support for MT8183 Nicolas Boichat
2019-03-13 9:11 Yongqiang Niu
2019-03-13 9:12 ` [RESEND PATCH v1, 10/18] drm/mediatek: add gmc_bits for ovl private data Yongqiang Niu
2019-03-13 9:24 [RESEND PATCH v1, 00/18] add drm support for MT8183 Yongqiang Niu
2019-03-13 9:25 ` [RESEND PATCH v1, 10/18] drm/mediatek: add gmc_bits for ovl private data Yongqiang Niu
2019-03-13 12:00 [RESEND PATCH v1, 00/18] add drm support for MT8183 Yongqiang Niu
2019-03-13 12:00 ` [RESEND PATCH v1, 10/18] drm/mediatek: add gmc_bits for ovl private data Yongqiang Niu
2019-03-14 8:05 [RESEND PATCH v1, 00/18] add drm support for MT8183 Yongqiang Niu
2019-03-14 8:05 ` [RESEND PATCH v1, 10/18] drm/mediatek: add gmc_bits for ovl private data Yongqiang Niu
2019-03-14 12:05 [RESEND PATCH v1 00/18] add drm support for MT8183 yongqiang.niu
2019-03-14 12:05 ` [RESEND PATCH v1 10/18] drm/mediatek: add gmc_bits for ovl private data yongqiang.niu
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