From: CK Hu <ck.hu@mediatek.com>
To: Hsin-Yi Wang <hsinyi@chromium.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
Project_Global_Chrome_Upstream_Group@mediatek.com,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v10 7/9] drm/mediatek: enable dither function
Date: Thu, 28 Jan 2021 14:01:09 +0800 [thread overview]
Message-ID: <1611813669.28312.5.camel@mtksdaap41> (raw)
In-Reply-To: <20210127045422.2418917-8-hsinyi@chromium.org>
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 37 ++++++++++++++++++++-
> 1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 8173f709272be..ee54505412dcd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -53,7 +53,9 @@
> #define DITHER_EN BIT(0)
> #define DISP_DITHER_CFG 0x0020
> #define DITHER_RELAY_MODE BIT(0)
> +#define DITHER_ENGINE_EN BIT(1)
> #define DISP_DITHER_SIZE 0x0030
> +#define DITHER_REG(idx) (0x100 + (idx) * 4)
>
> #define LUT_10BIT_MASK 0x03ff
>
> @@ -313,8 +315,41 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> + bool enable = true;
> +
> + const u32 dither_setting[] = {
> + 0x00000000, /* 5 */
> + 0x00003002, /* 6 */
> + 0x00000000, /* 7 */
> + 0x00000000, /* 8 */
> + 0x00000000, /* 9 */
> + 0x00000000, /* 10 */
> + 0x00000000, /* 11 */
> + 0x00000011, /* 12 */
> + 0x00000000, /* 13 */
> + 0x00000000, /* 14 */
Could you explain what is this?
> + };
> +
> + if (bpc == 6) {
> + mtk_ddp_write(cmdq_pkt, 0x40400001, &priv->cmdq_reg, priv->regs, DITHER_REG(15));
> + mtk_ddp_write(cmdq_pkt, 0x40404040, &priv->cmdq_reg, priv->regs, DITHER_REG(16));
> + } else if (bpc == 5) {
> + mtk_ddp_write(cmdq_pkt, 0x50500001, &priv->cmdq_reg, priv->regs, DITHER_REG(15));
> + mtk_ddp_write(cmdq_pkt, 0x50504040, &priv->cmdq_reg, priv->regs, DITHER_REG(16));
This looks very similar to the code in mtk_dither_set(), could you
symbolize this magic number like mtk_dither_set()?
Regards,
CK
> + } else {
> + enable = false;
> + }
> +
> + if (enable) {
> + u32 idx;
> +
> + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)
> + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs,
> + DITHER_REG(idx + 5));
> + }
> +
> mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
> - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> }
>
> static void mtk_dither_start(struct device *dev)
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2021-01-28 6:01 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-27 4:54 [PATCH v10 0/9] drm/mediatek: add support for mediatek SOC MT8183 Hsin-Yi Wang
2021-01-27 4:54 ` [PATCH v10 1/9] arm64: dts: mt8183: rename rdma fifo size Hsin-Yi Wang
2021-01-27 4:54 ` [PATCH v10 2/9] arm64: dts: mt8183: refine gamma compatible name Hsin-Yi Wang
2021-01-27 4:54 ` [PATCH v10 3/9] drm/mediatek: add RDMA fifo size error handle Hsin-Yi Wang
2021-01-27 7:59 ` CK Hu
2021-01-27 4:54 ` [PATCH v10 4/9] drm/mediatek: generalize mtk_dither_set() function Hsin-Yi Wang
2021-01-28 4:39 ` CK Hu
2021-01-28 5:09 ` Hsin-Yi Wang
2021-01-28 5:21 ` CK Hu
2021-01-27 4:54 ` [PATCH v10 5/9] drm/mediatek: separate gamma module Hsin-Yi Wang
2021-01-28 5:33 ` CK Hu
2021-01-27 4:54 ` [PATCH v10 6/9] drm/mediatek: add has_dither private data for gamma Hsin-Yi Wang
2021-01-28 5:34 ` CK Hu
2021-01-27 4:54 ` [PATCH v10 7/9] drm/mediatek: enable dither function Hsin-Yi Wang
2021-01-28 6:01 ` CK Hu [this message]
2021-01-27 4:54 ` [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183 Hsin-Yi Wang
2021-01-28 6:13 ` CK Hu
2021-01-28 6:15 ` Hsin-Yi Wang
2021-01-28 7:00 ` CK Hu
2021-01-28 6:19 ` CK Hu
2021-01-27 4:54 ` [PATCH v10 9/9] drm/mediatek: add support for mediatek SOC MT8183 Hsin-Yi Wang
2021-01-28 6:17 ` CK Hu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1611813669.28312.5.camel@mtksdaap41 \
--to=ck.hu@mediatek.com \
--cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
--cc=airlied@linux.ie \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=hsinyi@chromium.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=mark.rutland@arm.com \
--cc=matthias.bgg@gmail.com \
--cc=yongqiang.niu@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).