* [PATCH] freedreno/a6xx: Add a few registers
@ 2021-04-20 16:42 Akhil P Oommen
0 siblings, 0 replies; 2+ messages in thread
From: Akhil P Oommen @ 2021-04-20 16:42 UTC (permalink / raw)
To: freedreno, dri-devel; +Cc: linux-arm-msm
Add a few new registers for a6xx gpu.
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
---
registers/adreno/a6xx.xml | 2 ++
registers/adreno/a6xx_gmu.xml | 2 ++
2 files changed, 4 insertions(+)
diff --git a/registers/adreno/a6xx.xml b/registers/adreno/a6xx.xml
index 15314fb..3b04565 100644
--- a/registers/adreno/a6xx.xml
+++ b/registers/adreno/a6xx.xml
@@ -1107,6 +1107,7 @@ to upconvert to 32b float internally?
<reg32 offset="0x098D" name="CP_AHB_CNTL"/>
<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
+ <reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
<reg32 offset="0x0210" name="RBBM_STATUS">
@@ -1740,6 +1741,7 @@ to upconvert to 32b float internally?
<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
+ <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
<reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
<reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
<reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
diff --git a/registers/adreno/a6xx_gmu.xml b/registers/adreno/a6xx_gmu.xml
index dbefd0c..f8bf1fd 100644
--- a/registers/adreno/a6xx_gmu.xml
+++ b/registers/adreno/a6xx_gmu.xml
@@ -112,6 +112,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<reg32 offset="0x50e9" name="GMU_RPMH_HYST_CTRL"/>
<reg32 offset="0x50ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/>
<reg32 offset="0x50f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/>
+ <reg32 offset="0x50f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF"/>
<reg32 offset="0x5100" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
<reg32 offset="0x5101" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
<reg32 offset="0x51f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
@@ -193,6 +194,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<reg32 offset="0x9312" name="GMU_AHB_FENCE_RANGE_1"/>
<reg32 offset="0x9c03" name="GPU_CC_GX_GDSCR"/>
<reg32 offset="0x9d42" name="GPU_CC_GX_DOMAIN_MISC"/>
+ <reg32 offset="0xc001" name="GPU_CPR_FSM_CTL"/>
<!-- starts at offset 0x8c00 on most gpus -->
<reg32 offset="0x0004" name="GPU_RSCC_RSC_STATUS0_DRV0"/>
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH] freedreno/a6xx: Add a few registers
@ 2021-04-20 16:47 Akhil P Oommen
0 siblings, 0 replies; 2+ messages in thread
From: Akhil P Oommen @ 2021-04-20 16:47 UTC (permalink / raw)
To: freedreno, dri-devel; +Cc: linux-arm-msm
Add a few new registers for a6xx gpu.
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
---
registers/adreno/a6xx.xml | 2 ++
registers/adreno/a6xx_gmu.xml | 2 ++
2 files changed, 4 insertions(+)
diff --git a/registers/adreno/a6xx.xml b/registers/adreno/a6xx.xml
index 15314fb..3b04565 100644
--- a/registers/adreno/a6xx.xml
+++ b/registers/adreno/a6xx.xml
@@ -1107,6 +1107,7 @@ to upconvert to 32b float internally?
<reg32 offset="0x098D" name="CP_AHB_CNTL"/>
<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
+ <reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
<reg32 offset="0x0210" name="RBBM_STATUS">
@@ -1740,6 +1741,7 @@ to upconvert to 32b float internally?
<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
+ <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
<reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
<reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
<reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
diff --git a/registers/adreno/a6xx_gmu.xml b/registers/adreno/a6xx_gmu.xml
index dbefd0c..f8bf1fd 100644
--- a/registers/adreno/a6xx_gmu.xml
+++ b/registers/adreno/a6xx_gmu.xml
@@ -112,6 +112,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<reg32 offset="0x50e9" name="GMU_RPMH_HYST_CTRL"/>
<reg32 offset="0x50ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/>
<reg32 offset="0x50f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/>
+ <reg32 offset="0x50f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF"/>
<reg32 offset="0x5100" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
<reg32 offset="0x5101" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
<reg32 offset="0x51f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
@@ -193,6 +194,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<reg32 offset="0x9312" name="GMU_AHB_FENCE_RANGE_1"/>
<reg32 offset="0x9c03" name="GPU_CC_GX_GDSCR"/>
<reg32 offset="0x9d42" name="GPU_CC_GX_DOMAIN_MISC"/>
+ <reg32 offset="0xc001" name="GPU_CPR_FSM_CTL"/>
<!-- starts at offset 0x8c00 on most gpus -->
<reg32 offset="0x0004" name="GPU_RSCC_RSC_STATUS0_DRV0"/>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-04-20 16:52 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-20 16:42 [PATCH] freedreno/a6xx: Add a few registers Akhil P Oommen
2021-04-20 16:47 Akhil P Oommen
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).