From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CAC41C4332F for ; Sun, 30 Jan 2022 20:15:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AD3BF113AA5; Sun, 30 Jan 2022 20:15:49 +0000 (UTC) Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4081F113A9E; Sun, 30 Jan 2022 20:15:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1643573748; x=1675109748; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=nlceKRR9XYG+70HrS2RmpUq7A6HORpYsEV0OXmBraE8=; b=XVrSm8A+s1oeFdaS80Ym7ftzf423ubsu+2Lmg+zITtvS0asdNfPQNxXA WWEiI7/i5k5+JqxqQQEkosgAKerHgnqTIjWmX6cTyo5UFzINQ542ugWL2 JuIjfmhRcsaNFUStGWE43heikeck7GO7NMp73gnLc8AAsfoKL8dvTsWHV s=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 30 Jan 2022 12:15:48 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 30 Jan 2022 12:15:46 -0800 X-QCInternal: smtphost Received: from rajeevny-linux.qualcomm.com ([10.204.66.121]) by ironmsg02-blr.qualcomm.com with ESMTP; 31 Jan 2022 01:45:23 +0530 Received: by rajeevny-linux.qualcomm.com (Postfix, from userid 2363605) id 709A521AD2; Mon, 31 Jan 2022 01:45:23 +0530 (IST) From: Rajeev Nandan To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [v5 2/3] drm/msm/dsi: Add dsi phy tuning configuration support Date: Mon, 31 Jan 2022 01:45:18 +0530 Message-Id: <1643573719-32095-3-git-send-email-quic_rajeevny@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1643573719-32095-1-git-send-email-quic_rajeevny@quicinc.com> References: <1643573719-32095-1-git-send-email-quic_rajeevny@quicinc.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: quic_kalyant@quicinc.com, jonathan@marek.ca, airlied@linux.ie, Rajeev Nandan , linux-kernel@vger.kernel.org, quic_abhinavk@quicinc.com, robh+dt@kernel.org, quic_mkrishn@quicinc.com, dmitry.baryshkov@linaro.org, swboyd@chromium.org, sean@poorly.run Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for MSM DSI PHY tuning configuration. Current design is to support drive strength and drive level/amplitude tuning for 10nm PHY version, but this can be extended to other PHY versions. Signed-off-by: Rajeev Nandan Reviewed-by: Dmitry Baryshkov --- Changes in v2: - New. - Split into generic code and 10nm-specific part (Dmitry Baryshkov) Changes in v3: - s/ops.tuning_cfg_init/ops.parse_dt_properties To parse phy version specific DT properties (Dmitry Baryshkov) - Address comments for phy tuning data structure (Dmitry Baryshkov) No change since v4 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 6 ++++++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 8c65ef6..fcbca76 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -739,6 +739,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) } } + if (phy->cfg->ops.parse_dt_properties) { + ret = phy->cfg->ops.parse_dt_properties(phy); + if (ret) + goto fail; + } + ret = dsi_phy_regulator_init(phy); if (ret) goto fail; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index b91303a..9e08081 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -25,6 +25,7 @@ struct msm_dsi_phy_ops { void (*save_pll_state)(struct msm_dsi_phy *phy); int (*restore_pll_state)(struct msm_dsi_phy *phy); bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable); + int (*parse_dt_properties)(struct msm_dsi_phy *phy); }; struct msm_dsi_phy_cfg { @@ -81,6 +82,8 @@ struct msm_dsi_dphy_timing { #define DSI_PIXEL_PLL_CLK 1 #define NUM_PROVIDED_CLKS 2 +#define DSI_LANE_MAX 5 + struct msm_dsi_phy { struct platform_device *pdev; void __iomem *base; @@ -98,6 +101,7 @@ struct msm_dsi_phy { struct msm_dsi_dphy_timing timing; const struct msm_dsi_phy_cfg *cfg; + void *tuning_cfg; enum msm_dsi_phy_usecase usecase; bool regulator_ldo_mode; -- 2.7.4