From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0049CC433EF for ; Tue, 24 May 2022 03:36:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 16F5310E182; Tue, 24 May 2022 03:36:03 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0A0E610E182 for ; Tue, 24 May 2022 03:36:00 +0000 (UTC) X-UUID: 10ce425b9544498782f047918b3a7697-20220524 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:e7794dcc-2f7a-4448-b895-7aa5923d00d4, OB:0, LO B:0,IP:0,URL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:25 X-CID-META: VersionHash:2a19b09, CLOUDID:9610627a-5ef6-470b-96c9-bdb8ced32786, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:0,BEC:nil X-UUID: 10ce425b9544498782f047918b3a7697-20220524 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1951524685; Tue, 24 May 2022 11:35:57 +0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 24 May 2022 11:35:56 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 24 May 2022 11:35:55 +0800 Received: from mhfsdcap04 (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 24 May 2022 11:35:48 +0800 Message-ID: <1998a59df3b27fbeb0ca7945925e47336977bcd5.camel@mediatek.com> Subject: Re: [PATCH v10 02/21] dt-bindings: mediatek,dp: Add Display Port binding From: Chunfeng Yun To: Guillaume Ranquet , Chun-Kuang Hu , Philipp Zabel , "David Airlie" , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Kishon Vijay Abraham I , "Vinod Koul" , Helge Deller , CK Hu , Jitao shi Date: Tue, 24 May 2022 11:35:46 +0800 In-Reply-To: <20220523104758.29531-3-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> <20220523104758.29531-3-granquet@baylibre.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Markus Schneider-Pargmann , linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote: > From: Markus Schneider-Pargmann > > This controller is present on several mediatek hardware. Currently > mt8195 and mt8395 have this controller without a functional > difference, > so only one compatible field is added. > > The controller can have two forms, as a normal display port and as an > embedded display port. > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > --- > .../display/mediatek/mediatek,dp.yaml | 99 > +++++++++++++++++++ > 1 file changed, 99 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > new file mode 100644 > index 000000000000..36ae0a6df299 > --- /dev/null > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > @@ -0,0 +1,99 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: > http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Display Port Controller > + > +maintainers: > + - CK Hu > + - Jitao shi > + > +description: | > + Device tree bindings for the MediaTek (embedded) Display Port > controller > + present on some MediaTek SoCs. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8195-dp-tx > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: faxi clock > + > + clock-names: > + items: > + - const: faxi > + > + power-domains: > + maxItems: 1 > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: Input endpoint of the controller, usually > dp_intf > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: Output endpoint of the controller > + > + max-lanes: > + maxItems: 1 > + description: maximum number of lanes supported by the hardware > + > + max-linkrate: > + maxItems: 1 > + description: maximum link rate supported by the hardware > + > +required: > + - compatible > + - reg > + - interrupts > + - ports > + - max-lanes > + - max-linkrate > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + edp_tx: edp_tx@1c500000 { 'edp_tx: ' can be removed > + compatible = "mediatek,mt8195-dp-tx"; > + reg = <0 0x1c500000 0 0x8000>; reg = <0x1c500000 0x8000>; #address-cells, #size-cells are both 1 by default > + interrupts = ; > + power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; > + pinctrl-names = "default"; > + pinctrl-0 = <&edp_pin>; > + max-lanes = /bits/ 8 <4>; > + max-linkrate = /bits/ 8 <0x1e>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + edp_in: endpoint { > + remote-endpoint = <&dp_intf0_out>; > + }; > + }; > + port@1 { > + reg = <1>; > + edp_out: endpoint { > + remote-endpoint = <&panel_in>; > + }; > + }; > + }; > + };