Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in
drivers/gpu/drm/i915/intel_display.c between commit cc173961a680
("drm/i915: do not update cursor in crtc mode set") from the
drm-intel-fixes tree and commit e9fd1c02aca7 ("drm/i915: don't enable
DPLL for DSI") from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    sfr@canb.auug.org.au

diff --cc drivers/gpu/drm/i915/intel_display.c
index d8a1d98,2ed974e..0000000
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@@ -4863,21 -4915,27 +4915,24 @@@ static int i9xx_crtc_mode_set(struct dr
  
  	refclk = i9xx_get_refclk(crtc, num_connectors);
  
- 	/*
- 	 * Returns a set of divisors for the desired target clock with the given
- 	 * refclk, or FALSE.  The returned values represent the clock equation:
- 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
- 	 */
- 	limit = intel_limit(crtc, refclk);
- 	ok = dev_priv->display.find_dpll(limit, crtc,
- 					 intel_crtc->config.port_clock,
- 					 refclk, NULL, &clock);
- 	if (!ok && !intel_crtc->config.clock_set) {
- 		DRM_ERROR("Couldn't find PLL settings for mode!\n");
- 		return -EINVAL;
+ 	if (!is_dsi && !intel_crtc->config.clock_set) {
+ 		/*
+ 		 * Returns a set of divisors for the desired target clock with
+ 		 * the given refclk, or FALSE.  The returned values represent
+ 		 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
+ 		 * 2) / p1 / p2.
+ 		 */
+ 		limit = intel_limit(crtc, refclk);
+ 		ok = dev_priv->display.find_dpll(limit, crtc,
+ 						 intel_crtc->config.port_clock,
+ 						 refclk, NULL, &clock);
+ 		if (!ok && !intel_crtc->config.clock_set) {
+ 			DRM_ERROR("Couldn't find PLL settings for mode!\n");
+ 			return -EINVAL;
+ 		}
  	}
  
- 	if (is_lvds && dev_priv->lvds_downclock_avail) {
 -	/* Ensure that the cursor is valid for the new mode before changing... */
 -	intel_crtc_update_cursor(crtc, true);
 -
+ 	if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
  		/*
  		 * Ensure we match the reduced clock's P to the target clock.
  		 * If the clocks don't match, we can't switch the display clock
@@@ -8199,11 -8377,11 +8371,12 @@@ static void intel_dump_pipe_config(stru
  		      pipe_config->gmch_pfit.control,
  		      pipe_config->gmch_pfit.pgm_ratios,
  		      pipe_config->gmch_pfit.lvds_border_bits);
 -	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
 +	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
  		      pipe_config->pch_pfit.pos,
 -		      pipe_config->pch_pfit.size);
 +		      pipe_config->pch_pfit.size,
 +		      pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
  	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
+ 	DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
  }
  
  static bool check_encoder_cloning(struct drm_crtc *crtc)