From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: "Timur Kristóf" <timur.kristof@gmail.com>
Cc: michael.jamet@intel.com, dri-devel@lists.freedesktop.org
Subject: Re: Missing Thunderbolt 3 PCI-E atomics support
Date: Thu, 14 Mar 2019 20:17:03 +0200 [thread overview]
Message-ID: <20190314181703.GD3622@lahna.fi.intel.com> (raw)
In-Reply-To: <4adcd6da87f61581cd165220bb20b78c98d3faa1.camel@gmail.com>
On Thu, Mar 14, 2019 at 06:54:21PM +0100, Timur Kristóf wrote:
> On Thu, 2019-03-14 at 19:40 +0200, Mika Westerberg wrote:
> > On Thu, Mar 14, 2019 at 06:26:00PM +0100, Timur Kristóf wrote:
> > > I know atomics is a PCIe feature, but in this case the PCIe goes
> > > through TB3, so I would assume it has something to do with it.
> >
> > Does it work if you plug the graphics card directly to the PCIe slot?
>
> There is no PCIe slot in which I could plug the graphics card.
> At least I'm not aware of there being one on this laptop.
> Please correct me if I'm wrong.
No, you are right. I forgot that this is a laptop.
> >
> > > Here is the output of 'lspci -vv':
> > > https://pastebin.com/Qt5RUFVc
> >
> > The root port (1c.4) says this:
> >
> > DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF
> > Not Supported ARIFwd+
> > AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
> >
> > Not knowing much about AtomicOps but to me this looks like the root
> > port
> > does not support the feature.
>
> What kind of output should lspci show if the feature were supported?
The AMD card has this:
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported
AtomicOpsCap: 32bit+ 64bit+ 128bitCAS-
so I would expect something similar on the root port side as
pci_enable_atomic_ops_to_root() fails otherwise with mask of
PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64 that the
AMD driver requests.
> As far as I understand the root port is integrated in the CPU, or in
> the chipset maybe? It says it's a Sunrise Point-LP, and I googled it
> but was unable to find a spec sheet.
You can find it here:
https://www.intel.com/content/www/us/en/products/docs/processors/core/6th-gen-core-pch-u-y-io-datasheet-vol-2.html
Pages 845-826 show the DEVCAP2 register for the 1c.4 (D28/F4) and it
does not seem to have AtomicOps caps set.
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next prev parent reply other threads:[~2019-03-14 18:17 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-13 18:09 Missing Thunderbolt 3 PCI-E atomics support Timur Kristóf
2019-03-14 10:30 ` Mika Westerberg
2019-03-14 17:26 ` Timur Kristóf
2019-03-14 17:40 ` Mika Westerberg
2019-03-14 17:54 ` Timur Kristóf
2019-03-14 18:17 ` Mika Westerberg [this message]
2019-03-14 18:36 ` Timur Kristóf
2019-03-15 19:46 ` Dieter Nützel
2019-03-15 20:03 ` Alex Deucher
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