From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Michal Simek <michal.simek@xilinx.com>
Cc: Hyun Kwon <hyun.kwon@xilinx.com>,
dri-devel@lists.freedesktop.org,
Satish Kumar Nagireddy <SATISHNA@xilinx.com>
Subject: Re: [PATCH v10 4/4] arm64: dts: zynqmp: zcu106-revA: Wire up the DisplayPort subsystem
Date: Thu, 5 Dec 2019 17:19:12 +0200 [thread overview]
Message-ID: <20191205151912.GP4734@pendragon.ideasonboard.com> (raw)
In-Reply-To: <11a7c38f-8fe4-09f9-3202-d976edef6843@xilinx.com>
Hi Michal,
On Fri, Nov 15, 2019 at 09:30:10AM +0100, Michal Simek wrote:
> On 08. 11. 19 18:59, Laurent Pinchart wrote:
> > Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
> > the DisplayPort connector.
> >
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > ---
> > .../arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> > index 93ce7eb81498..4656f25b6b04 100644
> > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> > @@ -13,6 +13,7 @@
> > #include "zynqmp-clk.dtsi"
> > #include <dt-bindings/input/input.h>
> > #include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/phy/phy.h>
> >
> > / {
> > model = "ZynqMP ZCU106 RevA";
> > @@ -69,6 +70,17 @@
> > status = "okay";
> > };
> >
> > +&dpdma {
> > + status = "okay";
> > +};
> > +
> > +&dpsub {
> > + status = "okay";
> > + phy-names = "dp-phy0", "dp-phy1";
> > + phys = <&lane1 PHY_TYPE_DP 0 3 27000000>,
> > + <&lane0 PHY_TYPE_DP 1 3 27000000>;
>
> It is aligned with stuff in Xilinx tree.
> I think that putting any clock value here is wrong.
> It should really be pointing to &clk whatever it is.
> Then you can support more cases where clock doesn't need to be fixed and
> it is also aligned with clock binding.
OK, I'll check that when working on the PHY driver.
> > +};
> > +
> > /* fpd_dma clk 667MHz, lpd_dma 500MHz */
> > &fpd_dma_chan1 {
> > status = "okay";
> > @@ -503,6 +515,10 @@
> > no-1-8-v;
> > };
> >
> > +&serdes {
> > + status = "okay";
> > +};
> > +
> > &uart0 {
> > status = "okay";
> > };
--
Regards,
Laurent Pinchart
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prev parent reply other threads:[~2019-12-05 15:19 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-08 17:59 [PATCH v10 0/4] Xilinx ZynqMP DisplayPort Subsystem DRM/KMS driver Laurent Pinchart
2019-11-08 17:59 ` [PATCH v10 1/4] dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings Laurent Pinchart
2019-11-08 19:44 ` Rob Herring
2019-11-08 17:59 ` [PATCH v10 2/4] drm: xlnx: DRM/KMS driver for Xilinx ZynqMP DisplayPort Subsystem Laurent Pinchart
2019-11-08 17:59 ` [PATCH v10 3/4] arm64: dts: zynqmp: Add DisplayPort subsystem Laurent Pinchart
2019-11-08 17:59 ` [PATCH v10 4/4] arm64: dts: zynqmp: zcu106-revA: Wire up the " Laurent Pinchart
2019-11-15 8:30 ` Michal Simek
2019-12-05 15:19 ` Laurent Pinchart [this message]
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