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* [PATCH v3 0/9] DP Phy compliance auto test
@ 2019-12-30 16:15 Animesh Manna
  2019-12-30 16:15 ` [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec Animesh Manna
                   ` (8 more replies)
  0 siblings, 9 replies; 19+ messages in thread
From: Animesh Manna @ 2019-12-30 16:15 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jani.nikula, nidhi1.gupta, Animesh Manna, manasi.d.navare,
	uma.shankar, anshuman.gupta

Driver changes mainly to process the request coming from Test equipment
as short pulse hpd interrupt to change link-pattern/v-swing/pre-emphasis
Complete auto test suite takes much lesser time than manual run.

Overall design:
--------------
Automate test request will come to source device as HDP short pulse
interrupt from test scope.
Read DPCD 0x201, Check for bit 1 for automated test request.
If set continue and read DPCD 0x218.
Check for bit 3 for phy test pattern, If set continue.
Get the requested test pattern through DPCD 0x248.
Compute requested voltage swing level and pre-emphasis level
from DPCD 0x206 and 0x207
Set signal level through vswing programming sequence.
Write DDI_COMP_CTL and DDI_COMP_PATx as per requested pattern.
Configure the link and write the new test pattern through DPCD.

High level patch description.
-----------------------------
patch 1: drm level api added to get/set test pattern as per vesa
DP spec. This maybe useful for other driver so added in drm layer.
patch 2: Fix for a compilation issue.
patch 3: vswing/preemphasis adjustment calculation is needed during
phy compliance request processing along with existing link training
process, so moved the same function in intel_dp.c.
patch 4: Parse the test scope request regarding  rquested test pattern,
vswing level, preemphasis level.
patch 5: Notify testapp through uevent.
patch 6: Added debugfs entry for phy compliance.
patch 7: Register difnition of DP compliance register added.
patch 8: Function added to update the pattern in source side.
patch 9: This patch os mainly processing the request.

Currently through prototyping patch able to run DP compliance where
vswing, preemphasis and test pattern is changing fine but complete
test is under process. As per feedback redesigned the code. Could not test
due to unavailability of test scope, so sending as RFC again to get design
feedback.

v1: Redesigned the code as per review feedback from Manasi on RFC.
v2: Addressed review comments from Manasi.
v3: Addressed review commnets from Harry, Ville, Jani.

Animesh Manna (9):
  drm/amd/display: Align macro name as per DP spec
  drm/dp: get/set phy compliance pattern
  drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
  drm/i915/dp: Preparation for DP phy compliance auto test
  drm/i915/dsb: Send uevent to testapp.
  drm/i915/dp: Add debugfs entry for DP phy compliance.
  drm/i915/dp: Register definition for DP compliance register
  drm/i915/dp: Update the pattern as per request
  drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern

 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |   2 +-
 drivers/gpu/drm/drm_dp_helper.c               |  94 +++++++++
 drivers/gpu/drm/i915/display/intel_display.c  |  24 ++-
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 197 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   6 +
 .../drm/i915/display/intel_dp_link_training.c |  36 +---
 drivers/gpu/drm/i915/i915_debugfs.c           |  12 +-
 drivers/gpu/drm/i915/i915_drv.h               |   2 +
 drivers/gpu/drm/i915/i915_reg.h               |  20 ++
 include/drm/drm_dp_helper.h                   |  33 ++-
 11 files changed, 387 insertions(+), 40 deletions(-)

-- 
2.24.0

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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec
  2019-12-30 16:15 [PATCH v3 0/9] DP Phy compliance auto test Animesh Manna
@ 2019-12-30 16:15 ` Animesh Manna
  2020-01-03 23:54   ` Manasi Navare
  2019-12-30 16:15 ` [PATCH v3 2/9] drm/dp: get/set phy compliance pattern Animesh Manna
                   ` (7 subsequent siblings)
  8 siblings, 1 reply; 19+ messages in thread
From: Animesh Manna @ 2019-12-30 16:15 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jani.nikula, nidhi1.gupta, Animesh Manna, manasi.d.navare,
	uma.shankar, anshuman.gupta, Alex Deucher

[Why]:
Aligh with DP spec wanted to follow same naming convention.

[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.

Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 include/drm/drm_dp_helper.h                      | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 42aa889fd0f5..1a6109be2fce 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 	/* get phy test pattern and pattern parameters from DP receiver */
 	core_link_read_dpcd(
 			link,
-			DP_TEST_PHY_PATTERN,
+			DP_PHY_TEST_PATTERN,
 			&dpcd_test_pattern.raw,
 			sizeof(dpcd_test_pattern));
 	core_link_read_dpcd(
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 8f8f3632e697..d6e560870fb1 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -699,7 +699,7 @@
 # define DP_TEST_CRC_SUPPORTED		    (1 << 5)
 # define DP_TEST_COUNT_MASK		    0xf
 
-#define DP_TEST_PHY_PATTERN                 0x248
+#define DP_PHY_TEST_PATTERN                 0x248
 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
-- 
2.24.0

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https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 2/9] drm/dp: get/set phy compliance pattern
  2019-12-30 16:15 [PATCH v3 0/9] DP Phy compliance auto test Animesh Manna
  2019-12-30 16:15 ` [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec Animesh Manna
@ 2019-12-30 16:15 ` Animesh Manna
  2019-12-30 16:15 ` [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
                   ` (6 subsequent siblings)
  8 siblings, 0 replies; 19+ messages in thread
From: Animesh Manna @ 2019-12-30 16:15 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jani.nikula, nidhi1.gupta, Animesh Manna, manasi.d.navare,
	uma.shankar, anshuman.gupta

During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.

v2: As per review feedback from Manasi on RFC version,
- added dp revision as function argument in set_phy_pattern api.
- used int for link_rate and u8 for lane_count to align with existing code.

v3: As per review feedback from Harry,
- used sizeof() instead of magic number.
- corrected kernel-doc for drm_dp_phy_test_params structure.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 94 +++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     | 31 +++++++++++
 2 files changed, 125 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2c7870aef469..8a0786dd262d 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1371,3 +1371,97 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
 	return num_bpc;
 }
 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+/**
+ * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data)
+{
+	int err;
+	u8 rate, lanes;
+
+	err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
+	if (err < 0)
+		return err;
+	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
+
+	err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
+	if (err < 0)
+		return err;
+	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
+
+	if (lanes & DP_ENHANCED_FRAME_CAP)
+		data->enhanced_frame_cap = true;
+
+	err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
+	if (err < 0)
+		return err;
+
+	switch (data->phy_pattern) {
+	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+		err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+				       &data->custom80, sizeof(data->custom80));
+		if (err < 0)
+			return err;
+
+		break;
+	case DP_PHY_TEST_PATTERN_CP2520:
+		err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
+				       &data->hbr2_reset,
+				       sizeof(data->hbr2_reset));
+		if (err < 0)
+			return err;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
+
+/**
+ * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data, u8 dp_rev)
+{
+	int err, i;
+	u8 link_config[2];
+	u8 test_pattern;
+
+	link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
+	link_config[1] = data->num_lanes;
+	if (data->enhanced_frame_cap)
+		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
+	if (err < 0)
+		return err;
+
+	test_pattern = data->phy_pattern;
+	if (dp_rev < 0x12) {
+		test_pattern = (test_pattern << 2) &
+			       DP_LINK_QUAL_PATTERN_11_MASK;
+		err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
+					 test_pattern);
+		if (err < 0)
+			return err;
+	} else {
+		for (i = 0; i < data->num_lanes; i++) {
+			err = drm_dp_dpcd_writeb(aux,
+						 DP_LINK_QUAL_LANE0_SET + i,
+						 test_pattern);
+			if (err < 0)
+				return err;
+		}
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index d6e560870fb1..3d0e9e0d55cf 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -700,6 +700,15 @@
 # define DP_TEST_COUNT_MASK		    0xf
 
 #define DP_PHY_TEST_PATTERN                 0x248
+# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
+# define DP_PHY_TEST_PATTERN_NONE           0x0
+# define DP_PHY_TEST_PATTERN_D10_2          0x1
+# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
+# define DP_PHY_TEST_PATTERN_PRBS7          0x3
+# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
+# define DP_PHY_TEST_PATTERN_CP2520         0x5
+
+#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
@@ -1570,4 +1579,26 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
 
 #endif
 
+/**
+ * struct drm_dp_phy_test_params - DP Phy Compliance parameters
+ * @link_rate: Requested Link rate from DPCD 0x219
+ * @num_lanes: Number of lanes requested by sing through DPCD 0x220
+ * @phy_pattern: DP Phy test pattern from DPCD 0x248
+ * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
+ * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
+ * @enhanced_frame_cap: flag for enhanced frame capability.
+ */
+struct drm_dp_phy_test_params {
+	int link_rate;
+	u8 num_lanes;
+	u8 phy_pattern;
+	u8 hbr2_reset[2];
+	u8 custom80[10];
+	bool enhanced_frame_cap;
+};
+
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data);
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data, u8 dp_rev);
 #endif /* _DRM_DP_HELPER_H_ */
-- 
2.24.0

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dri-devel@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
  2019-12-30 16:15 [PATCH v3 0/9] DP Phy compliance auto test Animesh Manna
  2019-12-30 16:15 ` [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec Animesh Manna
  2019-12-30 16:15 ` [PATCH v3 2/9] drm/dp: get/set phy compliance pattern Animesh Manna
@ 2019-12-30 16:15 ` Animesh Manna
  2020-01-02  9:18   ` Jani Nikula
  2019-12-30 16:15 ` [PATCH v3 4/9] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
                   ` (5 subsequent siblings)
  8 siblings, 1 reply; 19+ messages in thread
From: Animesh Manna @ 2019-12-30 16:15 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jani.nikula, nidhi1.gupta, Animesh Manna, manasi.d.navare,
	uma.shankar, anshuman.gupta

vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.

No functional change.

v1: initial patch.
v2:
- used "intel_dp" prefix in function name. (Jani)
- used array notation instead pointer for link_status. (Ville)

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       | 34 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h       |  4 +++
 .../drm/i915/display/intel_dp_link_training.c | 36 ++-----------------
 3 files changed, 40 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 991f343579ef..2a27ee106089 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4110,6 +4110,40 @@ ivb_cpu_edp_signal_levels(u8 train_set)
 	}
 }
 
+void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+			  const u8 link_status[DP_LINK_STATUS_SIZE])
+{
+	u8 v = 0;
+	u8 p = 0;
+	int lane;
+	u8 voltage_max;
+	u8 preemph_max;
+
+	for (lane = 0; lane < intel_dp->lane_count; lane++) {
+		u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
+							      lane);
+		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
+								   lane);
+
+		if (this_v > v)
+			v = this_v;
+		if (this_p > p)
+			p = this_p;
+	}
+
+	voltage_max = intel_dp_voltage_max(intel_dp);
+	if (v >= voltage_max)
+		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
+	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
+	if (p >= preemph_max)
+		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+	for (lane = 0; lane < 4; lane++)
+		intel_dp->train_set[lane] = v | p;
+}
+
 void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..83eadc87af26 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -9,6 +9,7 @@
 #include <linux/types.h>
 
 #include <drm/i915_drm.h>
+#include <drm/drm_dp_helper.h>
 
 #include "i915_reg.h"
 
@@ -91,6 +92,9 @@ void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 				       u8 dp_train_pat);
 void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+			  const u8 link_status[DP_LINK_STATUS_SIZE]);
+void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
 u8
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2a1130dd1ad0..e8ff9e279800 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
 		      link_status[3], link_status[4], link_status[5]);
 }
 
-static void
-intel_get_adjust_train(struct intel_dp *intel_dp,
-		       const u8 link_status[DP_LINK_STATUS_SIZE])
-{
-	u8 v = 0;
-	u8 p = 0;
-	int lane;
-	u8 voltage_max;
-	u8 preemph_max;
-
-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
-		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
-		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
-
-		if (this_v > v)
-			v = this_v;
-		if (this_p > p)
-			p = this_p;
-	}
-
-	voltage_max = intel_dp_voltage_max(intel_dp);
-	if (v >= voltage_max)
-		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
-
-	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
-	if (p >= preemph_max)
-		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
-	for (lane = 0; lane < 4; lane++)
-		intel_dp->train_set[lane] = v | p;
-}
-
 static bool
 intel_dp_set_link_train(struct intel_dp *intel_dp,
 			u8 dp_train_pat)
@@ -215,7 +183,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 
 		/* Update training set as requested by target */
-		intel_get_adjust_train(intel_dp, link_status);
+		intel_dp_get_adjust_train(intel_dp, link_status);
 		if (!intel_dp_update_link_train(intel_dp)) {
 			DRM_ERROR("failed to update link training\n");
 			return false;
@@ -325,7 +293,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 		}
 
 		/* Update training set as requested by target */
-		intel_get_adjust_train(intel_dp, link_status);
+		intel_dp_get_adjust_train(intel_dp, link_status);
 		if (!intel_dp_update_link_train(intel_dp)) {
 			DRM_ERROR("failed to update link training\n");
 			break;
-- 
2.24.0

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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 4/9] drm/i915/dp: Preparation for DP phy compliance auto test
  2019-12-30 16:15 [PATCH v3 0/9] DP Phy compliance auto test Animesh Manna
                   ` (2 preceding siblings ...)
  2019-12-30 16:15 ` [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
@ 2019-12-30 16:15 ` Animesh Manna
  2019-12-30 16:15 ` [PATCH v3 5/9] drm/i915/dsb: Send uevent to testapp Animesh Manna
                   ` (4 subsequent siblings)
  8 siblings, 0 replies; 19+ messages in thread
From: Animesh Manna @ 2019-12-30 16:15 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jani.nikula, nidhi1.gupta, Animesh Manna, manasi.d.navare,
	uma.shankar, anshuman.gupta

During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 24 +++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 630a94892b7b..32f0740e4569 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1208,6 +1208,7 @@ struct intel_dp_compliance_data {
 	u8 video_pattern;
 	u16 hdisplay, vdisplay;
 	u8 bpc;
+	struct drm_dp_phy_test_params phytest;
 };
 
 struct intel_dp_compliance {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2a27ee106089..fa67b8f88e65 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4986,9 +4986,33 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
 	return test_result;
 }
 
+static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
+{
+	struct drm_dp_phy_test_params *data =
+		&intel_dp->compliance.test_data.phytest;
+
+	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
+		DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
+		return DP_TEST_NAK;
+	}
+
+	/*
+	 * link_mst is set to false to avoid executing mst related code
+	 * during compliance testing.
+	 */
+	intel_dp->link_mst = false;
+
+	return DP_TEST_ACK;
+}
+
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
 	u8 test_result = DP_TEST_NAK;
+
+	test_result = intel_dp_prepare_phytest(intel_dp);
+	if (test_result != DP_TEST_ACK)
+		DRM_ERROR("Phy test preparation failed\n");
+
 	return test_result;
 }
 
-- 
2.24.0

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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 5/9] drm/i915/dsb: Send uevent to testapp.
  2019-12-30 16:15 [PATCH v3 0/9] DP Phy compliance auto test Animesh Manna
                   ` (3 preceding siblings ...)
  2019-12-30 16:15 ` [PATCH v3 4/9] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
@ 2019-12-30 16:15 ` Animesh Manna
  2019-12-30 16:15 ` [PATCH v3 6/9] drm/i915/dp: Add debugfs entry for DP phy compliance Animesh Manna
                   ` (3 subsequent siblings)
  8 siblings, 0 replies; 19+ messages in thread
From: Animesh Manna @ 2019-12-30 16:15 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jani.nikula, nidhi1.gupta, Animesh Manna, manasi.d.navare,
	uma.shankar, anshuman.gupta

Send uevent to testapp and set test_active flag. To align with link
compliance design existing intel_dp_compliance tool will be used to
get the phy request in userspace through uevent.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fa67b8f88e65..cbefda9b6204 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5013,6 +5013,9 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 	if (test_result != DP_TEST_ACK)
 		DRM_ERROR("Phy test preparation failed\n");
 
+	/* Set test active flag here so userspace doesn't interrupt things */
+	intel_dp->compliance.test_active = 1;
+
 	return test_result;
 }
 
@@ -5338,8 +5341,11 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
 
 	intel_psr_short_pulse(intel_dp);
 
-	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
-		DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
+	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING ||
+	    intel_dp->compliance.test_type ==
+	    DP_TEST_LINK_PHY_TEST_PATTERN) {
+		DRM_DEBUG_KMS("Compliance Test requested, test-type = 0x%lx\n",
+			      intel_dp->compliance.test_type);
 		/* Send a Hotplug Uevent to userspace to start modeset */
 		drm_kms_helper_hotplug_event(&dev_priv->drm);
 	}
-- 
2.24.0

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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 6/9] drm/i915/dp: Add debugfs entry for DP phy compliance.
  2019-12-30 16:15 [PATCH v3 0/9] DP Phy compliance auto test Animesh Manna
                   ` (4 preceding siblings ...)
  2019-12-30 16:15 ` [PATCH v3 5/9] drm/i915/dsb: Send uevent to testapp Animesh Manna
@ 2019-12-30 16:15 ` Animesh Manna
  2019-12-30 16:15 ` [PATCH v3 7/9] drm/i915/dp: Register definition for DP compliance register Animesh Manna
                   ` (2 subsequent siblings)
  8 siblings, 0 replies; 19+ messages in thread
From: Animesh Manna @ 2019-12-30 16:15 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jani.nikula, nidhi1.gupta, Animesh Manna, manasi.d.navare,
	uma.shankar, anshuman.gupta

These debugfs entry will help testapp to understand the test request
during dp phy compliance mode.

Acked-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0ac98e39eb75..a903ed0632cb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3177,6 +3177,16 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data)
 					   intel_dp->compliance.test_data.vdisplay);
 				seq_printf(m, "bpc: %u\n",
 					   intel_dp->compliance.test_data.bpc);
+			} else if (intel_dp->compliance.test_type ==
+				   DP_TEST_LINK_PHY_TEST_PATTERN) {
+				seq_printf(m, "pattern: %d\n",
+					   intel_dp->compliance.test_data.phytest.phy_pattern);
+				seq_printf(m, "Number of lanes: %d\n",
+					   intel_dp->compliance.test_data.phytest.num_lanes);
+				seq_printf(m, "Link Rate: %d\n",
+					   intel_dp->compliance.test_data.phytest.link_rate);
+				seq_printf(m, "level: %02x\n",
+					   intel_dp->train_set[0]);
 			}
 		} else
 			seq_puts(m, "0");
@@ -3209,7 +3219,7 @@ static int i915_displayport_test_type_show(struct seq_file *m, void *data)
 
 		if (encoder && connector->status == connector_status_connected) {
 			intel_dp = enc_to_intel_dp(&encoder->base);
-			seq_printf(m, "%02lx", intel_dp->compliance.test_type);
+			seq_printf(m, "%02lx\n", intel_dp->compliance.test_type);
 		} else
 			seq_puts(m, "0");
 	}
-- 
2.24.0

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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 7/9] drm/i915/dp: Register definition for DP compliance register
  2019-12-30 16:15 [PATCH v3 0/9] DP Phy compliance auto test Animesh Manna
                   ` (5 preceding siblings ...)
  2019-12-30 16:15 ` [PATCH v3 6/9] drm/i915/dp: Add debugfs entry for DP phy compliance Animesh Manna
@ 2019-12-30 16:15 ` Animesh Manna
  2019-12-30 16:15 ` [PATCH v3 8/9] drm/i915/dp: Update the pattern as per request Animesh Manna
  2019-12-30 16:15 ` [PATCH v3 9/9] drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern Animesh Manna
  8 siblings, 0 replies; 19+ messages in thread
From: Animesh Manna @ 2019-12-30 16:15 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jani.nikula, nidhi1.gupta, Animesh Manna, manasi.d.navare,
	uma.shankar, anshuman.gupta

DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 030a3f3e69af..a536d920324c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9794,6 +9794,26 @@ enum skl_power_gate {
 #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
 #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
 
+/* DDI DP Compliance Control */
+#define DDI_DP_COMP_CTL_A                      0x605F0
+#define DDI_DP_COMP_CTL_B                      0x615F0
+#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, \
+					 DDI_DP_COMP_CTL_B)
+#define  DDI_DP_COMP_CTL_ENABLE                        (1 << 31)
+#define  DDI_DP_COMP_CTL_D10_2                 (0 << 28)
+#define  DDI_DP_COMP_CTL_SCRAMBLED_0           (1 << 28)
+#define  DDI_DP_COMP_CTL_PRBS7                 (2 << 28)
+#define  DDI_DP_COMP_CTL_CUSTOM80                      (3 << 28)
+#define  DDI_DP_COMP_CTL_HBR2                  (4 << 28)
+#define  DDI_DP_COMP_CTL_SCRAMBLED_1           (5 << 28)
+#define  DDI_DP_COMP_CTL_HBR2_RESET            (0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A                      0x605F4
+#define DDI_DP_COMP_PAT_B                      0x615F4
+#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, \
+					     DDI_DP_COMP_PAT_B) + (i) * 4)
+
 /* Sideband Interface (SBI) is programmed indirectly, via
  * SBI_ADDR, which contains the register offset; and SBI_DATA,
  * which contains the payload */
-- 
2.24.0

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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 8/9] drm/i915/dp: Update the pattern as per request
  2019-12-30 16:15 [PATCH v3 0/9] DP Phy compliance auto test Animesh Manna
                   ` (6 preceding siblings ...)
  2019-12-30 16:15 ` [PATCH v3 7/9] drm/i915/dp: Register definition for DP compliance register Animesh Manna
@ 2019-12-30 16:15 ` Animesh Manna
  2020-01-02  9:23   ` [Intel-gfx] " Jani Nikula
  2019-12-30 16:15 ` [PATCH v3 9/9] drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern Animesh Manna
  8 siblings, 1 reply; 19+ messages in thread
From: Animesh Manna @ 2019-12-30 16:15 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jani.nikula, nidhi1.gupta, Animesh Manna, manasi.d.navare,
	uma.shankar, anshuman.gupta

As per request from DP phy compliance test few special
test pattern need to set by source. Added function
to set pattern in DP_COMP_CTL register. It will be
called along with other test parameters like vswing,
pre-emphasis programming in atomic_commit_tail path.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cbefda9b6204..7c3f65e5d88b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5005,6 +5005,61 @@ static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
 	return DP_TEST_ACK;
 }
 
+static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv =
+			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_dp_phy_test_params *data =
+			&intel_dp->compliance.test_data.phytest;
+	u32 temp;
+
+	switch (data->phy_pattern) {
+	case DP_PHY_TEST_PATTERN_NONE:
+		DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), 0x0);
+		break;
+	case DP_PHY_TEST_PATTERN_D10_2:
+		DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
+		break;
+	case DP_PHY_TEST_PATTERN_ERROR_COUNT:
+		DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE |
+			   DDI_DP_COMP_CTL_SCRAMBLED_0);
+		break;
+	case DP_PHY_TEST_PATTERN_PRBS7:
+		DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
+		break;
+	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+		DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern\n");
+		temp = ((data->custom80[0] << 24) | (data->custom80[1] << 16) |
+			(data->custom80[2] << 8) | (data->custom80[3]));
+		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 0), temp);
+		temp = ((data->custom80[4] << 24) | (data->custom80[5] << 16) |
+			(data->custom80[6] << 8) | (data->custom80[7]));
+		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 1), temp);
+		temp = ((data->custom80[8] << 8) | data->custom80[9]);
+		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 2), temp);
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80);
+		break;
+	case DP_PHY_TEST_PATTERN_CP2520:
+		DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
+		temp = ((data->hbr2_reset[1] << 8) | data->hbr2_reset[0]);
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
+			   temp);
+		break;
+	default:
+		WARN(1, "Invalid Phy Test PAttern\n");
+	}
+}
+
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
 	u8 test_result = DP_TEST_NAK;
-- 
2.24.0

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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 9/9] drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern
  2019-12-30 16:15 [PATCH v3 0/9] DP Phy compliance auto test Animesh Manna
                   ` (7 preceding siblings ...)
  2019-12-30 16:15 ` [PATCH v3 8/9] drm/i915/dp: Update the pattern as per request Animesh Manna
@ 2019-12-30 16:15 ` Animesh Manna
  8 siblings, 0 replies; 19+ messages in thread
From: Animesh Manna @ 2019-12-30 16:15 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jani.nikula, nidhi1.gupta, Animesh Manna, manasi.d.navare,
	uma.shankar, anshuman.gupta

This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.

Note: FIXME tag added as design discusion is ongoing in previous patch
series. Some temporary fix added and the patch is under-development, not for
review.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 24 ++++++-
 drivers/gpu/drm/i915/display/intel_dp.c      | 74 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h      |  2 +
 drivers/gpu/drm/i915/i915_drv.h              |  2 +
 4 files changed, 101 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index da5266e76738..c00be1eb67d6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14480,6 +14480,9 @@ static int intel_atomic_check(struct drm_device *dev,
 	int ret, i;
 	bool any_ms = false;
 
+	if (dev_priv->dp_phy_comp)
+		return 0;
+
 	/* Catch I915_MODE_FLAG_INHERITED */
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
@@ -15207,10 +15210,23 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_crtc *crtc;
+	const struct drm_connector_state *conn_state;
+	struct drm_connector *conn;
 	u64 put_domains[I915_MAX_PIPES] = {};
 	intel_wakeref_t wakeref = 0;
 	int i;
 
+	if(dev_priv->dp_phy_comp) {
+		for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
+			struct intel_encoder *encoder =
+				to_intel_encoder(conn_state->best_encoder);
+			struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+			intel_dp_process_phy_request(intel_dp);
+		}
+		goto dp_phy_comp1;
+	}
+
 	intel_atomic_commit_fence_wait(state);
 
 	drm_atomic_helper_wait_for_dependencies(&state->base);
@@ -15345,6 +15361,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	if (state->modeset && intel_can_enable_sagv(state))
 		intel_enable_sagv(dev_priv);
 
+dp_phy_comp1:
 	drm_atomic_helper_commit_hw_done(&state->base);
 
 	if (state->modeset) {
@@ -15436,6 +15453,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
 	drm_atomic_state_get(&state->base);
+	if (!dev_priv->dp_phy_comp) {
 	i915_sw_fence_init(&state->commit_ready,
 			   intel_atomic_commit_ready);
 
@@ -15474,11 +15492,13 @@ static int intel_atomic_commit(struct drm_device *dev,
 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
 		return ret;
 	}
+	}
 
 	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
 	if (!ret)
 		ret = drm_atomic_helper_swap_state(&state->base, true);
 
+	if (!dev_priv->dp_phy_comp) {
 	if (ret) {
 		i915_sw_fence_commit(&state->commit_ready);
 
@@ -15489,6 +15509,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 	dev_priv->wm.distrust_bios_wm = false;
 	intel_shared_dpll_swap_state(state);
 	intel_atomic_track_fbs(state);
+	}
 
 	if (state->global_state_changed) {
 		assert_global_state_locked(dev_priv);
@@ -15505,8 +15526,9 @@ static int intel_atomic_commit(struct drm_device *dev,
 
 	drm_atomic_state_get(&state->base);
 	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
-
+	if (!dev_priv->dp_phy_comp) {
 	i915_sw_fence_commit(&state->commit_ready);
+	}
 	if (nonblock && state->modeset) {
 		queue_work(dev_priv->modeset_wq, &state->base.commit_work);
 	} else if (nonblock) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7c3f65e5d88b..c3454053a212 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5060,9 +5060,82 @@ static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
 	}
 }
 
+static void
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	enum port port = intel_dig_port->base.port;
+	u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+	ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+	dp_tp_ctl_value = I915_READ(TGL_DP_TP_CTL(port));
+	trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+	ddi_buf_ctl_value        &= ~(DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH_MASK);
+	dp_tp_ctl_value          &= ~DP_TP_CTL_ENABLE;
+	trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
+				      DDI_PORT_WIDTH_MASK);
+
+	I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+	I915_WRITE(TGL_DP_TP_CTL(port), dp_tp_ctl_value);
+	I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+}
+
+static void
+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	enum port port = intel_dig_port->base.port;
+	u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+	ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+	dp_tp_ctl_value = I915_READ(TGL_DP_TP_CTL(port));
+	trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+	ddi_buf_ctl_value |= DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH(lane_cnt);
+	dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
+	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
+				    DDI_PORT_WIDTH(lane_cnt);
+
+	I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+	I915_WRITE(TGL_DP_TP_CTL(port), dp_tp_ctl_value);
+	I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+}
+
+void intel_dp_process_phy_request(struct intel_dp *intel_dp)
+{
+	struct drm_dp_phy_test_params *data =
+		&intel_dp->compliance.test_data.phytest;
+	u8 link_status[DP_LINK_STATUS_SIZE];
+
+	if (!intel_dp_get_link_status(intel_dp, link_status)) {
+		DRM_DEBUG_KMS("failed to get link status\n");
+		return;
+	}
+
+	/* retrieve vswing & pre-emphasis setting */
+	intel_dp_get_adjust_train(intel_dp, link_status);
+
+	intel_dp_autotest_phy_ddi_disable(intel_dp);
+
+	intel_dp_set_signal_levels(intel_dp);
+
+	intel_dp_phy_pattern_update(intel_dp);
+
+	intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
+
+	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
+				    link_status[DP_DPCD_REV]);
+}
+
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
 	u8 test_result = DP_TEST_NAK;
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
 	test_result = intel_dp_prepare_phytest(intel_dp);
 	if (test_result != DP_TEST_ACK)
@@ -5070,6 +5143,7 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 
 	/* Set test active flag here so userspace doesn't interrupt things */
 	intel_dp->compliance.test_active = 1;
+	dev_priv->dp_phy_comp = true;
 
 	return test_result;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 83eadc87af26..65e4a01a4199 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -121,6 +121,8 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
 				  const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
+void intel_dp_process_phy_request(struct intel_dp *intel_dp);
+
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
 {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b7f122dccdca..b5839db97c1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1283,6 +1283,8 @@ struct drm_i915_private {
 
 	I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
 
+	bool dp_phy_comp;
+
 	/*
 	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
 	 * will be rejected. Instead look for a better place.
-- 
2.24.0

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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
  2019-12-30 16:15 ` [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
@ 2020-01-02  9:18   ` Jani Nikula
  2020-01-02 10:26     ` Manna, Animesh
  0 siblings, 1 reply; 19+ messages in thread
From: Jani Nikula @ 2020-01-02  9:18 UTC (permalink / raw)
  To: Animesh Manna, intel-gfx, dri-devel
  Cc: manasi.d.navare, nidhi1.gupta, Animesh Manna, uma.shankar,
	anshuman.gupta

On Mon, 30 Dec 2019, Animesh Manna <animesh.manna@intel.com> wrote:
> vswing/pre-emphasis adjustment calculation is needed in processing
> of auto phy compliance request other than link training, so moved
> the same function in intel_dp.c.

I guess I'm still asking why you think this is better located in
intel_dp.c than intel_dp_link_training.c, as the function has been moved
once in the other direction already to split out stuff from intel_dp.c
and to make the file smaller. Even the file name suggests it should
really be in intel_dp_link_training.c, right?

BR,
Jani.


>
> No functional change.
>
> v1: initial patch.
> v2:
> - used "intel_dp" prefix in function name. (Jani)
> - used array notation instead pointer for link_status. (Ville)
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c       | 34 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h       |  4 +++
>  .../drm/i915/display/intel_dp_link_training.c | 36 ++-----------------
>  3 files changed, 40 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 991f343579ef..2a27ee106089 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4110,6 +4110,40 @@ ivb_cpu_edp_signal_levels(u8 train_set)
>  	}
>  }
>  
> +void
> +intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> +			  const u8 link_status[DP_LINK_STATUS_SIZE])
> +{
> +	u8 v = 0;
> +	u8 p = 0;
> +	int lane;
> +	u8 voltage_max;
> +	u8 preemph_max;
> +
> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> +		u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
> +							      lane);
> +		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
> +								   lane);
> +
> +		if (this_v > v)
> +			v = this_v;
> +		if (this_p > p)
> +			p = this_p;
> +	}
> +
> +	voltage_max = intel_dp_voltage_max(intel_dp);
> +	if (v >= voltage_max)
> +		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> +
> +	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> +	if (p >= preemph_max)
> +		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> +
> +	for (lane = 0; lane < 4; lane++)
> +		intel_dp->train_set[lane] = v | p;
> +}
> +
>  void
>  intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 3da166054788..83eadc87af26 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -9,6 +9,7 @@
>  #include <linux/types.h>
>  
>  #include <drm/i915_drm.h>
> +#include <drm/drm_dp_helper.h>
>  
>  #include "i915_reg.h"
>  
> @@ -91,6 +92,9 @@ void
>  intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>  				       u8 dp_train_pat);
>  void
> +intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> +			  const u8 link_status[DP_LINK_STATUS_SIZE]);
> +void
>  intel_dp_set_signal_levels(struct intel_dp *intel_dp);
>  void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
>  u8
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 2a1130dd1ad0..e8ff9e279800 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>  		      link_status[3], link_status[4], link_status[5]);
>  }
>  
> -static void
> -intel_get_adjust_train(struct intel_dp *intel_dp,
> -		       const u8 link_status[DP_LINK_STATUS_SIZE])
> -{
> -	u8 v = 0;
> -	u8 p = 0;
> -	int lane;
> -	u8 voltage_max;
> -	u8 preemph_max;
> -
> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> -		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> -		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> -
> -		if (this_v > v)
> -			v = this_v;
> -		if (this_p > p)
> -			p = this_p;
> -	}
> -
> -	voltage_max = intel_dp_voltage_max(intel_dp);
> -	if (v >= voltage_max)
> -		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> -
> -	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> -	if (p >= preemph_max)
> -		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> -
> -	for (lane = 0; lane < 4; lane++)
> -		intel_dp->train_set[lane] = v | p;
> -}
> -
>  static bool
>  intel_dp_set_link_train(struct intel_dp *intel_dp,
>  			u8 dp_train_pat)
> @@ -215,7 +183,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>  		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
>  
>  		/* Update training set as requested by target */
> -		intel_get_adjust_train(intel_dp, link_status);
> +		intel_dp_get_adjust_train(intel_dp, link_status);
>  		if (!intel_dp_update_link_train(intel_dp)) {
>  			DRM_ERROR("failed to update link training\n");
>  			return false;
> @@ -325,7 +293,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>  		}
>  
>  		/* Update training set as requested by target */
> -		intel_get_adjust_train(intel_dp, link_status);
> +		intel_dp_get_adjust_train(intel_dp, link_status);
>  		if (!intel_dp_update_link_train(intel_dp)) {
>  			DRM_ERROR("failed to update link training\n");
>  			break;

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [Intel-gfx] [PATCH v3 8/9] drm/i915/dp: Update the pattern as per request
  2019-12-30 16:15 ` [PATCH v3 8/9] drm/i915/dp: Update the pattern as per request Animesh Manna
@ 2020-01-02  9:23   ` " Jani Nikula
  2020-01-03 23:51     ` Manasi Navare
  0 siblings, 1 reply; 19+ messages in thread
From: Jani Nikula @ 2020-01-02  9:23 UTC (permalink / raw)
  To: Animesh Manna, intel-gfx, dri-devel; +Cc: nidhi1.gupta

On Mon, 30 Dec 2019, Animesh Manna <animesh.manna@intel.com> wrote:
> As per request from DP phy compliance test few special
> test pattern need to set by source. Added function
> to set pattern in DP_COMP_CTL register. It will be
> called along with other test parameters like vswing,
> pre-emphasis programming in atomic_commit_tail path.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++++++++++++
>  1 file changed, 55 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index cbefda9b6204..7c3f65e5d88b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5005,6 +5005,61 @@ static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
>  	return DP_TEST_ACK;
>  }
>  
> +static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)

As a general rule, please only use the inline keyword for static inlines
in headers. Sometimes, it's useful in small helpers, but usually you
should just let the compiler decide what gets inlined.

In this case, the inline probably just hides the compiler warning about
the unused function.

BR,
Jani.

> +{
> +	struct drm_i915_private *dev_priv =
> +			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_dp_phy_test_params *data =
> +			&intel_dp->compliance.test_data.phytest;
> +	u32 temp;
> +
> +	switch (data->phy_pattern) {
> +	case DP_PHY_TEST_PATTERN_NONE:
> +		DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
> +		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), 0x0);
> +		break;
> +	case DP_PHY_TEST_PATTERN_D10_2:
> +		DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
> +		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> +			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
> +		break;
> +	case DP_PHY_TEST_PATTERN_ERROR_COUNT:
> +		DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
> +		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> +			   DDI_DP_COMP_CTL_ENABLE |
> +			   DDI_DP_COMP_CTL_SCRAMBLED_0);
> +		break;
> +	case DP_PHY_TEST_PATTERN_PRBS7:
> +		DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
> +		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> +			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
> +		break;
> +	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
> +		DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern\n");
> +		temp = ((data->custom80[0] << 24) | (data->custom80[1] << 16) |
> +			(data->custom80[2] << 8) | (data->custom80[3]));
> +		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 0), temp);
> +		temp = ((data->custom80[4] << 24) | (data->custom80[5] << 16) |
> +			(data->custom80[6] << 8) | (data->custom80[7]));
> +		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 1), temp);
> +		temp = ((data->custom80[8] << 8) | data->custom80[9]);
> +		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 2), temp);
> +		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> +			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80);
> +		break;
> +	case DP_PHY_TEST_PATTERN_CP2520:
> +		DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
> +		temp = ((data->hbr2_reset[1] << 8) | data->hbr2_reset[0]);
> +		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> +			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
> +			   temp);
> +		break;
> +	default:
> +		WARN(1, "Invalid Phy Test PAttern\n");
> +	}
> +}
> +
>  static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
>  {
>  	u8 test_result = DP_TEST_NAK;

-- 
Jani Nikula, Intel Open Source Graphics Center
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dri-devel@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
  2020-01-02  9:18   ` Jani Nikula
@ 2020-01-02 10:26     ` Manna, Animesh
  2020-01-03 23:48       ` Manasi Navare
  0 siblings, 1 reply; 19+ messages in thread
From: Manna, Animesh @ 2020-01-02 10:26 UTC (permalink / raw)
  To: Jani Nikula, intel-gfx, dri-devel
  Cc: manasi.d.navare, nidhi1.gupta, uma.shankar, anshuman.gupta

On 02-01-2020 14:48, Jani Nikula wrote:
> On Mon, 30 Dec 2019, Animesh Manna <animesh.manna@intel.com> wrote:
>> vswing/pre-emphasis adjustment calculation is needed in processing
>> of auto phy compliance request other than link training, so moved
>> the same function in intel_dp.c.
> I guess I'm still asking why you think this is better located in
> intel_dp.c than intel_dp_link_training.c, as the function has been moved
> once in the other direction already to split out stuff from intel_dp.c
> and to make the file smaller. Even the file name suggests it should
> really be in intel_dp_link_training.c, right?

Just a thought, can we change the name to "intel_dp_link_config.c" from "intel_dp_link_training.c" which will provide little wider scope
and all the function playing with link configuration can be under it and also exposed through header file.

AFAIK, processing phy compliance request always do not need link training. I understood link training is very specific process consisting of clock recovery + channel eq.
So I am afraid of exposing intel_get_adjust_train() from intel_dp_link_training.c which is not only specific to link-training. Need your suggestion.

Regards,
Animesh

>
> BR,
> Jani.
>
>
>> No functional change.
>>
>> v1: initial patch.
>> v2:
>> - used "intel_dp" prefix in function name. (Jani)
>> - used array notation instead pointer for link_status. (Ville)
>>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c       | 34 ++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dp.h       |  4 +++
>>   .../drm/i915/display/intel_dp_link_training.c | 36 ++-----------------
>>   3 files changed, 40 insertions(+), 34 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 991f343579ef..2a27ee106089 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4110,6 +4110,40 @@ ivb_cpu_edp_signal_levels(u8 train_set)
>>   	}
>>   }
>>   
>> +void
>> +intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>> +			  const u8 link_status[DP_LINK_STATUS_SIZE])
>> +{
>> +	u8 v = 0;
>> +	u8 p = 0;
>> +	int lane;
>> +	u8 voltage_max;
>> +	u8 preemph_max;
>> +
>> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> +		u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
>> +							      lane);
>> +		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
>> +								   lane);
>> +
>> +		if (this_v > v)
>> +			v = this_v;
>> +		if (this_p > p)
>> +			p = this_p;
>> +	}
>> +
>> +	voltage_max = intel_dp_voltage_max(intel_dp);
>> +	if (v >= voltage_max)
>> +		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>> +
>> +	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
>> +	if (p >= preemph_max)
>> +		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>> +
>> +	for (lane = 0; lane < 4; lane++)
>> +		intel_dp->train_set[lane] = v | p;
>> +}
>> +
>>   void
>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>>   {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index 3da166054788..83eadc87af26 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -9,6 +9,7 @@
>>   #include <linux/types.h>
>>   
>>   #include <drm/i915_drm.h>
>> +#include <drm/drm_dp_helper.h>
>>   
>>   #include "i915_reg.h"
>>   
>> @@ -91,6 +92,9 @@ void
>>   intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>>   				       u8 dp_train_pat);
>>   void
>> +intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>> +			  const u8 link_status[DP_LINK_STATUS_SIZE]);
>> +void
>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp);
>>   void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
>>   u8
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 2a1130dd1ad0..e8ff9e279800 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>>   		      link_status[3], link_status[4], link_status[5]);
>>   }
>>   
>> -static void
>> -intel_get_adjust_train(struct intel_dp *intel_dp,
>> -		       const u8 link_status[DP_LINK_STATUS_SIZE])
>> -{
>> -	u8 v = 0;
>> -	u8 p = 0;
>> -	int lane;
>> -	u8 voltage_max;
>> -	u8 preemph_max;
>> -
>> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> -		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>> -		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>> -
>> -		if (this_v > v)
>> -			v = this_v;
>> -		if (this_p > p)
>> -			p = this_p;
>> -	}
>> -
>> -	voltage_max = intel_dp_voltage_max(intel_dp);
>> -	if (v >= voltage_max)
>> -		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>> -
>> -	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
>> -	if (p >= preemph_max)
>> -		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>> -
>> -	for (lane = 0; lane < 4; lane++)
>> -		intel_dp->train_set[lane] = v | p;
>> -}
>> -
>>   static bool
>>   intel_dp_set_link_train(struct intel_dp *intel_dp,
>>   			u8 dp_train_pat)
>> @@ -215,7 +183,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>>   		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
>>   
>>   		/* Update training set as requested by target */
>> -		intel_get_adjust_train(intel_dp, link_status);
>> +		intel_dp_get_adjust_train(intel_dp, link_status);
>>   		if (!intel_dp_update_link_train(intel_dp)) {
>>   			DRM_ERROR("failed to update link training\n");
>>   			return false;
>> @@ -325,7 +293,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>>   		}
>>   
>>   		/* Update training set as requested by target */
>> -		intel_get_adjust_train(intel_dp, link_status);
>> +		intel_dp_get_adjust_train(intel_dp, link_status);
>>   		if (!intel_dp_update_link_train(intel_dp)) {
>>   			DRM_ERROR("failed to update link training\n");
>>   			break;
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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
  2020-01-02 10:26     ` Manna, Animesh
@ 2020-01-03 23:48       ` Manasi Navare
  2020-01-06 10:02         ` Manna, Animesh
  0 siblings, 1 reply; 19+ messages in thread
From: Manasi Navare @ 2020-01-03 23:48 UTC (permalink / raw)
  To: Manna, Animesh
  Cc: Jani Nikula, nidhi1.gupta, intel-gfx, dri-devel, uma.shankar,
	anshuman.gupta

On Thu, Jan 02, 2020 at 03:56:09PM +0530, Manna, Animesh wrote:
> On 02-01-2020 14:48, Jani Nikula wrote:
> >On Mon, 30 Dec 2019, Animesh Manna <animesh.manna@intel.com> wrote:
> >>vswing/pre-emphasis adjustment calculation is needed in processing
> >>of auto phy compliance request other than link training, so moved
> >>the same function in intel_dp.c.
> >I guess I'm still asking why you think this is better located in
> >intel_dp.c than intel_dp_link_training.c, as the function has been moved
> >once in the other direction already to split out stuff from intel_dp.c
> >and to make the file smaller. Even the file name suggests it should
> >really be in intel_dp_link_training.c, right?
> 
> Just a thought, can we change the name to "intel_dp_link_config.c" from "intel_dp_link_training.c" which will provide little wider scope
> and all the function playing with link configuration can be under it and also exposed through header file.
> 
> AFAIK, processing phy compliance request always do not need link training. I understood link training is very specific process consisting of clock recovery + channel eq.
> So I am afraid of exposing intel_get_adjust_train() from intel_dp_link_training.c which is not only specific to link-training. Need your suggestion.
> 
> Regards,
> Animesh
>

I agree with Jani here and I think I had even suggested this earlier that instead of moving this function to intel_dp.c
we should make it non static so it can be used even for PHY compliance but since this function still deals
with adjusting training patterns IMHO it should still stay in intel_dp_link_training.c

Manasi
 
> >
> >BR,
> >Jani.
> >
> >
> >>No functional change.
> >>
> >>v1: initial patch.
> >>v2:
> >>- used "intel_dp" prefix in function name. (Jani)
> >>- used array notation instead pointer for link_status. (Ville)
> >>
> >>Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >>---
> >>  drivers/gpu/drm/i915/display/intel_dp.c       | 34 ++++++++++++++++++
> >>  drivers/gpu/drm/i915/display/intel_dp.h       |  4 +++
> >>  .../drm/i915/display/intel_dp_link_training.c | 36 ++-----------------
> >>  3 files changed, 40 insertions(+), 34 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >>index 991f343579ef..2a27ee106089 100644
> >>--- a/drivers/gpu/drm/i915/display/intel_dp.c
> >>+++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >>@@ -4110,6 +4110,40 @@ ivb_cpu_edp_signal_levels(u8 train_set)
> >>  	}
> >>  }
> >>+void
> >>+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> >>+			  const u8 link_status[DP_LINK_STATUS_SIZE])
> >>+{
> >>+	u8 v = 0;
> >>+	u8 p = 0;
> >>+	int lane;
> >>+	u8 voltage_max;
> >>+	u8 preemph_max;
> >>+
> >>+	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> >>+		u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
> >>+							      lane);
> >>+		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
> >>+								   lane);
> >>+
> >>+		if (this_v > v)
> >>+			v = this_v;
> >>+		if (this_p > p)
> >>+			p = this_p;
> >>+	}
> >>+
> >>+	voltage_max = intel_dp_voltage_max(intel_dp);
> >>+	if (v >= voltage_max)
> >>+		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> >>+
> >>+	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> >>+	if (p >= preemph_max)
> >>+		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> >>+
> >>+	for (lane = 0; lane < 4; lane++)
> >>+		intel_dp->train_set[lane] = v | p;
> >>+}
> >>+
> >>  void
> >>  intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> >>  {
> >>diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> >>index 3da166054788..83eadc87af26 100644
> >>--- a/drivers/gpu/drm/i915/display/intel_dp.h
> >>+++ b/drivers/gpu/drm/i915/display/intel_dp.h
> >>@@ -9,6 +9,7 @@
> >>  #include <linux/types.h>
> >>  #include <drm/i915_drm.h>
> >>+#include <drm/drm_dp_helper.h>
> >>  #include "i915_reg.h"
> >>@@ -91,6 +92,9 @@ void
> >>  intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> >>  				       u8 dp_train_pat);
> >>  void
> >>+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> >>+			  const u8 link_status[DP_LINK_STATUS_SIZE]);
> >>+void
> >>  intel_dp_set_signal_levels(struct intel_dp *intel_dp);
> >>  void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
> >>  u8
> >>diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >>index 2a1130dd1ad0..e8ff9e279800 100644
> >>--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >>+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >>@@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
> >>  		      link_status[3], link_status[4], link_status[5]);
> >>  }
> >>-static void
> >>-intel_get_adjust_train(struct intel_dp *intel_dp,
> >>-		       const u8 link_status[DP_LINK_STATUS_SIZE])
> >>-{
> >>-	u8 v = 0;
> >>-	u8 p = 0;
> >>-	int lane;
> >>-	u8 voltage_max;
> >>-	u8 preemph_max;
> >>-
> >>-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> >>-		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> >>-		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> >>-
> >>-		if (this_v > v)
> >>-			v = this_v;
> >>-		if (this_p > p)
> >>-			p = this_p;
> >>-	}
> >>-
> >>-	voltage_max = intel_dp_voltage_max(intel_dp);
> >>-	if (v >= voltage_max)
> >>-		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> >>-
> >>-	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> >>-	if (p >= preemph_max)
> >>-		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> >>-
> >>-	for (lane = 0; lane < 4; lane++)
> >>-		intel_dp->train_set[lane] = v | p;
> >>-}
> >>-
> >>  static bool
> >>  intel_dp_set_link_train(struct intel_dp *intel_dp,
> >>  			u8 dp_train_pat)
> >>@@ -215,7 +183,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> >>  		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
> >>  		/* Update training set as requested by target */
> >>-		intel_get_adjust_train(intel_dp, link_status);
> >>+		intel_dp_get_adjust_train(intel_dp, link_status);
> >>  		if (!intel_dp_update_link_train(intel_dp)) {
> >>  			DRM_ERROR("failed to update link training\n");
> >>  			return false;
> >>@@ -325,7 +293,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
> >>  		}
> >>  		/* Update training set as requested by target */
> >>-		intel_get_adjust_train(intel_dp, link_status);
> >>+		intel_dp_get_adjust_train(intel_dp, link_status);
> >>  		if (!intel_dp_update_link_train(intel_dp)) {
> >>  			DRM_ERROR("failed to update link training\n");
> >>  			break;
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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [Intel-gfx] [PATCH v3 8/9] drm/i915/dp: Update the pattern as per request
  2020-01-02  9:23   ` [Intel-gfx] " Jani Nikula
@ 2020-01-03 23:51     ` Manasi Navare
  0 siblings, 0 replies; 19+ messages in thread
From: Manasi Navare @ 2020-01-03 23:51 UTC (permalink / raw)
  To: Jani Nikula; +Cc: nidhi1.gupta, Animesh Manna, intel-gfx, dri-devel

On Thu, Jan 02, 2020 at 11:23:14AM +0200, Jani Nikula wrote:
> On Mon, 30 Dec 2019, Animesh Manna <animesh.manna@intel.com> wrote:
> > As per request from DP phy compliance test few special
> > test pattern need to set by source. Added function
> > to set pattern in DP_COMP_CTL register. It will be
> > called along with other test parameters like vswing,
> > pre-emphasis programming in atomic_commit_tail path.
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++++++++++++
> >  1 file changed, 55 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index cbefda9b6204..7c3f65e5d88b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5005,6 +5005,61 @@ static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
> >  	return DP_TEST_ACK;
> >  }
> >  
> > +static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> 
> As a general rule, please only use the inline keyword for static inlines
> in headers. Sometimes, it's useful in small helpers, but usually you
> should just let the compiler decide what gets inlined.
> 
> In this case, the inline probably just hides the compiler warning about
> the unused function.
> 
> BR,
> Jani.
>

Yes I completely agree with Jani here, please do not use inline
other than some one line helpers in header files.
 
> > +{
> > +	struct drm_i915_private *dev_priv =
> > +			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
> > +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > +	struct drm_dp_phy_test_params *data =
> > +			&intel_dp->compliance.test_data.phytest;
> > +	u32 temp;
> > +
> > +	switch (data->phy_pattern) {
> > +	case DP_PHY_TEST_PATTERN_NONE:
> > +		DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
> > +		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), 0x0);
> > +		break;
> > +	case DP_PHY_TEST_PATTERN_D10_2:
> > +		DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
> > +		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> > +			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
> > +		break;
> > +	case DP_PHY_TEST_PATTERN_ERROR_COUNT:
> > +		DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
> > +		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> > +			   DDI_DP_COMP_CTL_ENABLE |
> > +			   DDI_DP_COMP_CTL_SCRAMBLED_0);
> > +		break;
> > +	case DP_PHY_TEST_PATTERN_PRBS7:
> > +		DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
> > +		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> > +			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
> > +		break;
> > +	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
> > +		DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern\n");
> > +		temp = ((data->custom80[0] << 24) | (data->custom80[1] << 16) |
> > +			(data->custom80[2] << 8) | (data->custom80[3]));
> > +		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 0), temp);
> > +		temp = ((data->custom80[4] << 24) | (data->custom80[5] << 16) |
> > +			(data->custom80[6] << 8) | (data->custom80[7]));
> > +		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 1), temp);
> > +		temp = ((data->custom80[8] << 8) | data->custom80[9]);
> > +		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 2), temp);
> > +		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> > +			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80);
> > +		break;
> > +	case DP_PHY_TEST_PATTERN_CP2520:
> > +		DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
> > +		temp = ((data->hbr2_reset[1] << 8) | data->hbr2_reset[0]);
> > +		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> > +			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
> > +			   temp);
> > +		break;
> > +	default:
> > +		WARN(1, "Invalid Phy Test PAttern\n");

Small nit here, it should be PHY Pattern

Manasi

> > +	}
> > +}
> > +
> >  static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
> >  {
> >  	u8 test_result = DP_TEST_NAK;
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec
  2019-12-30 16:15 ` [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec Animesh Manna
@ 2020-01-03 23:54   ` Manasi Navare
  2020-01-06 23:05     ` Alex Deucher
  0 siblings, 1 reply; 19+ messages in thread
From: Manasi Navare @ 2020-01-03 23:54 UTC (permalink / raw)
  To: Animesh Manna
  Cc: jani.nikula, nidhi1.gupta, intel-gfx, dri-devel, uma.shankar,
	anshuman.gupta, Alex Deucher

Harry, Jani - Since this also updates the AMD driver file, should this be merged through
AMD tree and then backmerged to drm-misc ?

Manasi

On Mon, Dec 30, 2019 at 09:45:15PM +0530, Animesh Manna wrote:
> [Why]:
> Aligh with DP spec wanted to follow same naming convention.
> 
> [How]:
> Changed the macro name of the dpcd address used for getting requested
> test-pattern.
> 
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
>  include/drm/drm_dp_helper.h                      | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 42aa889fd0f5..1a6109be2fce 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
>  	/* get phy test pattern and pattern parameters from DP receiver */
>  	core_link_read_dpcd(
>  			link,
> -			DP_TEST_PHY_PATTERN,
> +			DP_PHY_TEST_PATTERN,
>  			&dpcd_test_pattern.raw,
>  			sizeof(dpcd_test_pattern));
>  	core_link_read_dpcd(
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 8f8f3632e697..d6e560870fb1 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -699,7 +699,7 @@
>  # define DP_TEST_CRC_SUPPORTED		    (1 << 5)
>  # define DP_TEST_COUNT_MASK		    0xf
>  
> -#define DP_TEST_PHY_PATTERN                 0x248
> +#define DP_PHY_TEST_PATTERN                 0x248
>  #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
>  #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
>  #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
> -- 
> 2.24.0
> 
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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
  2020-01-03 23:48       ` Manasi Navare
@ 2020-01-06 10:02         ` Manna, Animesh
  2020-01-15  9:11           ` Jani Nikula
  0 siblings, 1 reply; 19+ messages in thread
From: Manna, Animesh @ 2020-01-06 10:02 UTC (permalink / raw)
  To: Manasi Navare, Jani Nikula
  Cc: nidhi1.gupta, intel-gfx, uma.shankar, dri-devel, anshuman.gupta

On 04-01-2020 05:18, Manasi Navare wrote:
> On Thu, Jan 02, 2020 at 03:56:09PM +0530, Manna, Animesh wrote:
>> On 02-01-2020 14:48, Jani Nikula wrote:
>>> On Mon, 30 Dec 2019, Animesh Manna <animesh.manna@intel.com> wrote:
>>>> vswing/pre-emphasis adjustment calculation is needed in processing
>>>> of auto phy compliance request other than link training, so moved
>>>> the same function in intel_dp.c.
>>> I guess I'm still asking why you think this is better located in
>>> intel_dp.c than intel_dp_link_training.c, as the function has been moved
>>> once in the other direction already to split out stuff from intel_dp.c
>>> and to make the file smaller. Even the file name suggests it should
>>> really be in intel_dp_link_training.c, right?
>> Just a thought, can we change the name to "intel_dp_link_config.c" from "intel_dp_link_training.c" which will provide little wider scope
>> and all the function playing with link configuration can be under it and also exposed through header file.
>>
>> AFAIK, processing phy compliance request always do not need link training. I understood link training is very specific process consisting of clock recovery + channel eq.
>> So I am afraid of exposing intel_get_adjust_train() from intel_dp_link_training.c which is not only specific to link-training. Need your suggestion.
>>
>> Regards,
>> Animesh
>>
> I agree with Jani here and I think I had even suggested this earlier that instead of moving this function to intel_dp.c
> we should make it non static so it can be used even for PHY compliance but since this function still deals
> with adjusting training patterns IMHO it should still stay in intel_dp_link_training.c
>
> Manasi

Sure Manasi, I will make intel_get_adjust_train() non-static and keep in intel_dp_link_training.c.
Now as suggested by Jani before (https://patchwork.freedesktop.org/patch/345823/?series=71121&rev=1#comment_640087) other non static functions are not following the rule,
should I change the function name or keep it as it is?

Regards,
Animesh

>   
>>> BR,
>>> Jani.
>>>
>>>
>>>> No functional change.
>>>>
>>>> v1: initial patch.
>>>> v2:
>>>> - used "intel_dp" prefix in function name. (Jani)
>>>> - used array notation instead pointer for link_status. (Ville)
>>>>
>>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/i915/display/intel_dp.c       | 34 ++++++++++++++++++
>>>>   drivers/gpu/drm/i915/display/intel_dp.h       |  4 +++
>>>>   .../drm/i915/display/intel_dp_link_training.c | 36 ++-----------------
>>>>   3 files changed, 40 insertions(+), 34 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> index 991f343579ef..2a27ee106089 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> @@ -4110,6 +4110,40 @@ ivb_cpu_edp_signal_levels(u8 train_set)
>>>>   	}
>>>>   }
>>>> +void
>>>> +intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>>>> +			  const u8 link_status[DP_LINK_STATUS_SIZE])
>>>> +{
>>>> +	u8 v = 0;
>>>> +	u8 p = 0;
>>>> +	int lane;
>>>> +	u8 voltage_max;
>>>> +	u8 preemph_max;
>>>> +
>>>> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>>>> +		u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
>>>> +							      lane);
>>>> +		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
>>>> +								   lane);
>>>> +
>>>> +		if (this_v > v)
>>>> +			v = this_v;
>>>> +		if (this_p > p)
>>>> +			p = this_p;
>>>> +	}
>>>> +
>>>> +	voltage_max = intel_dp_voltage_max(intel_dp);
>>>> +	if (v >= voltage_max)
>>>> +		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>>>> +
>>>> +	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
>>>> +	if (p >= preemph_max)
>>>> +		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>>>> +
>>>> +	for (lane = 0; lane < 4; lane++)
>>>> +		intel_dp->train_set[lane] = v | p;
>>>> +}
>>>> +
>>>>   void
>>>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>>>>   {
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>>>> index 3da166054788..83eadc87af26 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>>>> @@ -9,6 +9,7 @@
>>>>   #include <linux/types.h>
>>>>   #include <drm/i915_drm.h>
>>>> +#include <drm/drm_dp_helper.h>
>>>>   #include "i915_reg.h"
>>>> @@ -91,6 +92,9 @@ void
>>>>   intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>>>>   				       u8 dp_train_pat);
>>>>   void
>>>> +intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>>>> +			  const u8 link_status[DP_LINK_STATUS_SIZE]);
>>>> +void
>>>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp);
>>>>   void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
>>>>   u8
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>> index 2a1130dd1ad0..e8ff9e279800 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>>> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>>>>   		      link_status[3], link_status[4], link_status[5]);
>>>>   }
>>>> -static void
>>>> -intel_get_adjust_train(struct intel_dp *intel_dp,
>>>> -		       const u8 link_status[DP_LINK_STATUS_SIZE])
>>>> -{
>>>> -	u8 v = 0;
>>>> -	u8 p = 0;
>>>> -	int lane;
>>>> -	u8 voltage_max;
>>>> -	u8 preemph_max;
>>>> -
>>>> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>>>> -		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>>>> -		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>>>> -
>>>> -		if (this_v > v)
>>>> -			v = this_v;
>>>> -		if (this_p > p)
>>>> -			p = this_p;
>>>> -	}
>>>> -
>>>> -	voltage_max = intel_dp_voltage_max(intel_dp);
>>>> -	if (v >= voltage_max)
>>>> -		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>>>> -
>>>> -	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
>>>> -	if (p >= preemph_max)
>>>> -		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>>>> -
>>>> -	for (lane = 0; lane < 4; lane++)
>>>> -		intel_dp->train_set[lane] = v | p;
>>>> -}
>>>> -
>>>>   static bool
>>>>   intel_dp_set_link_train(struct intel_dp *intel_dp,
>>>>   			u8 dp_train_pat)
>>>> @@ -215,7 +183,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>>>>   		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
>>>>   		/* Update training set as requested by target */
>>>> -		intel_get_adjust_train(intel_dp, link_status);
>>>> +		intel_dp_get_adjust_train(intel_dp, link_status);
>>>>   		if (!intel_dp_update_link_train(intel_dp)) {
>>>>   			DRM_ERROR("failed to update link training\n");
>>>>   			return false;
>>>> @@ -325,7 +293,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>>>>   		}
>>>>   		/* Update training set as requested by target */
>>>> -		intel_get_adjust_train(intel_dp, link_status);
>>>> +		intel_dp_get_adjust_train(intel_dp, link_status);
>>>>   		if (!intel_dp_update_link_train(intel_dp)) {
>>>>   			DRM_ERROR("failed to update link training\n");
>>>>   			break;
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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec
  2020-01-03 23:54   ` Manasi Navare
@ 2020-01-06 23:05     ` Alex Deucher
  0 siblings, 0 replies; 19+ messages in thread
From: Alex Deucher @ 2020-01-06 23:05 UTC (permalink / raw)
  To: Manasi Navare
  Cc: Jani Nikula, nidhi1.gupta, Animesh Manna,
	Maling list - DRI developers, Shankar, Uma, anshuman.gupta,
	Alex Deucher, Intel Graphics Development

On Fri, Jan 3, 2020 at 6:53 PM Manasi Navare <manasi.d.navare@intel.com> wrote:
>
> Harry, Jani - Since this also updates the AMD driver file, should this be merged through
> AMD tree and then backmerged to drm-misc ?

Take it through whatever tree is easiest for you.

Alex

>
> Manasi
>
> On Mon, Dec 30, 2019 at 09:45:15PM +0530, Animesh Manna wrote:
> > [Why]:
> > Aligh with DP spec wanted to follow same naming convention.
> >
> > [How]:
> > Changed the macro name of the dpcd address used for getting requested
> > test-pattern.
> >
> > Cc: Harry Wentland <harry.wentland@amd.com>
> > Cc: Alex Deucher <alexander.deucher@amd.com>
> > Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
> >  include/drm/drm_dp_helper.h                      | 2 +-
> >  2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > index 42aa889fd0f5..1a6109be2fce 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > @@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
> >       /* get phy test pattern and pattern parameters from DP receiver */
> >       core_link_read_dpcd(
> >                       link,
> > -                     DP_TEST_PHY_PATTERN,
> > +                     DP_PHY_TEST_PATTERN,
> >                       &dpcd_test_pattern.raw,
> >                       sizeof(dpcd_test_pattern));
> >       core_link_read_dpcd(
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 8f8f3632e697..d6e560870fb1 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -699,7 +699,7 @@
> >  # define DP_TEST_CRC_SUPPORTED                   (1 << 5)
> >  # define DP_TEST_COUNT_MASK              0xf
> >
> > -#define DP_TEST_PHY_PATTERN                 0x248
> > +#define DP_PHY_TEST_PATTERN                 0x248
> >  #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
> >  #define      DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
> >  #define      DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
> > --
> > 2.24.0
> >
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
  2020-01-06 10:02         ` Manna, Animesh
@ 2020-01-15  9:11           ` Jani Nikula
  0 siblings, 0 replies; 19+ messages in thread
From: Jani Nikula @ 2020-01-15  9:11 UTC (permalink / raw)
  To: Manna\, Animesh, Manasi Navare
  Cc: nidhi1.gupta, intel-gfx, uma.shankar, dri-devel, anshuman.gupta

On Mon, 06 Jan 2020, "Manna, Animesh" <animesh.manna@intel.com> wrote:
> Sure Manasi, I will make intel_get_adjust_train() non-static and keep in intel_dp_link_training.c.
> Now as suggested by Jani before (https://patchwork.freedesktop.org/patch/345823/?series=71121&rev=1#comment_640087) other non static functions are not following the rule,
> should I change the function name or keep it as it is?

Please prefix it intel_dp_. I think intel_dp_link_training_ is too long
here. :)

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, back to index

Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-30 16:15 [PATCH v3 0/9] DP Phy compliance auto test Animesh Manna
2019-12-30 16:15 ` [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec Animesh Manna
2020-01-03 23:54   ` Manasi Navare
2020-01-06 23:05     ` Alex Deucher
2019-12-30 16:15 ` [PATCH v3 2/9] drm/dp: get/set phy compliance pattern Animesh Manna
2019-12-30 16:15 ` [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
2020-01-02  9:18   ` Jani Nikula
2020-01-02 10:26     ` Manna, Animesh
2020-01-03 23:48       ` Manasi Navare
2020-01-06 10:02         ` Manna, Animesh
2020-01-15  9:11           ` Jani Nikula
2019-12-30 16:15 ` [PATCH v3 4/9] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
2019-12-30 16:15 ` [PATCH v3 5/9] drm/i915/dsb: Send uevent to testapp Animesh Manna
2019-12-30 16:15 ` [PATCH v3 6/9] drm/i915/dp: Add debugfs entry for DP phy compliance Animesh Manna
2019-12-30 16:15 ` [PATCH v3 7/9] drm/i915/dp: Register definition for DP compliance register Animesh Manna
2019-12-30 16:15 ` [PATCH v3 8/9] drm/i915/dp: Update the pattern as per request Animesh Manna
2020-01-02  9:23   ` [Intel-gfx] " Jani Nikula
2020-01-03 23:51     ` Manasi Navare
2019-12-30 16:15 ` [PATCH v3 9/9] drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern Animesh Manna

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