From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: jani.nikula@intel.com, nidhi1.gupta@intel.com,
Animesh Manna <animesh.manna@intel.com>,
manasi.d.navare@intel.com, uma.shankar@intel.com,
anshuman.gupta@intel.com
Subject: [PATCH v3 7/9] drm/i915/dp: Register definition for DP compliance register
Date: Mon, 30 Dec 2019 21:45:21 +0530 [thread overview]
Message-ID: <20191230161523.32222-8-animesh.manna@intel.com> (raw)
In-Reply-To: <20191230161523.32222-1-animesh.manna@intel.com>
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 030a3f3e69af..a536d920324c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9794,6 +9794,26 @@ enum skl_power_gate {
#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
+/* DDI DP Compliance Control */
+#define DDI_DP_COMP_CTL_A 0x605F0
+#define DDI_DP_COMP_CTL_B 0x615F0
+#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, \
+ DDI_DP_COMP_CTL_B)
+#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
+#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
+#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
+#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A 0x605F4
+#define DDI_DP_COMP_PAT_B 0x615F4
+#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, \
+ DDI_DP_COMP_PAT_B) + (i) * 4)
+
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
--
2.24.0
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next prev parent reply other threads:[~2019-12-30 16:26 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-30 16:15 [PATCH v3 0/9] DP Phy compliance auto test Animesh Manna
2019-12-30 16:15 ` [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec Animesh Manna
2020-01-03 23:54 ` Manasi Navare
2020-01-06 23:05 ` Alex Deucher
2019-12-30 16:15 ` [PATCH v3 2/9] drm/dp: get/set phy compliance pattern Animesh Manna
2019-12-30 16:15 ` [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
2020-01-02 9:18 ` Jani Nikula
2020-01-02 10:26 ` Manna, Animesh
2020-01-03 23:48 ` Manasi Navare
2020-01-06 10:02 ` Manna, Animesh
2020-01-15 9:11 ` Jani Nikula
2019-12-30 16:15 ` [PATCH v3 4/9] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
2019-12-30 16:15 ` [PATCH v3 5/9] drm/i915/dsb: Send uevent to testapp Animesh Manna
2019-12-30 16:15 ` [PATCH v3 6/9] drm/i915/dp: Add debugfs entry for DP phy compliance Animesh Manna
2019-12-30 16:15 ` Animesh Manna [this message]
2019-12-30 16:15 ` [PATCH v3 8/9] drm/i915/dp: Update the pattern as per request Animesh Manna
2020-01-02 9:23 ` [Intel-gfx] " Jani Nikula
2020-01-03 23:51 ` Manasi Navare
2019-12-30 16:15 ` [PATCH v3 9/9] drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern Animesh Manna
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