From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: dri-devel@lists.freedesktop.org
Cc: Michal Simek <michal.simek@xilinx.com>,
Hyun Kwon <hyun.kwon@xilinx.com>,
Satish Kumar Nagireddy <SATISHNA@xilinx.com>
Subject: [PATCH v11 4/5] arm64: dts: zynqmp: Add DisplayPort subsystem
Date: Wed, 18 Mar 2020 17:37:27 +0200 [thread overview]
Message-ID: <20200318153728.25843-5-laurent.pinchart@ideasonboard.com> (raw)
In-Reply-To: <20200318153728.25843-1-laurent.pinchart@ideasonboard.com>
Add a DT node for the DisplayPort subsystem, a hard IP present in the
Zynq Ultrascale+ MPSoC.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
Changes since v10:
- Replace fixed frequency clocks with real clocks
- Add resets property to zynqmp-dpsub
Changes since v9:
- Update to the latest DPDMA DT bindings
---
.../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 6 +++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24 +++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index 32c4914738d9..48db1b353a1a 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -61,6 +61,12 @@ &dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
};
+&dpsub {
+ clocks = <&zynqmp_clk TOPSW_LSBUS>,
+ <&zynqmp_clk DP_AUDIO_REF>,
+ <&zynqmp_clk DP_VIDEO_REF>;
+};
+
&fpd_dma_chan1 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index b195fd0dbeed..003fa5c4d572 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -12,6 +12,7 @@
* the License, or (at your option) any later version.
*/
+#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
@@ -450,6 +451,29 @@ mc: memory-controller@fd070000 {
interrupts = <0 112 4>;
};
+ dpsub: display@fd4a0000 {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ status = "disabled";
+ reg = <0x0 0xfd4a0000 0x0 0x1000>,
+ <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <&gic>;
+
+ clock-names = "dp_apb_clk", "dp_aud_clk",
+ "dp_vtc_pixel_clk_in";
+
+ resets = <&reset ZYNQMP_RESET_DP>;
+
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <&dpdma ZYNQMP_DPDMA_VIDEO0>,
+ <&dpdma ZYNQMP_DPDMA_VIDEO1>,
+ <&dpdma ZYNQMP_DPDMA_VIDEO2>,
+ <&dpdma ZYNQMP_DPDMA_GRAPHICS>;
+ };
+
gem0: ethernet@ff0b0000 {
compatible = "cdns,zynqmp-gem", "cdns,gem";
status = "disabled";
--
Regards,
Laurent Pinchart
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next prev parent reply other threads:[~2020-03-18 15:37 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-18 15:37 [PATCH v11 0/5] Xilinx ZynqMP DisplayPort Subsystem DRM/KMS driver Laurent Pinchart
2020-03-18 15:37 ` [PATCH v11 1/5] dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings Laurent Pinchart
2020-03-18 19:26 ` Sam Ravnborg
2020-03-19 1:08 ` Hyun Kwon
2020-03-19 6:22 ` Michal Simek
2020-04-02 3:11 ` Laurent Pinchart
2020-04-15 16:58 ` Laurent Pinchart
2020-03-19 1:50 ` Laurent Pinchart
2020-03-18 15:37 ` [PATCH v11 2/5] drm: xlnx: DRM/KMS driver for Xilinx ZynqMP DisplayPort Subsystem Laurent Pinchart
2020-03-18 20:30 ` Sam Ravnborg
2020-03-19 2:27 ` Laurent Pinchart
2020-03-18 15:37 ` [PATCH v11 3/5] arm64: dts: zynqmp: Add reset controller Laurent Pinchart
2020-03-18 15:37 ` Laurent Pinchart [this message]
2020-03-18 15:37 ` [PATCH v11 5/5] arm64: dts: zynqmp: zcu106-revA: Wire up the DisplayPort subsystem Laurent Pinchart
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