From: Dmitry Osipenko <digetx@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Artur Świgoń" <a.swigon@samsung.com>,
"Georgi Djakov" <georgi.djakov@linaro.org>,
"Rob Herring" <robh+dt@kernel.org>
Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-pm@vger.kernel.org
Subject: [PATCH v2 06/22] dt-bindings: memory: tegra20: Add memory client IDs
Date: Mon, 30 Mar 2020 04:08:48 +0300 [thread overview]
Message-ID: <20200330010904.27643-7-digetx@gmail.com> (raw)
In-Reply-To: <20200330010904.27643-1-digetx@gmail.com>
Each memory client have a unique hardware ID, this patch adds these IDs.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
include/dt-bindings/memory/tegra20-mc.h | 53 +++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/include/dt-bindings/memory/tegra20-mc.h b/include/dt-bindings/memory/tegra20-mc.h
index 35e131eee198..6f8829508ad0 100644
--- a/include/dt-bindings/memory/tegra20-mc.h
+++ b/include/dt-bindings/memory/tegra20-mc.h
@@ -18,4 +18,57 @@
#define TEGRA20_MC_RESET_VDE 13
#define TEGRA20_MC_RESET_VI 14
+#define TEGRA20_MC_DISPLAY0A 0
+#define TEGRA20_MC_DISPLAY0AB 1
+#define TEGRA20_MC_DISPLAY0B 2
+#define TEGRA20_MC_DISPLAY0BB 3
+#define TEGRA20_MC_DISPLAY0C 4
+#define TEGRA20_MC_DISPLAY0CB 5
+#define TEGRA20_MC_DISPLAY1B 6
+#define TEGRA20_MC_DISPLAY1BB 7
+#define TEGRA20_MC_EPPUP 8
+#define TEGRA20_MC_G2PR 9
+#define TEGRA20_MC_G2SR 10
+#define TEGRA20_MC_MPEUNIFBR 11
+#define TEGRA20_MC_VIRUV 12
+#define TEGRA20_MC_AVPCARM7R 13
+#define TEGRA20_MC_DISPLAYHC 14
+#define TEGRA20_MC_DISPLAYHCB 15
+#define TEGRA20_MC_FDCDRD 16
+#define TEGRA20_MC_G2DR 17
+#define TEGRA20_MC_HOST1XDMAR 18
+#define TEGRA20_MC_HOST1XR 19
+#define TEGRA20_MC_IDXSRD 20
+#define TEGRA20_MC_MPCORER 21
+#define TEGRA20_MC_MPE_IPRED 22
+#define TEGRA20_MC_MPEAMEMRD 23
+#define TEGRA20_MC_MPECSRD 24
+#define TEGRA20_MC_PPCSAHBDMAR 25
+#define TEGRA20_MC_PPCSAHBSLVR 26
+#define TEGRA20_MC_TEXSRD 27
+#define TEGRA20_MC_VDEBSEVR 28
+#define TEGRA20_MC_VDEMBER 29
+#define TEGRA20_MC_VDEMCER 30
+#define TEGRA20_MC_VDETPER 31
+#define TEGRA20_MC_EPPU 32
+#define TEGRA20_MC_EPPV 33
+#define TEGRA20_MC_EPPY 34
+#define TEGRA20_MC_MPEUNIFBW 35
+#define TEGRA20_MC_VIWSB 36
+#define TEGRA20_MC_VIWU 37
+#define TEGRA20_MC_VIWV 38
+#define TEGRA20_MC_VIWY 39
+#define TEGRA20_MC_G2DW 40
+#define TEGRA20_MC_AVPCARM7W 41
+#define TEGRA20_MC_FDCDWR 42
+#define TEGRA20_MC_HOST1XW 43
+#define TEGRA20_MC_ISPW 44
+#define TEGRA20_MC_MPCOREW 45
+#define TEGRA20_MC_MPECSWR 46
+#define TEGRA20_MC_PPCSAHBDMAW 47
+#define TEGRA20_MC_PPCSAHBSLVW 48
+#define TEGRA20_MC_VDEBSEVW 49
+#define TEGRA20_MC_VDEMBEW 50
+#define TEGRA20_MC_VDETPMW 51
+
#endif
--
2.25.1
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next prev parent reply other threads:[~2020-03-30 7:12 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-30 1:08 [PATCH v2 00/22] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 01/22] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko
2020-04-10 17:05 ` Rob Herring
2020-03-30 1:08 ` [PATCH v2 02/22] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko
2020-04-10 17:06 ` Rob Herring
2020-03-30 1:08 ` [PATCH v2 03/22] dt-bindings: memory: tegra30: mc: " Dmitry Osipenko
2020-04-10 17:06 ` Rob Herring
2020-03-30 1:08 ` [PATCH v2 04/22] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko
2020-04-10 17:07 ` Rob Herring
2020-03-30 1:08 ` [PATCH v2 05/22] dt-bindings: host1x: Document new interconnect properties Dmitry Osipenko
2020-04-10 17:09 ` Rob Herring
2020-04-10 18:28 ` Dmitry Osipenko
2020-03-30 1:08 ` Dmitry Osipenko [this message]
2020-04-10 17:10 ` [PATCH v2 06/22] dt-bindings: memory: tegra20: Add memory client IDs Rob Herring
2020-03-30 1:08 ` [PATCH v2 07/22] dt-bindings: memory: tegra30: " Dmitry Osipenko
2020-04-10 17:10 ` Rob Herring
2020-03-30 1:08 ` [PATCH v2 08/22] ARM: tegra: Add interconnect properties to Tegra20 device-tree Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 09/22] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 10/22] interconnect: Relax requirement in of_icc_get_from_provider() Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 11/22] memory: tegra: Register as interconnect provider Dmitry Osipenko
2020-04-13 12:43 ` Georgi Djakov
2020-04-13 15:01 ` Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 12/22] memory: tegra20-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 13/22] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 14/22] memory: tegra20-emc: Register as interconnect provider Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 15/22] memory: tegra20-emc: Create tegra20-devfreq device Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 16/22] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-03-30 1:08 ` [PATCH v2 17/22] memory: tegra30-emc: Register as interconnect provider Dmitry Osipenko
2020-04-13 12:44 ` Georgi Djakov
2020-04-13 15:18 ` Dmitry Osipenko
2020-03-30 1:09 ` [PATCH v2 18/22] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko
2020-03-30 1:09 ` [PATCH v2 19/22] drm/tegra: dc: Tune up high priority request controls for Tegra20 Dmitry Osipenko
2020-03-30 1:09 ` [PATCH v2 20/22] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko
2020-03-30 1:09 ` [PATCH v2 21/22] ARM: tegra: Enable interconnect API in tegra_defconfig Dmitry Osipenko
2020-03-30 1:09 ` [PATCH v2 22/22] ARM: multi_v7_defconfig: Enable interconnect API Dmitry Osipenko
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