From: Jordan Crouse <jcrouse@codeaurora.org> To: Jonathan Marek <jonathan@marek.ca> Cc: Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <linux-arm-msm@vger.kernel.org>, Sharat Masetty <smasetty@codeaurora.org>, open list <linux-kernel@vger.kernel.org>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <dri-devel@lists.freedesktop.org>, Stephen Boyd <swboyd@chromium.org>, "Michael J. Ruhl" <michael.j.ruhl@intel.com>, freedreno@lists.freedesktop.org Subject: Re: [Freedreno] [PATCH 8/9] drm/msm/a6xx: enable GMU log Date: Tue, 21 Apr 2020 10:38:41 -0600 Message-ID: <20200421163841.GC13825@jcrouse1-lnx.qualcomm.com> (raw) In-Reply-To: <20200420140313.7263-9-jonathan@marek.ca> On Mon, Apr 20, 2020 at 10:03:12AM -0400, Jonathan Marek wrote: > This is required for a650 to work. > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16 ++++++++++++++++ > drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + > drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 4 ++++ > 3 files changed, 21 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index b583bf6e293b..1cdb7c832b87 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -198,6 +198,12 @@ static int a6xx_gmu_start(struct a6xx_gmu *gmu) > u32 val; > > gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); > + > + /* Set the log wptr index > + * note: downstream saves the value in poweroff and restores it here > + */ > + gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); > + > gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); > > ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, > @@ -739,6 +745,9 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > > gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); > > + gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG, > + gmu->log->iova | (gmu->log->size / SZ_4K - 1)); > + > /* Set up the lowest idle level on the GMU */ > a6xx_gmu_power_config(gmu); > > @@ -1416,6 +1425,7 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) > a6xx_gmu_memory_free(gmu, gmu->dcache); > a6xx_gmu_memory_free(gmu, gmu->dummy); > a6xx_gmu_memory_free(gmu, gmu->debug); > + a6xx_gmu_memory_free(gmu, gmu->log); > a6xx_gmu_memory_free(gmu, gmu->hfi); > > iommu_detach_device(gmu->domain, gmu->dev); > @@ -1495,6 +1505,11 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) > if (IS_ERR(gmu->hfi)) > goto err_memory; > > + /* Allocate memory for the GMU log region */ > + gmu->log = a6xx_gmu_memory_alloc(gmu, SZ_4K, 0); > + if (IS_ERR(gmu->log)) > + goto err_memory; > + > /* Map the GMU registers */ > gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); > if (IS_ERR(gmu->mmio)) > @@ -1542,6 +1557,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) > a6xx_gmu_memory_free(gmu, gmu->dcache); > a6xx_gmu_memory_free(gmu, gmu->dummy); > a6xx_gmu_memory_free(gmu, gmu->debug); > + a6xx_gmu_memory_free(gmu, gmu->log); > a6xx_gmu_memory_free(gmu, gmu->hfi); This is starting to feel like we could use some devres style garbage collection. > > if (gmu->domain) { > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > index abd425ca6682..589b9b0c348e 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > @@ -59,6 +59,7 @@ struct a6xx_gmu { > > struct a6xx_gmu_bo *hfi; > struct a6xx_gmu_bo *debug; > + struct a6xx_gmu_bo *log; > struct a6xx_gmu_bo *icache; > struct a6xx_gmu_bo *dcache; > struct a6xx_gmu_bo *dummy; > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h > index b4357ea550ec..176ae94d9fe6 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h > @@ -205,6 +205,10 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) > > #define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0 > > +#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100 > + > +#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101 > + > #define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE 0x000051f0 > > #define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL 0x00005157 > -- > 2.26.1 > > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply index Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <20200420140313.7263-1-jonathan@marek.ca> 2020-04-20 14:03 ` [PATCH 1/9] drm/msm/adreno: add A640/A650 to gpulist Jonathan Marek 2020-04-20 14:30 ` Greg Kroah-Hartman 2020-04-20 14:03 ` [PATCH 2/9] Revert "drm/msm/a6xx: Use the DMA API for GMU memory objects" Jonathan Marek 2020-04-20 19:51 ` Bjorn Andersson 2020-04-20 19:59 ` Jonathan Marek 2020-04-20 21:16 ` Rob Clark 2020-04-20 14:03 ` [PATCH 3/9] drm/msm/a6xx: allow allocating GMU memory with a fixed address Jonathan Marek 2020-04-20 14:03 ` [PATCH 4/9] drm/msm/a6xx: HFI v2 for A640 and A650 Jonathan Marek 2020-04-21 16:30 ` Jordan Crouse 2020-04-21 16:52 ` Jonathan Marek 2020-04-20 14:03 ` [PATCH 5/9] drm/msm/a6xx: A640/A650 GMU firmware path Jonathan Marek 2020-04-20 14:03 ` [PATCH 6/9] drm/msm/a6xx: add support for A650 gmu rscc registers Jonathan Marek 2020-04-20 14:03 ` [PATCH 7/9] drm/msm/a6xx: gmu_pdc register values for A640 and A650 Jonathan Marek 2020-04-21 16:34 ` Jordan Crouse 2020-04-20 14:03 ` [PATCH 8/9] drm/msm/a6xx: enable GMU log Jonathan Marek 2020-04-21 16:38 ` Jordan Crouse [this message] 2020-04-20 14:03 ` [PATCH 9/9] drm/msm/a6xx: update a6xx_hw_init for A640 and A650 Jonathan Marek 2020-04-21 16:48 ` Jordan Crouse
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