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Tue, 2 Jun 2020 10:12:29 -0400 (EDT) Date: Tue, 2 Jun 2020 16:12:28 +0200 From: Maxime Ripard To: Eric Anholt Subject: Re: [PATCH v3 032/105] drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable Message-ID: <20200602141228.7zbkob7bw3owajsq@gilmour> References: MIME-Version: 1.0 In-Reply-To: X-Mailman-Approved-At: Wed, 03 Jun 2020 07:04:29 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tim Gover , Dave Stevenson , linux-kernel@vger.kernel.org, DRI Development , bcm-kernel-feedback-list@broadcom.com, Nicolas Saenz Julienne , Phil Elwell , linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============0281621603==" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --===============0281621603== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="6jdhhfajj55wnhto" Content-Disposition: inline --6jdhhfajj55wnhto Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Eric On Wed, May 27, 2020 at 09:54:44AM -0700, Eric Anholt wrote: > On Wed, May 27, 2020 at 8:50 AM Maxime Ripard wrote: > > > > The VIDEN bit in the pixelvalve currently being used to enable or disab= le > > the pixelvalve seems to not be enough in some situations, which whill e= nd > > up with the pixelvalve stalling. > > > > In such a case, even re-enabling VIDEN doesn't bring it back and we nee= d to > > clear the FIFO. This can only be done if the pixelvalve is disabled tho= ugh. > > > > In order to overcome this, we can configure the pixelvalve during > > mode_set_no_fb, but only enable it in atomic_enable and flush the FIFO > > there, and in atomic_disable disable the pixelvalve again. >=20 > What displays has this been tested with? Getting this sequencing > right is so painful, and things like DSI are tricky to get to light > up. That FIFO is between the HVS and the HDMI PVs, so this was obviously tested against that. Dave also tested the DSI output IIRC, so we should be covered here. Maxime --6jdhhfajj55wnhto Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXtZeTAAKCRDj7w1vZxhR xVJqAQCUmpR8JL8pnnKjcPFlmgxyfzwLZXpVwBbL1P2+kZmIMAEAtrzlIP25oS5g 9aixg7Ifrmc88nWmBcIbxDH1tuDcFAs= =Ak49 -----END PGP SIGNATURE----- --6jdhhfajj55wnhto-- --===============0281621603== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel --===============0281621603==--