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Wed, 2 Sep 2020 10:48:45 -0400 (EDT) Date: Wed, 2 Sep 2020 16:48:43 +0200 From: Maxime Ripard To: Chanwoo Choi Subject: Re: [PATCH v4 03/78] drm/vc4: hvs: Boost the core clock during modeset Message-ID: <20200902144843.fuvgtu62wdrnd4on@gilmour.lan> References: MIME-Version: 1.0 In-Reply-To: X-Mailman-Approved-At: Thu, 03 Sep 2020 08:50:07 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tim Gover , Dave Stevenson , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, bcm-kernel-feedback-list@broadcom.com, Nicolas Saenz Julienne , Phil Elwell , linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============1243100537==" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --===============1243100537== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="oo64qjpa7isnxgnm" Content-Disposition: inline --oo64qjpa7isnxgnm Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Tue, Sep 01, 2020 at 08:21:36PM +0900, Chanwoo Choi wrote: > Hi Maxime, >=20 > On 7/9/20 2:41 AM, Maxime Ripard wrote: > > In order to prevent timeouts and stalls in the pipeline, the core clock > > needs to be maxed at 500MHz during a modeset on the BCM2711. > >=20 > > Reviewed-by: Eric Anholt > > Signed-off-by: Maxime Ripard > > --- > > drivers/gpu/drm/vc4/vc4_drv.h | 2 ++ > > drivers/gpu/drm/vc4/vc4_hvs.c | 9 +++++++++ > > drivers/gpu/drm/vc4/vc4_kms.c | 9 +++++++++ > > 3 files changed, 20 insertions(+) > >=20 > > diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_dr= v.h > > index e4cde1f9224b..6358f6ca8d56 100644 > > --- a/drivers/gpu/drm/vc4/vc4_drv.h > > +++ b/drivers/gpu/drm/vc4/vc4_drv.h > > @@ -320,6 +320,8 @@ struct vc4_hvs { > > void __iomem *regs; > > u32 __iomem *dlist; > > =20 > > + struct clk *core_clk; > > + > > /* Memory manager for CRTCs to allocate space in the display > > * list. Units are dwords. > > */ > > diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hv= s.c > > index 836d8799d79e..091fdf4908aa 100644 > > --- a/drivers/gpu/drm/vc4/vc4_hvs.c > > +++ b/drivers/gpu/drm/vc4/vc4_hvs.c > > @@ -19,6 +19,7 @@ > > * each CRTC. > > */ > > =20 > > +#include > > #include > > #include > > =20 > > @@ -540,6 +541,14 @@ static int vc4_hvs_bind(struct device *dev, struct= device *master, void *data) > > hvs->regset.regs =3D hvs_regs; > > hvs->regset.nregs =3D ARRAY_SIZE(hvs_regs); > > =20 > > + if (hvs->hvs5) { > > + hvs->core_clk =3D devm_clk_get(&pdev->dev, NULL); > > + if (IS_ERR(hvs->core_clk)) { > > + dev_err(&pdev->dev, "Couldn't get core clock\n"); > > + return PTR_ERR(hvs->core_clk); > > + } > > + } > > + > > if (!hvs->hvs5) > > hvs->dlist =3D hvs->regs + SCALER_DLIST_START; > > else > > diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_km= s.c > > index 08318e69061b..210cc2408087 100644 > > --- a/drivers/gpu/drm/vc4/vc4_kms.c > > +++ b/drivers/gpu/drm/vc4/vc4_kms.c > > @@ -11,6 +11,8 @@ > > * crtc, HDMI encoder). > > */ > > =20 > > +#include > > + > > #include > > #include > > #include > > @@ -149,6 +151,7 @@ vc4_atomic_complete_commit(struct drm_atomic_state = *state) > > { > > struct drm_device *dev =3D state->dev; > > struct vc4_dev *vc4 =3D to_vc4_dev(dev); > > + struct vc4_hvs *hvs =3D vc4->hvs; > > struct vc4_crtc *vc4_crtc; > > int i; > > =20 > > @@ -160,6 +163,9 @@ vc4_atomic_complete_commit(struct drm_atomic_state = *state) > > vc4_hvs_mask_underrun(dev, vc4_crtc->channel); > > } > > =20 > > + if (vc4->hvs->hvs5) > > + clk_set_min_rate(hvs->core_clk, 500000000); > > + > > drm_atomic_helper_wait_for_fences(dev, state, false); > > =20 > > drm_atomic_helper_wait_for_dependencies(state); > > @@ -182,6 +188,9 @@ vc4_atomic_complete_commit(struct drm_atomic_state = *state) > > =20 > > drm_atomic_helper_commit_cleanup_done(state); > > =20 > > + if (vc4->hvs->hvs5) > > + clk_set_min_rate(hvs->core_clk, 0); > > + > > drm_atomic_state_put(state); > > =20 > > up(&vc4->async_modeset); > >=20 >=20 > This patch doesn't control the enable/disable of core_clk. > So, I think that it need to handle the clock as following: >=20 > diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c > index 4ef88c0b51ab..355d67fd8beb 100644 > --- a/drivers/gpu/drm/vc4/vc4_hvs.c > +++ b/drivers/gpu/drm/vc4/vc4_hvs.c > @@ -588,6 +588,12 @@ static int vc4_hvs_bind(struct device *dev, struct d= evice *master, void *data) > dev_err(&pdev->dev, "Couldn't get core clock\n"); > return PTR_ERR(hvs->core_clk); > } > + > + ret =3D clk_prepare_enable(hvs->core_clk); > + if (ret) { > + dev_err(&pdev->dev, "Couldn't enable core clock\n= "); > + return ret; > + } > } > =20 > if (!hvs->hvs5) > @@ -681,6 +687,8 @@ static void vc4_hvs_unbind(struct device *dev, struct= device *master, > drm_mm_takedown(&vc4->hvs->dlist_mm); > drm_mm_takedown(&vc4->hvs->lbm_mm); > =20 > + clk_prepare_enable(vc4->hvs->core_clk); > + > vc4->hvs =3D NULL; > } Good catch, thanks! Maxime --oo64qjpa7isnxgnm Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCX0+wywAKCRDj7w1vZxhR xWO1AQDeDuT9LC5OJjJCw0wJbII/glIroNJaR6BYRKSfUw2EVAEAg87EDHY2jhPJ nlutA8am7X/slgA6UtdYLqOm5hJ6Lgo= =gbvn -----END PGP SIGNATURE----- --oo64qjpa7isnxgnm-- --===============1243100537== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel --===============1243100537==--