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Wed, 2 Sep 2020 11:08:16 -0400 (EDT) Date: Wed, 2 Sep 2020 17:08:15 +0200 From: Maxime Ripard To: Stefan Wahren Subject: Re: [PATCH v4 29/78] drm/vc4: crtc: Add a delay after disabling the PixelValve output Message-ID: <20200902150815.kw3nynnlvgrrcygc@gilmour.lan> References: <20200729144251.us6a2pgkjjmm53ov@gilmour.lan> <20200825150606.utlynhzo664bwksy@gilmour.lan> <20200901095829.64a5hjghf3mlsyvo@gilmour.lan> <27a549fe-e38d-f9a2-2677-ae5b5dc1aa45@i2se.com> MIME-Version: 1.0 In-Reply-To: <27a549fe-e38d-f9a2-2677-ae5b5dc1aa45@i2se.com> X-Mailman-Approved-At: Thu, 03 Sep 2020 08:50:07 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tim Gover , Dave Stevenson , LKML , DRI Development , bcm-kernel-feedback-list@broadcom.com, Nicolas Saenz Julienne , Phil Elwell , linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============1803107919==" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --===============1803107919== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="cdchspgt6i3o3s2q" Content-Disposition: inline --cdchspgt6i3o3s2q Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Sep 01, 2020 at 06:31:07PM +0200, Stefan Wahren wrote: > Hi Maxime, >=20 > Am 01.09.20 um 11:58 schrieb Maxime Ripard: > > Hi Stefan > > > > On Tue, Aug 25, 2020 at 11:30:58PM +0200, Stefan Wahren wrote: > >> Am 25.08.20 um 17:06 schrieb Maxime Ripard: > >>> Hi Stefan, > >>> > >>> On Wed, Jul 29, 2020 at 05:50:31PM +0200, Stefan Wahren wrote: > >>>> Am 29.07.20 um 16:42 schrieb Maxime Ripard: > >>>>> Hi, > >>>>> > >>>>> On Wed, Jul 29, 2020 at 03:09:21PM +0100, Dave Stevenson wrote: > >>>>>> On Wed, 8 Jul 2020 at 18:43, Maxime Ripard wro= te: > >>>>>>> In order to avoid pixels getting stuck in the (unflushable) FIFO = between > >>>>>>> the HVS and the PV, we need to add some delay after disabling the= PV output > >>>>>>> and before disabling the HDMI controller. 20ms seems to be good e= nough so > >>>>>>> let's use that. > >>>>>>> > >>>>>>> Signed-off-by: Maxime Ripard > >>>>>>> --- > >>>>>>> drivers/gpu/drm/vc4/vc4_crtc.c | 2 ++ > >>>>>>> 1 file changed, 2 insertions(+) > >>>>>>> > >>>>>>> diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4= /vc4_crtc.c > >>>>>>> index d0b326e1df0a..7b178d67187f 100644 > >>>>>>> --- a/drivers/gpu/drm/vc4/vc4_crtc.c > >>>>>>> +++ b/drivers/gpu/drm/vc4/vc4_crtc.c > >>>>>>> @@ -403,6 +403,8 @@ static void vc4_crtc_atomic_disable(struct dr= m_crtc *crtc, > >>>>>>> ret =3D wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_= VIDEN), 1); > >>>>>>> WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"= ); > >>>>>>> > >>>>>>> + mdelay(20); > >>>>>> mdelay for 20ms seems a touch unfriendly as it's a busy wait. Can = we > >>>>>> not msleep instead? > >>>>> Since the timing was fairly critical, sleeping didn't seem like a g= ood > >>>>> solution since there's definitely some chance you overshoot and end= up > >>>>> with a higher time than the one you targeted. > >>>> usleep_range(min, max) isn't a solution? > >>> My understanding of usleep_range was that you can still overshoot, ev= en > >>> though it's backed by an HR timer so the resolution is not a jiffy. A= re > >>> we certain that we're going to be in that range? > >> you are right there is no guarantee about the upper wake up time. > >> > >> And it's not worth the effort to poll the FIFO state until its empty > >> (using 20 ms as timeout)? > > I know this isn't really a great argument there, but getting this to > > work has been quite painful, and the timing is very sensitive. If we > > fail to wait for enough time, there's going to be a pixel shift that we > > can't get rid of unless we reboot, which is pretty bad (and would fail > > any CI test that checks for the output integrity). > > > > I know busy-looping for 20ms isn't ideal, but it's not really in a > > hot-path (it's only done when changing a mode), with the sync time of > > the display likely to be much more than that, and if it can avoid having > > to look into it ever again or avoid random failures, I'd say it's worth > > it. >=20 > i don't want to delay this series. >=20 > Could you please add a small comment to the delay to clarify the timing > is very sensitive? I will, thanks! Maxime --cdchspgt6i3o3s2q Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCX0+1XwAKCRDj7w1vZxhR xTExAQDs1BYdGeS/lvk546x1sgn6AifEwOlrVxDSeMO/QWhu3wD/RfIhHhh1s1j1 DfqNBjaatkPCQAZkursDakHjOFFOYQI= =bDzq -----END PGP SIGNATURE----- --cdchspgt6i3o3s2q-- --===============1803107919== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel --===============1803107919==--