From: Dmitry Osipenko <digetx@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Alan Stern" <stern@rowland.harvard.edu>,
"Peter Chen" <Peter.Chen@nxp.com>,
"Mark Brown" <broonie@kernel.org>,
"Liam Girdwood" <lgirdwood@gmail.com>,
"Adrian Hunter" <adrian.hunter@intel.com>,
"Krzysztof Kozlowski" <krzk@kernel.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Lee Jones" <lee.jones@linaro.org>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Ulf Hansson" <ulf.hansson@linaro.org>,
"Mauro Carvalho Chehab" <mchehab@kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Marek Szyprowski" <m.szyprowski@samsung.com>,
"Peter Geis" <pgwipeout@gmail.com>,
"Nicolas Chauvet" <kwizart@gmail.com>
Cc: devel@driverdev.osuosl.org, linux-pwm@vger.kernel.org,
linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-usb@vger.kernel.org, linux-mmc@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-tegra@vger.kernel.org, linux-media@vger.kernel.org
Subject: [PATCH v1 24/30] ARM: tegra: Add OPP tables for Tegra20 peripheral devices
Date: Thu, 5 Nov 2020 02:44:21 +0300 [thread overview]
Message-ID: <20201104234427.26477-25-digetx@gmail.com> (raw)
In-Reply-To: <20201104234427.26477-1-digetx@gmail.com>
Add OPP tables for Tegra20 SoC devices.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
.../arm/boot/dts/tegra20-peripherals-opp.dtsi | 386 ++++++++++++++++++
arch/arm/boot/dts/tegra20.dtsi | 14 +
2 files changed, 400 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
index 25b1ba73951e..792dc79d32c5 100644
--- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
+++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
@@ -89,4 +89,390 @@ opp@760000000 {
opp-hz = /bits/ 64 <760000000>;
};
};
+
+ vde_dvfs_opp_table: vde-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@95000000,950 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <95000000>;
+ opp-supported-hw = <0x0001>;
+ };
+
+ opp@123500000,1000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <123500000>;
+ opp-supported-hw = <0x0001>;
+ };
+
+ opp@123500000,950 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <123500000>;
+ opp-supported-hw = <0x0002>;
+ };
+
+ opp@152000000,1000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <152000000>;
+ opp-supported-hw = <0x0002>;
+ };
+
+ opp@152000000,950 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <152000000>;
+ opp-supported-hw = <0x0004>;
+ };
+
+ opp@171000000,950 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <171000000>;
+ opp-supported-hw = <0x0008>;
+ };
+
+ opp@209000000,1100 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <209000000>;
+ opp-supported-hw = <0x0001>;
+ };
+
+ opp@209000000,1000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <209000000>;
+ opp-supported-hw = <0x0004>;
+ };
+
+ opp@218500000,1000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <218500000>;
+ opp-supported-hw = <0x0008>;
+ };
+
+ opp@237500000,1100 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <237500000>;
+ opp-supported-hw = <0x0002>;
+ };
+
+ opp@275500000,1200 {
+ opp-microvolt = <1200000 1200000 1300000>;
+ opp-hz = /bits/ 64 <275500000>;
+ opp-supported-hw = <0x0001>;
+ };
+
+ opp@285000000,1100 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <285000000>;
+ opp-supported-hw = <0x0004>;
+ };
+
+ opp@300000000,1275 {
+ opp-microvolt = <1275000 1275000 1300000>;
+ opp-hz = /bits/ 64 <300000000>;
+ opp-supported-hw = <0x0001>;
+ };
+
+ opp@300000000,1200 {
+ opp-microvolt = <1200000 1200000 1300000>;
+ opp-hz = /bits/ 64 <300000000>;
+ opp-supported-hw = <0x0006>;
+ };
+
+ opp@300000000,1100 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <300000000>;
+ opp-supported-hw = <0x0008>;
+ };
+ };
+
+ gr2d_dvfs_opp_table: gr2d-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@133000000,950 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <133000000>;
+ opp-supported-hw = <0x000F>;
+ };
+
+ opp@171000000,1000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <171000000>;
+ opp-supported-hw = <0x000F>;
+ };
+
+ opp@247000000,1100 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <247000000>;
+ opp-supported-hw = <0x000F>;
+ };
+
+ opp@300000000,1200 {
+ opp-microvolt = <1200000 1200000 1300000>;
+ opp-hz = /bits/ 64 <300000000>;
+ opp-supported-hw = <0x000F>;
+ };
+ };
+
+ gr3d_dvfs_opp_table: gr3d-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@114000000,950 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <114000000>;
+ opp-supported-hw = <0x0001>;
+ };
+
+ opp@161500000,1000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <161500000>;
+ opp-supported-hw = <0x0001>;
+ };
+
+ opp@161500000,950 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <161500000>;
+ opp-supported-hw = <0x0002>;
+ };
+
+ opp@209000000,1000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <209000000>;
+ opp-supported-hw = <0x0002>;
+ };
+
+ opp@218500000,950 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <218500000>;
+ opp-supported-hw = <0x0004>;
+ };
+
+ opp@247000000,1100 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <247000000>;
+ opp-supported-hw = <0x0001>;
+ };
+
+ opp@247000000,950 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <247000000>;
+ opp-supported-hw = <0x0008>;
+ };
+
+ opp@256500000,1000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <256500000>;
+ opp-supported-hw = <0x0004>;
+ };
+
+ opp@285000000,1100 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <285000000>;
+ opp-supported-hw = <0x0002>;
+ };
+
+ opp@285000000,1000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <285000000>;
+ opp-supported-hw = <0x0008>;
+ };
+
+ opp@304000000,1200 {
+ opp-microvolt = <1200000 1200000 1300000>;
+ opp-hz = /bits/ 64 <304000000>;
+ opp-supported-hw = <0x0001>;
+ };
+
+ opp@323000000,1100 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <323000000>;
+ opp-supported-hw = <0x0004>;
+ };
+
+ opp@333500000,1275 {
+ opp-microvolt = <1275000 1275000 1300000>;
+ opp-hz = /bits/ 64 <333500000>;
+ opp-supported-hw = <0x0001>;
+ };
+
+ opp@333500000,1200 {
+ opp-microvolt = <1200000 1200000 1300000>;
+ opp-hz = /bits/ 64 <333500000>;
+ opp-supported-hw = <0x0002>;
+ };
+
+ opp@351500000,1100 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <351500000>;
+ opp-supported-hw = <0x0008>;
+ };
+
+ opp@361000000,1275 {
+ opp-microvolt = <1275000 1275000 1300000>;
+ opp-hz = /bits/ 64 <361000000>;
+ opp-supported-hw = <0x0002>;
+ };
+
+ opp@380000000,1200 {
+ opp-microvolt = <1200000 1200000 1300000>;
+ opp-hz = /bits/ 64 <380000000>;
+ opp-supported-hw = <0x0004>;
+ };
+
+ opp@400000000,1275 {
+ opp-microvolt = <1275000 1275000 1300000>;
+ opp-hz = /bits/ 64 <400000000>;
+ opp-supported-hw = <0x0004>;
+ };
+
+ opp@400000000,1200 {
+ opp-microvolt = <1200000 1200000 1300000>;
+ opp-hz = /bits/ 64 <400000000>;
+ opp-supported-hw = <0x0008>;
+ };
+ };
+
+ host1x_dvfs_opp_table: host1x-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@104500000,950 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <104500000>;
+ opp-supported-hw = <0x000F>;
+ };
+
+ opp@133000000,1000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <133000000>;
+ opp-supported-hw = <0x000F>;
+ };
+
+ opp@166000000,1100 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <166000000>;
+ opp-supported-hw = <0x000F>;
+ };
+ };
+
+ usbd_dvfs_opp_table: usbd-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@480000000 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <480000000>;
+ };
+ };
+
+ usb2_dvfs_opp_table: usb2-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@480000000 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <480000000>;
+ };
+ };
+
+ usb3_dvfs_opp_table: usb3-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@480000000 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <480000000>;
+ };
+ };
+
+ sdmmc1_dvfs_opp_table: sdmmc1-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@44000000 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <44000000>;
+ };
+
+ opp@52000000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <52000000>;
+ };
+ };
+
+ sdmmc2_dvfs_opp_table: sdmmc2-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@44000000 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <44000000>;
+ };
+
+ opp@52000000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <52000000>;
+ };
+ };
+
+ sdmmc3_dvfs_opp_table: sdmmc3-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@44000000 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <44000000>;
+ };
+
+ opp@52000000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <52000000>;
+ };
+ };
+
+ sdmmc4_dvfs_opp_table: sdmmc4-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@44000000 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <44000000>;
+ };
+
+ opp@52000000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <52000000>;
+ };
+ };
+
+ hdmi_dvfs_opp_table: hdmi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@148500000 {
+ opp-microvolt = <1200000 1200000 1300000>;
+ opp-hz = /bits/ 64 <148500000>;
+ };
+ };
+
+ dc0_dvfs_opp_table: dc0-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@158000000,950 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <158000000>;
+ opp-supported-hw = <0x000F>;
+ };
+
+ opp@190000000,1100 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <190000000>;
+ opp-supported-hw = <0x000F>;
+ };
+ };
+
+ dc1_dvfs_opp_table: dc1-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@158000000,950 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <158000000>;
+ opp-supported-hw = <0x000F>;
+ };
+
+ opp@190000000,1100 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <190000000>;
+ opp-supported-hw = <0x000F>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 6ce498178105..317bdf75ff6c 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -42,6 +42,7 @@ host1x@50000000 {
clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
+ operating-points-v2 = <&host1x_dvfs_opp_table>;
#address-cells = <1>;
#size-cells = <1>;
@@ -91,6 +92,7 @@ gr2d@54140000 {
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
resets = <&tegra_car 21>;
reset-names = "2d";
+ operating-points-v2 = <&gr2d_dvfs_opp_table>;
};
gr3d@54180000 {
@@ -99,6 +101,7 @@ gr3d@54180000 {
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&tegra_car 24>;
reset-names = "3d";
+ operating-points-v2 = <&gr3d_dvfs_opp_table>;
};
dc@54200000 {
@@ -110,6 +113,7 @@ dc@54200000 {
clock-names = "dc", "parent";
resets = <&tegra_car 27>;
reset-names = "dc";
+ operating-points-v2 = <&dc0_dvfs_opp_table>;
nvidia,head = <0>;
@@ -138,6 +142,7 @@ dc@54240000 {
clock-names = "dc", "parent";
resets = <&tegra_car 26>;
reset-names = "dc";
+ operating-points-v2 = <&dc1_dvfs_opp_table>;
nvidia,head = <1>;
@@ -167,6 +172,7 @@ hdmi@54280000 {
resets = <&tegra_car 51>;
reset-names = "hdmi";
status = "disabled";
+ operating-points-v2 = <&hdmi_dvfs_opp_table>;
};
tvo@542c0000 {
@@ -319,6 +325,7 @@ vde@6001a000 {
clocks = <&tegra_car TEGRA20_CLK_VDE>;
reset-names = "vde", "mc";
resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
+ operating-points-v2 = <&vde_dvfs_opp_table>;
};
apbmisc@70000800 {
@@ -755,6 +762,7 @@ usb@c5000000 {
nvidia,needs-double-reset;
nvidia,phy = <&phy1>;
status = "disabled";
+ operating-points-v2 = <&usbd_dvfs_opp_table>;
};
phy1: usb-phy@c5000000 {
@@ -792,6 +800,7 @@ usb@c5004000 {
reset-names = "usb";
nvidia,phy = <&phy2>;
status = "disabled";
+ operating-points-v2 = <&usb2_dvfs_opp_table>;
};
phy2: usb-phy@c5004000 {
@@ -818,6 +827,7 @@ usb@c5008000 {
reset-names = "usb";
nvidia,phy = <&phy3>;
status = "disabled";
+ operating-points-v2 = <&usb3_dvfs_opp_table>;
};
phy3: usb-phy@c5008000 {
@@ -852,6 +862,7 @@ mmc@c8000000 {
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled";
+ operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
};
mmc@c8000200 {
@@ -863,6 +874,7 @@ mmc@c8000200 {
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled";
+ operating-points-v2 = <&sdmmc2_dvfs_opp_table>;
};
mmc@c8000400 {
@@ -874,6 +886,7 @@ mmc@c8000400 {
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disabled";
+ operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
};
mmc@c8000600 {
@@ -885,6 +898,7 @@ mmc@c8000600 {
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled";
+ operating-points-v2 = <&sdmmc4_dvfs_opp_table>;
};
cpus {
--
2.27.0
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next prev parent reply other threads:[~2020-11-05 8:21 UTC|newest]
Thread overview: 107+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-04 23:43 [PATCH v1 00/30] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs Dmitry Osipenko
2020-11-04 23:43 ` [PATCH v1 01/30] dt-bindings: host1x: Document OPP and voltage regulator properties Dmitry Osipenko
2020-11-09 18:57 ` Rob Herring
2020-11-11 11:45 ` Ulf Hansson
2020-11-04 23:43 ` [PATCH v1 02/30] dt-bindings: mmc: tegra: " Dmitry Osipenko
2020-11-09 18:58 ` Rob Herring
2020-11-04 23:44 ` [PATCH v1 03/30] dt-bindings: pwm: " Dmitry Osipenko
2020-11-09 19:00 ` Rob Herring
2020-11-04 23:44 ` [PATCH v1 04/30] media: dt: bindings: tegra-vde: " Dmitry Osipenko
2020-11-09 19:01 ` Rob Herring
2020-11-04 23:44 ` [PATCH v1 05/30] dt-binding: usb: ci-hdrc-usb2: " Dmitry Osipenko
2020-11-09 19:01 ` Rob Herring
2020-11-04 23:44 ` [PATCH v1 06/30] dt-bindings: usb: tegra-ehci: " Dmitry Osipenko
2020-11-09 19:01 ` Rob Herring
2020-11-04 23:44 ` [PATCH v1 07/30] soc/tegra: Add sync state API Dmitry Osipenko
2020-11-10 20:47 ` Thierry Reding
2020-11-10 21:22 ` Dmitry Osipenko
2020-11-10 21:32 ` Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 08/30] soc/tegra: regulators: Support Tegra SoC device " Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 09/30] soc/tegra: regulators: Fix lockup when voltage-spread is out of range Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 10/30] regulator: Allow skipping disabled regulators in regulator_check_consumers() Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 11/30] drm/tegra: dc: Support OPP and SoC core voltage scaling Dmitry Osipenko
2020-11-10 20:29 ` Thierry Reding
2020-11-10 20:32 ` Mark Brown
2020-11-10 21:23 ` Dmitry Osipenko
2020-11-11 11:55 ` Mark Brown
2020-11-12 16:59 ` Dmitry Osipenko
2020-11-12 17:16 ` Mark Brown
2020-11-12 19:16 ` Dmitry Osipenko
2020-11-12 20:01 ` Mark Brown
2020-11-12 22:37 ` Dmitry Osipenko
2020-11-13 14:29 ` Mark Brown
2020-11-13 15:55 ` Dmitry Osipenko
2020-11-13 16:15 ` Mark Brown
2020-11-13 17:13 ` Dmitry Osipenko
2020-11-13 17:28 ` Mark Brown
2020-11-15 17:42 ` Dmitry Osipenko
2020-11-16 13:33 ` Mark Brown
2020-11-19 14:22 ` Dmitry Osipenko
2020-11-19 15:19 ` Mark Brown
2020-11-13 17:30 ` Thierry Reding
2020-11-10 21:17 ` Dmitry Osipenko
2020-11-10 21:50 ` Dmitry Osipenko
2020-11-11 9:28 ` Dan Carpenter
2020-11-04 23:44 ` [PATCH v1 12/30] drm/tegra: gr2d: Correct swapped device-tree compatibles Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 13/30] drm/tegra: gr2d: Support OPP and SoC core voltage scaling Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 14/30] drm/tegra: gr3d: " Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 15/30] drm/tegra: hdmi: " Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 16/30] gpu: host1x: " Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 17/30] mmc: sdhci-tegra: Support OPP and " Dmitry Osipenko
2020-11-05 9:58 ` Viresh Kumar
2020-11-05 14:18 ` Dmitry Osipenko
2020-11-06 6:15 ` Viresh Kumar
[not found] ` <a6926456-8bce-a438-bfaa-be334208f004@gmail.com>
[not found] ` <CAEExFWsp0DWw1yO84e3vzr_YZkqkd+pyPfQQR3J2W6n3wTX4Jw@mail.gmail.com>
2020-11-09 5:00 ` Viresh Kumar
2020-11-09 5:08 ` Dmitry Osipenko
2020-11-09 5:10 ` Viresh Kumar
2020-11-09 5:19 ` Dmitry Osipenko
2020-11-09 5:35 ` Viresh Kumar
2020-11-09 5:44 ` Dmitry Osipenko
2020-11-09 5:53 ` Viresh Kumar
2020-11-09 11:20 ` Frank Lee
2020-12-22 8:54 ` Viresh Kumar
2020-11-04 23:44 ` [PATCH v1 18/30] pwm: tegra: " Dmitry Osipenko
2020-11-10 20:50 ` Thierry Reding
2020-11-10 21:17 ` Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 19/30] media: staging: tegra-vde: Support OPP and SoC " Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 20/30] usb: chipidea: tegra: " Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 21/30] usb: host: ehci-tegra: " Dmitry Osipenko
2020-11-05 16:07 ` Alan Stern
2020-11-05 17:54 ` Dmitry Osipenko
2020-11-05 18:02 ` Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 22/30] memory: tegra20-emc: Support Tegra SoC device state syncing Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 23/30] memory: tegra30-emc: " Dmitry Osipenko
2020-11-04 23:44 ` Dmitry Osipenko [this message]
2020-11-04 23:44 ` [PATCH v1 25/30] ARM: tegra: Add OPP tables for Tegra30 peripheral devices Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 26/30] ARM: tegra: ventana: Add voltage supplies to DVFS-capable devices Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 27/30] ARM: tegra: paz00: " Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 28/30] ARM: tegra: acer-a500: " Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 29/30] ARM: tegra: cardhu-a04: " Dmitry Osipenko
2020-11-04 23:44 ` [PATCH v1 30/30] ARM: tegra: nexus7: " Dmitry Osipenko
2020-11-05 1:45 ` [PATCH v1 00/30] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs Michał Mirosław
2020-11-05 13:57 ` Dmitry Osipenko
2020-11-05 9:45 ` Ulf Hansson
2020-11-05 10:06 ` Viresh Kumar
2020-11-05 10:34 ` Ulf Hansson
2020-11-05 10:40 ` Viresh Kumar
2020-11-05 10:56 ` Ulf Hansson
2020-11-05 11:13 ` Viresh Kumar
2020-11-05 12:52 ` Ulf Hansson
2020-11-05 15:22 ` Dmitry Osipenko
2020-11-08 12:19 ` Dmitry Osipenko
2020-11-09 4:43 ` Viresh Kumar
2020-11-09 4:47 ` Dmitry Osipenko
2020-11-09 5:10 ` Dmitry Osipenko
2020-11-09 5:12 ` Viresh Kumar
2020-11-11 11:38 ` Ulf Hansson
2020-11-12 19:57 ` Dmitry Osipenko
2020-11-12 20:43 ` Thierry Reding
2020-11-12 22:14 ` Dmitry Osipenko
2020-11-13 14:45 ` Ulf Hansson
2020-11-13 16:00 ` Dmitry Osipenko
2020-11-13 16:35 ` Thierry Reding
2020-11-15 16:29 ` Dmitry Osipenko
2020-12-01 13:57 ` Mark Brown
2020-12-01 14:17 ` Dmitry Osipenko
2020-12-01 14:34 ` Mark Brown
2020-12-01 14:44 ` Dmitry Osipenko
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