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Thu, 14 Jan 2021 06:42:20 -0500 (EST) Date: Thu, 14 Jan 2021 12:42:19 +0100 From: Maxime Ripard To: Giulio Benetti Subject: Re: [PATCH v6] drm/sun4i: tcon: fix inverted DCLK polarity Message-ID: <20210114114219.faulkwww3dhdqwmc@gilmour> References: <20210114081732.9386-1-giulio.benetti@benettiengineering.com> MIME-Version: 1.0 In-Reply-To: <20210114081732.9386-1-giulio.benetti@benettiengineering.com> X-Mailman-Approved-At: Fri, 15 Jan 2021 08:55:00 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jernej Skrabec , airlied@linux.ie, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, wens@csie.org, linux-arm-kernel@lists.infradead.org, treding@nvidia.com, Giulio Benetti , Marjan Pascolo Content-Type: multipart/mixed; boundary="===============1464218736==" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --===============1464218736== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="lcvqz25cpg3ywj2t" Content-Disposition: inline --lcvqz25cpg3ywj2t Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Jan 14, 2021 at 09:17:32AM +0100, Giulio Benetti wrote: > From: Giulio Benetti >=20 > During commit 88bc4178568b ("drm: Use new > DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") DRM_BUS_FLAG_* > macros have been changed to avoid ambiguity but just because of this > ambiguity previous DRM_BUS_FLAG_PIXDATA_(POS/NEG)EDGE were used meaning > _SAMPLE_ not _DRIVE_. This leads to DLCK inversion and need to fix but > instead of swapping phase values, let's adopt an easier approach Maxime > suggested: > It turned out that bit 26 of SUN4I_TCON0_IO_POL_REG is dedicated to > invert DCLK polarity and this makes things really easier than before. So > let's handle DCLK polarity by adding SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE > as bit 26 and activating according to bus_flags the same way it is done > for all the other signals polarity. >=20 > Fixes: 88bc4178568b ("drm: Use new DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG= )EDGE flags") > Suggested-by: Maxime Ripard > Signed-off-by: Giulio Benetti > --- > V2->V3: > - squash 2 patches into 1 > V3->V4: > - add SUN4I_TCON0_IO_POL_DCLK_POSITIVE to regmap_update_bits() as suggest= ed by Maxime > V4->V5: > polarity is still wrong so: > - let's use SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE macro > instead of _DCLK_POSITIVE(that would make sense only in realtion with D= CLK) > - invert condition using _NEGEDGE instead of _POSEDGE and then matching w= ith > register bit SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE > - correct commit log according to V4->V5 changes > V5->V6: > - fix typo in SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE as suggested by Marjan > --- > drivers/gpu/drm/sun4i/sun4i_tcon.c | 21 ++------------------- > drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 + > 2 files changed, 3 insertions(+), 19 deletions(-) >=20 > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/s= un4i_tcon.c > index eaaf5d70e352..6b9af4c08cd6 100644 > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > @@ -569,30 +569,13 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_t= con *tcon, > if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) > val |=3D SUN4I_TCON0_IO_POL_DE_NEGATIVE; > =20 > - /* > - * On A20 and similar SoCs, the only way to achieve Positive Edge > - * (Rising Edge), is setting dclk clock phase to 2/3(240=B0). > - * By default TCON works in Negative Edge(Falling Edge), > - * this is why phase is set to 0 in that case. > - * Unfortunately there's no way to logically invert dclk through > - * IO_POL register. > - * The only acceptable way to work, triple checked with scope, > - * is using clock phase set to 0=B0 for Negative Edge and set to 240=B0 > - * for Positive Edge. > - * On A33 and similar SoCs there would be a 90=B0 phase option, > - * but it divides also dclk by 2. > - * Following code is a way to avoid quirks all around TCON > - * and DOTCLOCK drivers. > - */ > - if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) > - clk_set_phase(tcon->dclk, 240); > - > if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) > - clk_set_phase(tcon->dclk, 0); > + val |=3D SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE; > =20 > regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, > SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | > SUN4I_TCON0_IO_POL_VSYNC_POSITIVE | > + SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE | > SUN4I_TCON0_IO_POL_DE_NEGATIVE, > val); > =20 > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/s= un4i_tcon.h > index cfbf4e6c1679..c5ac1b02482c 100644 > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h > @@ -113,6 +113,7 @@ > #define SUN4I_TCON0_IO_POL_REG 0x88 > #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28) > #define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27) > +#define SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE BIT(26) > #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25) > #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24) > =20 > --=20 > 2.25.1 >=20 Applied, thanks! Maxime --lcvqz25cpg3ywj2t Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYAAuGwAKCRDj7w1vZxhR xaoIAP9OtTnumUDxgNNTQFtC7oOJn1YsBUjkqVZp2fi9J7qkwAD+NE2kvzKlPgZf UYE0jF/kx7nz7FX3odyMJmy16ZDJrA0= =wEvo -----END PGP SIGNATURE----- --lcvqz25cpg3ywj2t-- --===============1464218736== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel --===============1464218736==--