Hi all,

On Mon, 1 Feb 2021 12:30:12 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> 
> Today's linux-next merge of the drm tree got a conflict in:
> 
>   drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> 
> between commit:
> 
>   a119f87b86bc ("Revert "drm/amdgpu/swsmu: drop set_fan_speed_percent (v2)"")
> 
> from Linus' tree and commit:
> 
>   d8a0b8dd690b ("drm/amd/pm: add pptable_funcs documentation (v3)")
> 
> from the drm tree.
> 
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
> 
> diff --cc drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index 0d797fa9f5cc,a087e00382e6..000000000000
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@@ -551,39 -924,199 +924,201 @@@ struct pptable_funcs 
>   	int (*display_clock_voltage_request)(struct smu_context *smu, struct
>   					     pp_display_clock_request
>   					     *clock_req);
> + 
> + 	/**
> + 	 * @get_fan_control_mode: Get the current fan control mode.
> + 	 */
>   	uint32_t (*get_fan_control_mode)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @set_fan_control_mode: Set the fan control mode.
> + 	 */
>   	int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
> + 
>  +	int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
> ++
> + 	/**
> + 	 * @set_fan_speed_rpm: Set a static fan speed in RPM.
> + 	 */
>   	int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
> + 
> + 	/**
> + 	 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
> + 	 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
> + 	 */
>   	int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
> + 
> + 	/**
> + 	 * @gfx_off_control: Enable/disable graphics engine poweroff.
> + 	 */
>   	int (*gfx_off_control)(struct smu_context *smu, bool enable);
> + 
> + 
> + 	/**
> + 	 * @get_gfx_off_status: Get graphics engine poweroff status.
> + 	 *
> + 	 * Return:
> + 	 * 0 - GFXOFF(default).
> + 	 * 1 - Transition out of GFX State.
> + 	 * 2 - Not in GFXOFF.
> + 	 * 3 - Transition into GFXOFF.
> + 	 */
>   	uint32_t (*get_gfx_off_status)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @register_irq_handler: Register interupt request handlers.
> + 	 */
>   	int (*register_irq_handler)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep.
> + 	 */
>   	int (*set_azalia_d3_pme)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable
> + 	 *                                    clock speeds table.
> + 	 *
> + 	 * Provides a way for the display component (DC) to get the max
> + 	 * sustainable clocks from the SMU.
> + 	 */
>   	int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
> + 
> + 	/**
> + 	 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off).
> + 	 */
>   	bool (*baco_is_support)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @baco_get_state: Get the current BACO state.
> + 	 *
> + 	 * Return: Current BACO state.
> + 	 */
>   	enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @baco_set_state: Enter/exit BACO.
> + 	 */
>   	int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
> + 
> + 	/**
> + 	 * @baco_enter: Enter BACO.
> + 	 */
>   	int (*baco_enter)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @baco_exit: Exit Baco.
> + 	 */
>   	int (*baco_exit)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @mode1_reset_is_support: Check if GPU supports mode1 reset.
> + 	 */
>   	bool (*mode1_reset_is_support)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @mode1_reset: Perform mode1 reset.
> + 	 *
> + 	 * Complete GPU reset.
> + 	 */
>   	int (*mode1_reset)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @mode2_reset: Perform mode2 reset.
> + 	 *
> + 	 * Mode2 reset generally does not reset as many IPs as mode1 reset. The
> + 	 * IPs reset varies by asic.
> + 	 */
>   	int (*mode2_reset)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock
> + 	 *                         domain in MHz.
> + 	 */
>   	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
> + 
> + 	/**
> + 	 * @set_soft_freq_limited_range: Set the soft frequency range of a clock
> + 	 *                               domain in MHz.
> + 	 */
>   	int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
> + 
> + 	/**
> + 	 * @set_power_source: Notify the SMU of the current power source.
> + 	 */
>   	int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
> + 
> + 	/**
> + 	 * @log_thermal_throttling_event: Print a thermal throttling warning to
> + 	 *                                the system's log.
> + 	 */
>   	void (*log_thermal_throttling_event)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @get_pp_feature_mask: Print a human readable table of enabled
> + 	 *                       features to buffer.
> + 	 */
>   	size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
> + 
> + 	/**
> + 	 * @set_pp_feature_mask: Request the SMU enable/disable features to
> + 	 *                       match those enabled in &new_mask.
> + 	 */
>   	int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
> + 
> + 	/**
> + 	 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU.
> + 	 *
> + 	 * Return: Size of &table
> + 	 */
>   	ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
> + 
> + 	/**
> + 	 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost.
> + 	 */
>   	int (*enable_mgpu_fan_boost)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @gfx_ulv_control: Enable/disable ultra low voltage.
> + 	 */
>   	int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
> + 
> + 	/**
> + 	 * @deep_sleep_control: Enable/disable deep sleep.
> + 	 */
>   	int (*deep_sleep_control)(struct smu_context *smu, bool enablement);
> + 
> + 	/**
> + 	 * @get_fan_parameters: Get fan parameters.
> + 	 *
> + 	 * Get maximum fan speed from the power play table.
> + 	 */
>   	int (*get_fan_parameters)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @post_init: Helper function for asic specific workarounds.
> + 	 */
>   	int (*post_init)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @interrupt_work: Work task scheduled from SMU interrupt handler.
> + 	 */
>   	void (*interrupt_work)(struct smu_context *smu);
> + 
> + 	/**
> + 	 * @gpo_control: Enable/disable graphics power optimization if supported.
> + 	 */
>   	int (*gpo_control)(struct smu_context *smu, bool enablement);
> + 
> + 	/**
> + 	 * @gfx_state_change_set: Send the current graphics state to the SMU.
> + 	 */
>   	int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
> + 
> + 	/**
> + 	 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock
> + 	 *                                      parameters to defaults.
> + 	 */
>   	int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
>   };
>   

With the merge window about to open, this is a reminder that this
conflict still exists.

-- 
Cheers,
Stephen Rothwell