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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org, dri-devel@lists.freedesktop.org,
	Chris Wilson <chris@chris-wilson.co.uk>
Subject: [PATCH 1/4] drm/i915: Avoid div-by-zero on gen2
Date: Wed, 21 Apr 2021 18:33:58 +0300	[thread overview]
Message-ID: <20210421153401.13847-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210421153401.13847-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Gen2 tiles are 2KiB in size so i915_gem_object_get_tile_row_size()
can in fact return <4KiB, which leads to div-by-zero here.
Avoid that.

Not sure i915_gem_object_get_tile_row_size() is entirely
sane anyway since it doesn't account for the different tile
layouts on i8xx/i915...

I'm not able to hit this before commit 6846895fde05 ("drm/i915:
Replace PIN_NONFAULT with calls to PIN_NOEVICT") and it looks
like I also need to run recent version of Mesa. With those in
place xonotic trips on this quite easily on my 85x.

Cc: stable@vger.kernel.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 2561a2f1e54f..8598a1c78a4c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj,
 	struct i915_ggtt_view view;
 
 	if (i915_gem_object_is_tiled(obj))
-		chunk = roundup(chunk, tile_row_pages(obj));
+		chunk = roundup(chunk, tile_row_pages(obj) ?: 1);
 
 	view.type = I915_GGTT_VIEW_PARTIAL;
 	view.partial.offset = rounddown(page_offset, chunk);
-- 
2.26.3

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  reply	other threads:[~2021-04-21 15:34 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-21 15:33 [PATCH 0/4] drm/i915: Fix older platforms Ville Syrjala
2021-04-21 15:33 ` Ville Syrjala [this message]
2021-04-21 15:33 ` [PATCH 2/4] drm/i915: Read C0DRB3/C1DRB3 as 16 bits again Ville Syrjala
2021-04-21 15:34 ` [PATCH 3/4] drm/i915: Give C0DRB3/C1DRB3 a _BW suffix Ville Syrjala
2021-04-21 15:34 ` [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection Ville Syrjala
2021-04-22  9:49   ` [Intel-gfx] " Daniel Vetter
2021-04-22 13:11     ` Ville Syrjälä
2021-04-26 16:08       ` Daniel Vetter
2021-04-26 17:18         ` Ville Syrjälä
2021-04-27  8:58           ` Daniel Vetter
2021-10-04 10:36             ` Ville Syrjälä
2021-04-22 18:51     ` Ville Syrjälä

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