From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, Chris Wilson <chris@chris-wilson.co.uk>
Subject: [PATCH 2/4] drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
Date: Wed, 21 Apr 2021 18:33:59 +0300 [thread overview]
Message-ID: <20210421153401.13847-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210421153401.13847-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We've defined C0DRB3/C0DRB3 as 16 bit registers, so access them
as such.
Fixes: 1c8242c3a4b2 ("drm/i915: Use unchecked writes for setting up the fences")
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index e72b7a0dc316..8a322594210c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
* banks of memory are paired and unswizzled on the
* uneven portion, so leave that as unknown.
*/
- if (intel_uncore_read(uncore, C0DRB3) ==
- intel_uncore_read(uncore, C1DRB3)) {
+ if (intel_uncore_read16(uncore, C0DRB3) ==
+ intel_uncore_read16(uncore, C1DRB3)) {
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
}
--
2.26.3
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next prev parent reply other threads:[~2021-04-21 15:34 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-21 15:33 [PATCH 0/4] drm/i915: Fix older platforms Ville Syrjala
2021-04-21 15:33 ` [PATCH 1/4] drm/i915: Avoid div-by-zero on gen2 Ville Syrjala
2021-04-21 15:33 ` Ville Syrjala [this message]
2021-04-21 15:34 ` [PATCH 3/4] drm/i915: Give C0DRB3/C1DRB3 a _BW suffix Ville Syrjala
2021-04-21 15:34 ` [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection Ville Syrjala
2021-04-22 9:49 ` [Intel-gfx] " Daniel Vetter
2021-04-22 13:11 ` Ville Syrjälä
2021-04-26 16:08 ` Daniel Vetter
2021-04-26 17:18 ` Ville Syrjälä
2021-04-27 8:58 ` Daniel Vetter
2021-10-04 10:36 ` Ville Syrjälä
2021-04-22 18:51 ` Ville Syrjälä
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