* [PATCH 1/7] drm/i915/dg1: Fix mapping type for default state object
@ 2021-04-26 10:18 Matthew Auld
2021-04-26 10:18 ` [PATCH 2/7] drm/i915: Update the helper to set correct mapping Matthew Auld
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Matthew Auld @ 2021-04-26 10:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Venkata Ramana Nayana, dri-devel
From: Venkata Ramana Nayana <venkata.ramana.nayana@intel.com>
Use I915_MAP_WC when default state object is allocated in LMEM.
Signed-off-by: Venkata Ramana Nayana <venkata.ramana.nayana@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gt/shmem_utils.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c b/drivers/gpu/drm/i915/gt/shmem_utils.c
index f8f02aab842b..0683b27a3890 100644
--- a/drivers/gpu/drm/i915/gt/shmem_utils.c
+++ b/drivers/gpu/drm/i915/gt/shmem_utils.c
@@ -8,6 +8,7 @@
#include <linux/shmem_fs.h>
#include "gem/i915_gem_object.h"
+#include "gem/i915_gem_lmem.h"
#include "shmem_utils.h"
struct file *shmem_create_from_data(const char *name, void *data, size_t len)
@@ -39,7 +40,8 @@ struct file *shmem_create_from_object(struct drm_i915_gem_object *obj)
return file;
}
- ptr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
+ ptr = i915_gem_object_pin_map_unlocked(obj, i915_gem_object_is_lmem(obj) ?
+ I915_MAP_WC : I915_MAP_WB);
if (IS_ERR(ptr))
return ERR_CAST(ptr);
--
2.26.3
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/7] drm/i915: Update the helper to set correct mapping
2021-04-26 10:18 [PATCH 1/7] drm/i915/dg1: Fix mapping type for default state object Matthew Auld
@ 2021-04-26 10:18 ` Matthew Auld
2021-04-26 10:18 ` [PATCH 3/7] drm/i915/gtt: map the PD up front Matthew Auld
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Matthew Auld @ 2021-04-26 10:18 UTC (permalink / raw)
To: intel-gfx
Cc: Tvrtko Ursulin, CQ Tang, Venkata Sandeep Dhanalakota, dri-devel,
Michal Wajdeczko
From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Determine the possible coherent map type based on object location,
and if target has llc or if user requires an always coherent
mapping.
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: CQ Tang <cq.tang@intel.com>
Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
drivers/gpu/drm/i915/gt/intel_ring.c | 9 ++++++---
drivers/gpu/drm/i915/gt/selftest_context.c | 3 ++-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4 +++-
drivers/gpu/drm/i915/i915_drv.h | 11 +++++++++--
drivers/gpu/drm/i915/selftests/igt_spinner.c | 4 ++--
10 files changed, 34 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 7c9af86fdb1e..47f4397095e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -23,7 +23,7 @@ static void dbg_poison_ce(struct intel_context *ce)
if (ce->state) {
struct drm_i915_gem_object *obj = ce->state->obj;
- int type = i915_coherent_map_type(ce->engine->i915);
+ int type = i915_coherent_map_type(ce->engine->i915, obj, true);
void *map;
if (!i915_gem_object_trylock(obj))
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e86897cde984..aafe2a4df496 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -903,7 +903,9 @@ lrc_pre_pin(struct intel_context *ce,
GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
*vaddr = i915_gem_object_pin_map(ce->state->obj,
- i915_coherent_map_type(ce->engine->i915) |
+ i915_coherent_map_type(ce->engine->i915,
+ ce->state->obj,
+ false) |
I915_MAP_OVERRIDE);
return PTR_ERR_OR_ZERO(*vaddr);
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c
index aee0a77c77e0..3cf6c7e68108 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -53,9 +53,12 @@ int intel_ring_pin(struct intel_ring *ring, struct i915_gem_ww_ctx *ww)
if (i915_vma_is_map_and_fenceable(vma))
addr = (void __force *)i915_vma_pin_iomap(vma);
- else
- addr = i915_gem_object_pin_map(vma->obj,
- i915_coherent_map_type(vma->vm->i915));
+ else {
+ int type = i915_coherent_map_type(vma->vm->i915, vma->obj, false);
+
+ addr = i915_gem_object_pin_map(vma->obj, type);
+ }
+
if (IS_ERR(addr)) {
ret = PTR_ERR(addr);
goto err_ring;
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c b/drivers/gpu/drm/i915/gt/selftest_context.c
index b9bdd1d23243..26685b927169 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -88,7 +88,8 @@ static int __live_context_size(struct intel_engine_cs *engine)
goto err;
vaddr = i915_gem_object_pin_map_unlocked(ce->state->obj,
- i915_coherent_map_type(engine->i915));
+ i915_coherent_map_type(engine->i915,
+ ce->state->obj, false));
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);
intel_context_unpin(ce);
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 746985971c3a..5b63d4df8c93 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -69,7 +69,7 @@ static int hang_init(struct hang *h, struct intel_gt *gt)
h->seqno = memset(vaddr, 0xff, PAGE_SIZE);
vaddr = i915_gem_object_pin_map_unlocked(h->obj,
- i915_coherent_map_type(gt->i915));
+ i915_coherent_map_type(gt->i915, h->obj, false));
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);
goto err_unpin_hws;
@@ -130,7 +130,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
return ERR_CAST(obj);
}
- vaddr = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt->i915));
+ vaddr = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt->i915, obj, false));
if (IS_ERR(vaddr)) {
i915_gem_object_put(obj);
i915_vm_put(vm);
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 85e7df6a5123..d8f6623524e8 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1221,7 +1221,9 @@ static int compare_isolation(struct intel_engine_cs *engine,
}
lrc = i915_gem_object_pin_map_unlocked(ce->state->obj,
- i915_coherent_map_type(engine->i915));
+ i915_coherent_map_type(engine->i915,
+ ce->state->obj,
+ false));
if (IS_ERR(lrc)) {
err = PTR_ERR(lrc);
goto err_B1;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 78305b2ec89d..adae04c47aab 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -682,7 +682,9 @@ int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size,
if (IS_ERR(vma))
return PTR_ERR(vma);
- vaddr = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WB);
+ vaddr = i915_gem_object_pin_map_unlocked(vma->obj,
+ i915_coherent_map_type(guc_to_gt(guc)->i915,
+ vma->obj, true));
if (IS_ERR(vaddr)) {
i915_vma_unpin_and_release(&vma, 0);
return PTR_ERR(vaddr);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 2126dd81ac38..56d2144dc6a0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -82,7 +82,9 @@ static int intel_huc_rsa_data_create(struct intel_huc *huc)
if (IS_ERR(vma))
return PTR_ERR(vma);
- vaddr = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WB);
+ vaddr = i915_gem_object_pin_map_unlocked(vma->obj,
+ i915_coherent_map_type(gt->i915,
+ vma->obj, true));
if (IS_ERR(vaddr)) {
i915_vma_unpin_and_release(&vma, 0);
return PTR_ERR(vaddr);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0b44333eb703..336b09f38aad 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -78,6 +78,7 @@
#include "gem/i915_gem_context_types.h"
#include "gem/i915_gem_shrinker.h"
#include "gem/i915_gem_stolen.h"
+#include "gem/i915_gem_lmem.h"
#include "gt/intel_engine.h"
#include "gt/intel_gt_types.h"
@@ -1936,9 +1937,15 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
}
static inline enum i915_map_type
-i915_coherent_map_type(struct drm_i915_private *i915)
+i915_coherent_map_type(struct drm_i915_private *i915,
+ struct drm_i915_gem_object *obj, bool always_coherent)
{
- return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
+ if (i915_gem_object_is_lmem(obj))
+ return I915_MAP_WC;
+ if (HAS_LLC(i915) || always_coherent)
+ return I915_MAP_WB;
+ else
+ return I915_MAP_WC;
}
#endif
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index cfbbe415b57c..5fe397b7d1d9 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -94,9 +94,9 @@ int igt_spinner_pin(struct igt_spinner *spin,
}
if (!spin->batch) {
- unsigned int mode =
- i915_coherent_map_type(spin->gt->i915);
+ unsigned int mode;
+ mode = i915_coherent_map_type(spin->gt->i915, spin->obj, false);
vaddr = igt_spinner_pin_obj(ce, ww, spin->obj, mode, &spin->batch_vma);
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
--
2.26.3
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/7] drm/i915/gtt: map the PD up front
2021-04-26 10:18 [PATCH 1/7] drm/i915/dg1: Fix mapping type for default state object Matthew Auld
2021-04-26 10:18 ` [PATCH 2/7] drm/i915: Update the helper to set correct mapping Matthew Auld
@ 2021-04-26 10:18 ` Matthew Auld
2021-04-26 15:20 ` Tvrtko Ursulin
2021-04-26 10:18 ` [PATCH 4/7] drm/i915/gtt/dgfx: place the PD in LMEM Matthew Auld
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Matthew Auld @ 2021-04-26 10:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Tvrtko Ursulin, dri-devel, Chris Wilson
We need to general our accessor for the page directories and tables from
using the simple kmap_atomic to support local memory, and this setup
must be done on acquisition of the backing storage prior to entering
fence execution contexts. Here we replace the kmap with the object
maping code that for simple single page shmemfs object will return a
plain kmap, that is then kept for the lifetime of the page directory.
v2: (Thomas) Rebase on dma_resv and obj->mm.lock removal.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
.../drm/i915/gem/selftests/i915_gem_context.c | 11 +----
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 11 ++---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 26 ++++------
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 48 +++++++++----------
drivers/gpu/drm/i915/gt/intel_gtt.h | 11 +++--
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 7 ++-
drivers/gpu/drm/i915/i915_vma.c | 3 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 10 ++--
drivers/gpu/drm/i915/selftests/i915_perf.c | 3 +-
10 files changed, 54 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 5fef592390cb..ce70d0a3afb2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1740,7 +1740,6 @@ static int read_from_scratch(struct i915_gem_context *ctx,
static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
{
struct i915_address_space *vm;
- struct page *page;
u32 *vaddr;
int err = 0;
@@ -1748,24 +1747,18 @@ static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
if (!vm)
return -ENODEV;
- page = __px_page(vm->scratch[0]);
- if (!page) {
+ if (!vm->scratch[0]) {
pr_err("No scratch page!\n");
return -EINVAL;
}
- vaddr = kmap(page);
- if (!vaddr) {
- pr_err("No (mappable) scratch page!\n");
- return -EINVAL;
- }
+ vaddr = __px_vaddr(vm->scratch[0]);
memcpy(out, vaddr, sizeof(*out));
if (memchr_inv(vaddr, *out, PAGE_SIZE)) {
pr_err("Inconsistent initial state of scratch page!\n");
err = -EINVAL;
}
- kunmap(page);
return err;
}
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index e08dff376339..21b1085769be 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -96,9 +96,8 @@ static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
* entries back to scratch.
*/
- vaddr = kmap_atomic_px(pt);
+ vaddr = px_vaddr(pt);
memset32(vaddr + pte, scratch_pte, count);
- kunmap_atomic(vaddr);
pte = 0;
}
@@ -120,7 +119,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
GEM_BUG_ON(!pd->entry[act_pt]);
- vaddr = kmap_atomic_px(i915_pt_entry(pd, act_pt));
+ vaddr = px_vaddr(i915_pt_entry(pd, act_pt));
do {
GEM_BUG_ON(sg_dma_len(iter.sg) < I915_GTT_PAGE_SIZE);
vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
@@ -136,12 +135,10 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
}
if (++act_pte == GEN6_PTES) {
- kunmap_atomic(vaddr);
- vaddr = kmap_atomic_px(i915_pt_entry(pd, ++act_pt));
+ vaddr = px_vaddr(i915_pt_entry(pd, ++act_pt));
act_pte = 0;
}
} while (1);
- kunmap_atomic(vaddr);
vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
}
@@ -235,7 +232,7 @@ static int gen6_ppgtt_init_scratch(struct gen6_ppgtt *ppgtt)
goto err_scratch0;
}
- ret = pin_pt_dma(vm, vm->scratch[1]);
+ ret = map_pt_dma(vm, vm->scratch[1]);
if (ret)
goto err_scratch1;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 176c19633412..f83496836f0f 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -242,11 +242,10 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm,
atomic_read(&pt->used));
GEM_BUG_ON(!count || count >= atomic_read(&pt->used));
- vaddr = kmap_atomic_px(pt);
+ vaddr = px_vaddr(pt);
memset64(vaddr + gen8_pd_index(start, 0),
vm->scratch[0]->encode,
count);
- kunmap_atomic(vaddr);
atomic_sub(count, &pt->used);
start += count;
@@ -375,7 +374,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
gen8_pte_t *vaddr;
pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
- vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
+ vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
do {
GEM_BUG_ON(sg_dma_len(iter->sg) < I915_GTT_PAGE_SIZE);
vaddr[gen8_pd_index(idx, 0)] = pte_encode | iter->dma;
@@ -402,12 +401,10 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
}
clflush_cache_range(vaddr, PAGE_SIZE);
- kunmap_atomic(vaddr);
- vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
+ vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
}
} while (1);
clflush_cache_range(vaddr, PAGE_SIZE);
- kunmap_atomic(vaddr);
return idx;
}
@@ -442,7 +439,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
encode |= GEN8_PDE_PS_2M;
page_size = I915_GTT_PAGE_SIZE_2M;
- vaddr = kmap_atomic_px(pd);
+ vaddr = px_vaddr(pd);
} else {
struct i915_page_table *pt =
i915_pt_entry(pd, __gen8_pte_index(start, 1));
@@ -457,7 +454,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE))
maybe_64K = __gen8_pte_index(start, 1);
- vaddr = kmap_atomic_px(pt);
+ vaddr = px_vaddr(pt);
}
do {
@@ -491,7 +488,6 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
} while (rem >= page_size && index < I915_PDES);
clflush_cache_range(vaddr, PAGE_SIZE);
- kunmap_atomic(vaddr);
/*
* Is it safe to mark the 2M block as 64K? -- Either we have
@@ -505,9 +501,8 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
!iter->sg && IS_ALIGNED(vma->node.start +
vma->node.size,
I915_GTT_PAGE_SIZE_2M)))) {
- vaddr = kmap_atomic_px(pd);
+ vaddr = px_vaddr(pd);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
- kunmap_atomic(vaddr);
page_size = I915_GTT_PAGE_SIZE_64K;
/*
@@ -523,12 +518,11 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
u16 i;
encode = vma->vm->scratch[0]->encode;
- vaddr = kmap_atomic_px(i915_pt_entry(pd, maybe_64K));
+ vaddr = px_vaddr(i915_pt_entry(pd, maybe_64K));
for (i = 1; i < index; i += 16)
memset64(vaddr + i, encode, 15);
- kunmap_atomic(vaddr);
}
}
@@ -602,7 +596,7 @@ static int gen8_init_scratch(struct i915_address_space *vm)
if (IS_ERR(obj))
goto free_scratch;
- ret = pin_pt_dma(vm, obj);
+ ret = map_pt_dma(vm, obj);
if (ret) {
i915_gem_object_put(obj);
goto free_scratch;
@@ -639,7 +633,7 @@ static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt)
if (IS_ERR(pde))
return PTR_ERR(pde);
- err = pin_pt_dma(vm, pde->pt.base);
+ err = map_pt_dma(vm, pde->pt.base);
if (err) {
i915_gem_object_put(pde->pt.base);
free_pd(vm, pde);
@@ -675,7 +669,7 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
goto err_pd;
}
- err = pin_pt_dma(vm, pd->pt.base);
+ err = map_pt_dma(vm, pd->pt.base);
if (err)
goto err_pd;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 670c1271e7d5..d94628b9d89e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -657,7 +657,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
goto err_ppgtt;
i915_gem_object_lock(ppgtt->vm.scratch[0], NULL);
- err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
+ err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
i915_gem_object_unlock(ppgtt->vm.scratch[0]);
if (err)
goto err_stash;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 941f8af016d6..d386b89e2758 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -25,27 +25,25 @@ struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz)
return obj;
}
-int pin_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
+int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
{
- int err;
+ void *vaddr;
- i915_gem_object_lock(obj, NULL);
- err = i915_gem_object_pin_pages(obj);
- i915_gem_object_unlock(obj);
- if (err)
- return err;
+ vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
i915_gem_object_make_unshrinkable(obj);
return 0;
}
-int pin_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
+int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
{
- int err;
+ void *vaddr;
- err = i915_gem_object_pin_pages(obj);
- if (err)
- return err;
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
i915_gem_object_make_unshrinkable(obj);
return 0;
@@ -155,6 +153,14 @@ void clear_pages(struct i915_vma *vma)
memset(&vma->page_sizes, 0, sizeof(vma->page_sizes));
}
+void *__px_vaddr(struct drm_i915_gem_object *p)
+{
+ enum i915_map_type type;
+
+ GEM_BUG_ON(!i915_gem_object_has_pages(p));
+ return page_unpack_bits(p->mm.mapping, &type);
+}
+
dma_addr_t __px_dma(struct drm_i915_gem_object *p)
{
GEM_BUG_ON(!i915_gem_object_has_pages(p));
@@ -170,32 +176,22 @@ struct page *__px_page(struct drm_i915_gem_object *p)
void
fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
{
- struct page *page = __px_page(p);
- void *vaddr;
+ void *vaddr = __px_vaddr(p);
- vaddr = kmap(page);
memset64(vaddr, val, count);
clflush_cache_range(vaddr, PAGE_SIZE);
- kunmap(page);
}
static void poison_scratch_page(struct drm_i915_gem_object *scratch)
{
- struct sgt_iter sgt;
- struct page *page;
+ void *vaddr = __px_vaddr(scratch);
u8 val;
val = 0;
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
val = POISON_FREE;
- for_each_sgt_page(page, sgt, scratch->mm.pages) {
- void *vaddr;
-
- vaddr = kmap(page);
- memset(vaddr, val, PAGE_SIZE);
- kunmap(page);
- }
+ memset(vaddr, val, scratch->base.size);
}
int setup_scratch_page(struct i915_address_space *vm)
@@ -225,7 +221,7 @@ int setup_scratch_page(struct i915_address_space *vm)
if (IS_ERR(obj))
goto skip;
- if (pin_pt_dma(vm, obj))
+ if (map_pt_dma(vm, obj))
goto skip_obj;
/* We need a single contiguous page for our scratch */
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index e67e34e17913..40e486704558 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -180,6 +180,9 @@ struct page *__px_page(struct drm_i915_gem_object *p);
dma_addr_t __px_dma(struct drm_i915_gem_object *p);
#define px_dma(px) (__px_dma(px_base(px)))
+void *__px_vaddr(struct drm_i915_gem_object *p);
+#define px_vaddr(px) (__px_vaddr(px_base(px)))
+
#define px_pt(px) \
__px_choose_expr(px, struct i915_page_table *, __x, \
__px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
@@ -511,8 +514,6 @@ struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
void i915_ggtt_suspend(struct i915_ggtt *gtt);
void i915_ggtt_resume(struct i915_ggtt *ggtt);
-#define kmap_atomic_px(px) kmap_atomic(__px_page(px_base(px)))
-
void
fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count);
@@ -530,8 +531,8 @@ struct i915_page_table *alloc_pt(struct i915_address_space *vm);
struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
struct i915_page_directory *__alloc_pd(int npde);
-int pin_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
-int pin_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
+int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
+int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
void free_px(struct i915_address_space *vm,
struct i915_page_table *pt, int lvl);
@@ -578,7 +579,7 @@ void setup_private_pat(struct intel_uncore *uncore);
int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
struct i915_vm_pt_stash *stash,
u64 size);
-int i915_vm_pin_pt_stash(struct i915_address_space *vm,
+int i915_vm_map_pt_stash(struct i915_address_space *vm,
struct i915_vm_pt_stash *stash);
void i915_vm_free_pt_stash(struct i915_address_space *vm,
struct i915_vm_pt_stash *stash);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 014ae8ac4480..4e3d80c2295c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -87,11 +87,10 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
const unsigned short idx,
const u64 encoded_entry)
{
- u64 * const vaddr = kmap_atomic(__px_page(pdma));
+ u64 * const vaddr = __px_vaddr(pdma);
vaddr[idx] = encoded_entry;
clflush_cache_range(&vaddr[idx], sizeof(u64));
- kunmap_atomic(vaddr);
}
void
@@ -258,7 +257,7 @@ int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
return 0;
}
-int i915_vm_pin_pt_stash(struct i915_address_space *vm,
+int i915_vm_map_pt_stash(struct i915_address_space *vm,
struct i915_vm_pt_stash *stash)
{
struct i915_page_table *pt;
@@ -266,7 +265,7 @@ int i915_vm_pin_pt_stash(struct i915_address_space *vm,
for (n = 0; n < ARRAY_SIZE(stash->pt); n++) {
for (pt = stash->pt[n]; pt; pt = pt->stash) {
- err = pin_pt_dma_locked(vm, pt->base);
+ err = map_pt_dma_locked(vm, pt->base);
if (err)
return err;
}
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 07490db51cdc..eb01899ac6b7 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -905,8 +905,7 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
if (err)
goto err_fence;
- err = i915_vm_pin_pt_stash(vma->vm,
- &work->stash);
+ err = i915_vm_map_pt_stash(vma->vm, &work->stash);
if (err)
goto err_fence;
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 2e4f06eaacc1..e060e455e9f6 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -186,7 +186,7 @@ static int igt_ppgtt_alloc(void *arg)
if (err)
goto err_ppgtt_cleanup;
- err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
+ err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
if (err) {
i915_vm_free_pt_stash(&ppgtt->vm, &stash);
goto err_ppgtt_cleanup;
@@ -208,7 +208,7 @@ static int igt_ppgtt_alloc(void *arg)
if (err)
goto err_ppgtt_cleanup;
- err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
+ err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
if (err) {
i915_vm_free_pt_stash(&ppgtt->vm, &stash);
goto err_ppgtt_cleanup;
@@ -325,11 +325,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
BIT_ULL(size)))
goto alloc_vm_end;
- err = i915_vm_pin_pt_stash(vm, &stash);
+ err = i915_vm_map_pt_stash(vm, &stash);
if (!err)
vm->allocate_va_range(vm, &stash,
addr, BIT_ULL(size));
-
i915_vm_free_pt_stash(vm, &stash);
alloc_vm_end:
if (err == -EDEADLK) {
@@ -1967,10 +1966,9 @@ static int igt_cs_tlb(void *arg)
if (err)
goto end_ww;
- err = i915_vm_pin_pt_stash(vm, &stash);
+ err = i915_vm_map_pt_stash(vm, &stash);
if (!err)
vm->allocate_va_range(vm, &stash, offset, chunk_size);
-
i915_vm_free_pt_stash(vm, &stash);
end_ww:
if (err == -EDEADLK) {
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
index e9d86dab8677..bfb0290967a1 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
@@ -307,7 +307,7 @@ static int live_noa_gpr(void *arg)
}
/* Poison the ce->vm so we detect writes not to the GGTT gt->scratch */
- scratch = kmap(__px_page(ce->vm->scratch[0]));
+ scratch = __px_vaddr(ce->vm->scratch[0]);
memset(scratch, POISON_FREE, PAGE_SIZE);
rq = intel_context_create_request(ce);
@@ -405,7 +405,6 @@ static int live_noa_gpr(void *arg)
out_rq:
i915_request_put(rq);
out_ce:
- kunmap(__px_page(ce->vm->scratch[0]));
intel_context_put(ce);
out:
stream_destroy(stream);
--
2.26.3
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/7] drm/i915/gtt/dgfx: place the PD in LMEM
2021-04-26 10:18 [PATCH 1/7] drm/i915/dg1: Fix mapping type for default state object Matthew Auld
2021-04-26 10:18 ` [PATCH 2/7] drm/i915: Update the helper to set correct mapping Matthew Auld
2021-04-26 10:18 ` [PATCH 3/7] drm/i915/gtt: map the PD up front Matthew Auld
@ 2021-04-26 10:18 ` Matthew Auld
2021-04-26 15:22 ` Tvrtko Ursulin
2021-04-26 10:18 ` [PATCH 5/7] drm/i915/fbdev: Use lmem physical addresses for fb_mmap() on discrete Matthew Auld
` (2 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Matthew Auld @ 2021-04-26 10:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Tvrtko Ursulin, dri-devel
It's a requirement that for dgfx we place all the paging structures in
device local-memory.
v2: use i915_coherent_map_type()
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 ++++-
drivers/gpu/drm/i915/gt/intel_gtt.c | 21 +++++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_gtt.h | 1 +
3 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index f83496836f0f..11fb5df45a0f 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -712,7 +712,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
*/
ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
- ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
+ if (HAS_LMEM(gt->i915))
+ ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
+ else
+ ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
err = gen8_init_scratch(&ppgtt->vm);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index d386b89e2758..bbe5b09e59ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -7,10 +7,23 @@
#include <linux/fault-inject.h>
+#include "gem/i915_gem_lmem.h"
#include "i915_trace.h"
#include "intel_gt.h"
#include "intel_gtt.h"
+struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
+{
+ struct drm_i915_gem_object *obj;
+
+ obj = i915_gem_object_create_lmem(vm->i915, sz, 0);
+
+ /* ensure all dma objects have the same reservation class */
+ if (!IS_ERR(obj))
+ obj->base.resv = &vm->resv;
+ return obj;
+}
+
struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz)
{
struct drm_i915_gem_object *obj;
@@ -27,9 +40,11 @@ struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz)
int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
{
+ enum i915_map_type type;
void *vaddr;
- vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
+ type = i915_coherent_map_type(vm->i915, obj, true);
+ vaddr = i915_gem_object_pin_map_unlocked(obj, type);
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
@@ -39,9 +54,11 @@ int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
{
+ enum i915_map_type type;
void *vaddr;
- vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ type = i915_coherent_map_type(vm->i915, obj, true);
+ vaddr = i915_gem_object_pin_map(obj, type);
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 40e486704558..44ce27c51631 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -527,6 +527,7 @@ int setup_scratch_page(struct i915_address_space *vm);
void free_scratch(struct i915_address_space *vm);
struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz);
+struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz);
struct i915_page_table *alloc_pt(struct i915_address_space *vm);
struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
struct i915_page_directory *__alloc_pd(int npde);
--
2.26.3
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/7] drm/i915/fbdev: Use lmem physical addresses for fb_mmap() on discrete
2021-04-26 10:18 [PATCH 1/7] drm/i915/dg1: Fix mapping type for default state object Matthew Auld
` (2 preceding siblings ...)
2021-04-26 10:18 ` [PATCH 4/7] drm/i915/gtt/dgfx: place the PD in LMEM Matthew Auld
@ 2021-04-26 10:18 ` Matthew Auld
2021-04-26 10:18 ` [PATCH 6/7] drm/i915/lmem: Bypass aperture when lmem is available Matthew Auld
2021-04-26 10:18 ` [PATCH 7/7] drm/i915: Return error value when bo not in LMEM for discrete Matthew Auld
5 siblings, 0 replies; 12+ messages in thread
From: Matthew Auld @ 2021-04-26 10:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Mohammed Khajapasha, dri-devel
From: Mohammed Khajapasha <mohammed.khajapasha@intel.com>
Use local memory io BAR address for fbdev's fb_mmap() operation on
discrete, fbdev uses the physical address of our framebuffer for its
fb_mmap() fn.
Signed-off-by: Mohammed Khajapasha <mohammed.khajapasha@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 29 +++++++++++++++++-----
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index ccd00e65a5fe..2b37959da747 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -41,6 +41,8 @@
#include <drm/drm_fb_helper.h>
#include <drm/drm_fourcc.h>
+#include "gem/i915_gem_lmem.h"
+
#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_fbdev.h"
@@ -178,6 +180,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
unsigned long flags = 0;
bool prealloc = false;
void __iomem *vaddr;
+ struct drm_i915_gem_object *obj;
int ret;
if (intel_fb &&
@@ -232,13 +235,27 @@ static int intelfb_create(struct drm_fb_helper *helper,
info->fbops = &intelfb_ops;
/* setup aperture base/size for vesafb takeover */
- info->apertures->ranges[0].base = ggtt->gmadr.start;
- info->apertures->ranges[0].size = ggtt->mappable_end;
+ obj = intel_fb_obj(&intel_fb->base);
+ if (i915_gem_object_is_lmem(obj)) {
+ struct intel_memory_region *mem = obj->mm.region;
+
+ info->apertures->ranges[0].base = mem->io_start;
+ info->apertures->ranges[0].size = mem->total;
+
+ /* Use fbdev's framebuffer from lmem for discrete */
+ info->fix.smem_start =
+ (unsigned long)(mem->io_start +
+ i915_gem_object_get_dma_address(obj, 0));
+ info->fix.smem_len = obj->base.size;
+ } else {
+ info->apertures->ranges[0].base = ggtt->gmadr.start;
+ info->apertures->ranges[0].size = ggtt->mappable_end;
- /* Our framebuffer is the entirety of fbdev's system memory */
- info->fix.smem_start =
- (unsigned long)(ggtt->gmadr.start + vma->node.start);
- info->fix.smem_len = vma->node.size;
+ /* Our framebuffer is the entirety of fbdev's system memory */
+ info->fix.smem_start =
+ (unsigned long)(ggtt->gmadr.start + vma->node.start);
+ info->fix.smem_len = vma->node.size;
+ }
vaddr = i915_vma_pin_iomap(vma);
if (IS_ERR(vaddr)) {
--
2.26.3
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 6/7] drm/i915/lmem: Bypass aperture when lmem is available
2021-04-26 10:18 [PATCH 1/7] drm/i915/dg1: Fix mapping type for default state object Matthew Auld
` (3 preceding siblings ...)
2021-04-26 10:18 ` [PATCH 5/7] drm/i915/fbdev: Use lmem physical addresses for fb_mmap() on discrete Matthew Auld
@ 2021-04-26 10:18 ` Matthew Auld
2021-04-26 10:18 ` [PATCH 7/7] drm/i915: Return error value when bo not in LMEM for discrete Matthew Auld
5 siblings, 0 replies; 12+ messages in thread
From: Matthew Auld @ 2021-04-26 10:18 UTC (permalink / raw)
To: intel-gfx
Cc: Anusha Srivatsa, Tvrtko Ursulin, Chris P Wilson, CQ Tang,
Daniele Ceraolo Spurio, dri-devel, Daniel Vetter,
Dhinakaran Pandiyan
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
In the scenario where local memory is available, we have
rely on CPU access via lmem directly instead of aperture.
v2:
gmch is only relevant for much older hw, therefore we can drop the
has_aperture check since it should always be present on such platforms.
(Chris)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Chris P Wilson <chris.p.wilson@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: CQ Tang <cq.tang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 22 +++++++++++++------
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 15 +++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 5 +++++
drivers/gpu/drm/i915/i915_vma.c | 25 ++++++++++++++++------
4 files changed, 54 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 2b37959da747..4af40229f5ec 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -139,14 +139,22 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
size = mode_cmd.pitches[0] * mode_cmd.height;
size = PAGE_ALIGN(size);
- /* If the FB is too big, just don't use it since fbdev is not very
- * important and we should probably use that space with FBC or other
- * features. */
obj = ERR_PTR(-ENODEV);
- if (size * 2 < dev_priv->stolen_usable_size)
- obj = i915_gem_object_create_stolen(dev_priv, size);
- if (IS_ERR(obj))
- obj = i915_gem_object_create_shmem(dev_priv, size);
+ if (HAS_LMEM(dev_priv)) {
+ obj = i915_gem_object_create_lmem(dev_priv, size,
+ I915_BO_ALLOC_CONTIGUOUS);
+ } else {
+ /*
+ * If the FB is too big, just don't use it since fbdev is not very
+ * important and we should probably use that space with FBC or other
+ * features.
+ */
+ if (size * 2 < dev_priv->stolen_usable_size)
+ obj = i915_gem_object_create_stolen(dev_priv, size);
+ if (IS_ERR(obj))
+ obj = i915_gem_object_create_shmem(dev_priv, size);
+ }
+
if (IS_ERR(obj)) {
drm_err(&dev_priv->drm, "failed to allocate framebuffer\n");
return PTR_ERR(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 017db8f71130..f44bdd08f7cb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -17,6 +17,21 @@ const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
.release = i915_gem_object_release_memory_region,
};
+void __iomem *
+i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned long size)
+{
+ resource_size_t offset;
+
+ GEM_BUG_ON(!i915_gem_object_is_contiguous(obj));
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
+
+ return io_mapping_map_wc(&obj->mm.region->iomap, offset, size);
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
struct intel_memory_region *mr = obj->mm.region;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index 036d53c01de9..fac6bc5a5ebb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -14,6 +14,11 @@ struct intel_memory_region;
extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+void __iomem *
+i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned long size);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index eb01899ac6b7..468317e3b477 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -27,6 +27,7 @@
#include "display/intel_frontbuffer.h"
+#include "gem/i915_gem_lmem.h"
#include "gt/intel_engine.h"
#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_gt.h"
@@ -448,9 +449,11 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
void __iomem *ptr;
int err;
- if (GEM_WARN_ON(!i915_vma_is_map_and_fenceable(vma))) {
- err = -ENODEV;
- goto err;
+ if (!i915_gem_object_is_lmem(vma->obj)) {
+ if (GEM_WARN_ON(!i915_vma_is_map_and_fenceable(vma))) {
+ err = -ENODEV;
+ goto err;
+ }
}
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
@@ -458,9 +461,19 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
ptr = READ_ONCE(vma->iomap);
if (ptr == NULL) {
- ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
- vma->node.start,
- vma->node.size);
+ /*
+ * TODO: consider just using i915_gem_object_pin_map() for lmem
+ * instead, which already supports mapping non-contiguous chunks
+ * of pages, that way we can also drop the
+ * I915_BO_ALLOC_CONTIGUOUS when allocating the object.
+ */
+ if (i915_gem_object_is_lmem(vma->obj))
+ ptr = i915_gem_object_lmem_io_map(vma->obj, 0,
+ vma->obj->base.size);
+ else
+ ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
+ vma->node.start,
+ vma->node.size);
if (ptr == NULL) {
err = -ENOMEM;
goto err;
--
2.26.3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 7/7] drm/i915: Return error value when bo not in LMEM for discrete
2021-04-26 10:18 [PATCH 1/7] drm/i915/dg1: Fix mapping type for default state object Matthew Auld
` (4 preceding siblings ...)
2021-04-26 10:18 ` [PATCH 6/7] drm/i915/lmem: Bypass aperture when lmem is available Matthew Auld
@ 2021-04-26 10:18 ` Matthew Auld
5 siblings, 0 replies; 12+ messages in thread
From: Matthew Auld @ 2021-04-26 10:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Mohammed Khajapasha, dri-devel, Tvrtko Ursulin
From: Mohammed Khajapasha <mohammed.khajapasha@intel.com>
Return EREMOTE value when frame buffer object is not backed by LMEM
for discrete. If Local memory is supported by hardware the framebuffer
backing gem objects should be from local memory.
Signed-off-by: Mohammed Khajapasha <mohammed.khajapasha@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a10e26380ef3..be9155c95c33 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -63,6 +63,7 @@
#include "display/intel_vdsc.h"
#include "display/intel_vrr.h"
+#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_object.h"
#include "gt/intel_rps.h"
@@ -11269,11 +11270,20 @@ intel_user_framebuffer_create(struct drm_device *dev,
struct drm_framebuffer *fb;
struct drm_i915_gem_object *obj;
struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
+ struct drm_i915_private *i915;
obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
if (!obj)
return ERR_PTR(-ENOENT);
+ /* object is backed with LMEM for discrete */
+ i915 = to_i915(obj->base.dev);
+ if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj)) {
+ /* object is "remote", not in local memory */
+ i915_gem_object_put(obj);
+ return ERR_PTR(-EREMOTE);
+ }
+
fb = intel_framebuffer_create(obj, &mode_cmd);
i915_gem_object_put(obj);
--
2.26.3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 3/7] drm/i915/gtt: map the PD up front
2021-04-26 10:18 ` [PATCH 3/7] drm/i915/gtt: map the PD up front Matthew Auld
@ 2021-04-26 15:20 ` Tvrtko Ursulin
2021-04-26 16:18 ` Matthew Auld
0 siblings, 1 reply; 12+ messages in thread
From: Tvrtko Ursulin @ 2021-04-26 15:20 UTC (permalink / raw)
To: Matthew Auld, intel-gfx; +Cc: dri-devel, Chris Wilson
On 26/04/2021 11:18, Matthew Auld wrote:
> We need to general our accessor for the page directories and tables from
Generalise?
> using the simple kmap_atomic to support local memory, and this setup
> must be done on acquisition of the backing storage prior to entering
> fence execution contexts. Here we replace the kmap with the object
> maping code that for simple single page shmemfs object will return a
> plain kmap, that is then kept for the lifetime of the page directory.
How big are the address spaces used for mapping types? On 32-bit?
Do we have a mechanism to free something up if there is address space
pressure in there and is that a concern if we do not?
Regards,
Tvrtko
> v2: (Thomas) Rebase on dma_resv and obj->mm.lock removal.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> ---
> .../drm/i915/gem/selftests/i915_gem_context.c | 11 +----
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 11 ++---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 26 ++++------
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 48 +++++++++----------
> drivers/gpu/drm/i915/gt/intel_gtt.h | 11 +++--
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 7 ++-
> drivers/gpu/drm/i915/i915_vma.c | 3 +-
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 10 ++--
> drivers/gpu/drm/i915/selftests/i915_perf.c | 3 +-
> 10 files changed, 54 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index 5fef592390cb..ce70d0a3afb2 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -1740,7 +1740,6 @@ static int read_from_scratch(struct i915_gem_context *ctx,
> static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
> {
> struct i915_address_space *vm;
> - struct page *page;
> u32 *vaddr;
> int err = 0;
>
> @@ -1748,24 +1747,18 @@ static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
> if (!vm)
> return -ENODEV;
>
> - page = __px_page(vm->scratch[0]);
> - if (!page) {
> + if (!vm->scratch[0]) {
> pr_err("No scratch page!\n");
> return -EINVAL;
> }
>
> - vaddr = kmap(page);
> - if (!vaddr) {
> - pr_err("No (mappable) scratch page!\n");
> - return -EINVAL;
> - }
> + vaddr = __px_vaddr(vm->scratch[0]);
>
> memcpy(out, vaddr, sizeof(*out));
> if (memchr_inv(vaddr, *out, PAGE_SIZE)) {
> pr_err("Inconsistent initial state of scratch page!\n");
> err = -EINVAL;
> }
> - kunmap(page);
>
> return err;
> }
> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> index e08dff376339..21b1085769be 100644
> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> @@ -96,9 +96,8 @@ static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
> * entries back to scratch.
> */
>
> - vaddr = kmap_atomic_px(pt);
> + vaddr = px_vaddr(pt);
> memset32(vaddr + pte, scratch_pte, count);
> - kunmap_atomic(vaddr);
>
> pte = 0;
> }
> @@ -120,7 +119,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
>
> GEM_BUG_ON(!pd->entry[act_pt]);
>
> - vaddr = kmap_atomic_px(i915_pt_entry(pd, act_pt));
> + vaddr = px_vaddr(i915_pt_entry(pd, act_pt));
> do {
> GEM_BUG_ON(sg_dma_len(iter.sg) < I915_GTT_PAGE_SIZE);
> vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
> @@ -136,12 +135,10 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
> }
>
> if (++act_pte == GEN6_PTES) {
> - kunmap_atomic(vaddr);
> - vaddr = kmap_atomic_px(i915_pt_entry(pd, ++act_pt));
> + vaddr = px_vaddr(i915_pt_entry(pd, ++act_pt));
> act_pte = 0;
> }
> } while (1);
> - kunmap_atomic(vaddr);
>
> vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
> }
> @@ -235,7 +232,7 @@ static int gen6_ppgtt_init_scratch(struct gen6_ppgtt *ppgtt)
> goto err_scratch0;
> }
>
> - ret = pin_pt_dma(vm, vm->scratch[1]);
> + ret = map_pt_dma(vm, vm->scratch[1]);
> if (ret)
> goto err_scratch1;
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 176c19633412..f83496836f0f 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -242,11 +242,10 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm,
> atomic_read(&pt->used));
> GEM_BUG_ON(!count || count >= atomic_read(&pt->used));
>
> - vaddr = kmap_atomic_px(pt);
> + vaddr = px_vaddr(pt);
> memset64(vaddr + gen8_pd_index(start, 0),
> vm->scratch[0]->encode,
> count);
> - kunmap_atomic(vaddr);
>
> atomic_sub(count, &pt->used);
> start += count;
> @@ -375,7 +374,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
> gen8_pte_t *vaddr;
>
> pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
> - vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
> + vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
> do {
> GEM_BUG_ON(sg_dma_len(iter->sg) < I915_GTT_PAGE_SIZE);
> vaddr[gen8_pd_index(idx, 0)] = pte_encode | iter->dma;
> @@ -402,12 +401,10 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
> }
>
> clflush_cache_range(vaddr, PAGE_SIZE);
> - kunmap_atomic(vaddr);
> - vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
> + vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
> }
> } while (1);
> clflush_cache_range(vaddr, PAGE_SIZE);
> - kunmap_atomic(vaddr);
>
> return idx;
> }
> @@ -442,7 +439,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
> encode |= GEN8_PDE_PS_2M;
> page_size = I915_GTT_PAGE_SIZE_2M;
>
> - vaddr = kmap_atomic_px(pd);
> + vaddr = px_vaddr(pd);
> } else {
> struct i915_page_table *pt =
> i915_pt_entry(pd, __gen8_pte_index(start, 1));
> @@ -457,7 +454,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
> rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE))
> maybe_64K = __gen8_pte_index(start, 1);
>
> - vaddr = kmap_atomic_px(pt);
> + vaddr = px_vaddr(pt);
> }
>
> do {
> @@ -491,7 +488,6 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
> } while (rem >= page_size && index < I915_PDES);
>
> clflush_cache_range(vaddr, PAGE_SIZE);
> - kunmap_atomic(vaddr);
>
> /*
> * Is it safe to mark the 2M block as 64K? -- Either we have
> @@ -505,9 +501,8 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
> !iter->sg && IS_ALIGNED(vma->node.start +
> vma->node.size,
> I915_GTT_PAGE_SIZE_2M)))) {
> - vaddr = kmap_atomic_px(pd);
> + vaddr = px_vaddr(pd);
> vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
> - kunmap_atomic(vaddr);
> page_size = I915_GTT_PAGE_SIZE_64K;
>
> /*
> @@ -523,12 +518,11 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
> u16 i;
>
> encode = vma->vm->scratch[0]->encode;
> - vaddr = kmap_atomic_px(i915_pt_entry(pd, maybe_64K));
> + vaddr = px_vaddr(i915_pt_entry(pd, maybe_64K));
>
> for (i = 1; i < index; i += 16)
> memset64(vaddr + i, encode, 15);
>
> - kunmap_atomic(vaddr);
> }
> }
>
> @@ -602,7 +596,7 @@ static int gen8_init_scratch(struct i915_address_space *vm)
> if (IS_ERR(obj))
> goto free_scratch;
>
> - ret = pin_pt_dma(vm, obj);
> + ret = map_pt_dma(vm, obj);
> if (ret) {
> i915_gem_object_put(obj);
> goto free_scratch;
> @@ -639,7 +633,7 @@ static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt)
> if (IS_ERR(pde))
> return PTR_ERR(pde);
>
> - err = pin_pt_dma(vm, pde->pt.base);
> + err = map_pt_dma(vm, pde->pt.base);
> if (err) {
> i915_gem_object_put(pde->pt.base);
> free_pd(vm, pde);
> @@ -675,7 +669,7 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
> goto err_pd;
> }
>
> - err = pin_pt_dma(vm, pd->pt.base);
> + err = map_pt_dma(vm, pd->pt.base);
> if (err)
> goto err_pd;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 670c1271e7d5..d94628b9d89e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -657,7 +657,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
> goto err_ppgtt;
>
> i915_gem_object_lock(ppgtt->vm.scratch[0], NULL);
> - err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
> + err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
> i915_gem_object_unlock(ppgtt->vm.scratch[0]);
> if (err)
> goto err_stash;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 941f8af016d6..d386b89e2758 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -25,27 +25,25 @@ struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz)
> return obj;
> }
>
> -int pin_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
> +int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
> {
> - int err;
> + void *vaddr;
>
> - i915_gem_object_lock(obj, NULL);
> - err = i915_gem_object_pin_pages(obj);
> - i915_gem_object_unlock(obj);
> - if (err)
> - return err;
> + vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
> + if (IS_ERR(vaddr))
> + return PTR_ERR(vaddr);
>
> i915_gem_object_make_unshrinkable(obj);
> return 0;
> }
>
> -int pin_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
> +int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
> {
> - int err;
> + void *vaddr;
>
> - err = i915_gem_object_pin_pages(obj);
> - if (err)
> - return err;
> + vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
> + if (IS_ERR(vaddr))
> + return PTR_ERR(vaddr);
>
> i915_gem_object_make_unshrinkable(obj);
> return 0;
> @@ -155,6 +153,14 @@ void clear_pages(struct i915_vma *vma)
> memset(&vma->page_sizes, 0, sizeof(vma->page_sizes));
> }
>
> +void *__px_vaddr(struct drm_i915_gem_object *p)
> +{
> + enum i915_map_type type;
> +
> + GEM_BUG_ON(!i915_gem_object_has_pages(p));
> + return page_unpack_bits(p->mm.mapping, &type);
> +}
> +
> dma_addr_t __px_dma(struct drm_i915_gem_object *p)
> {
> GEM_BUG_ON(!i915_gem_object_has_pages(p));
> @@ -170,32 +176,22 @@ struct page *__px_page(struct drm_i915_gem_object *p)
> void
> fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
> {
> - struct page *page = __px_page(p);
> - void *vaddr;
> + void *vaddr = __px_vaddr(p);
>
> - vaddr = kmap(page);
> memset64(vaddr, val, count);
> clflush_cache_range(vaddr, PAGE_SIZE);
> - kunmap(page);
> }
>
> static void poison_scratch_page(struct drm_i915_gem_object *scratch)
> {
> - struct sgt_iter sgt;
> - struct page *page;
> + void *vaddr = __px_vaddr(scratch);
> u8 val;
>
> val = 0;
> if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> val = POISON_FREE;
>
> - for_each_sgt_page(page, sgt, scratch->mm.pages) {
> - void *vaddr;
> -
> - vaddr = kmap(page);
> - memset(vaddr, val, PAGE_SIZE);
> - kunmap(page);
> - }
> + memset(vaddr, val, scratch->base.size);
> }
>
> int setup_scratch_page(struct i915_address_space *vm)
> @@ -225,7 +221,7 @@ int setup_scratch_page(struct i915_address_space *vm)
> if (IS_ERR(obj))
> goto skip;
>
> - if (pin_pt_dma(vm, obj))
> + if (map_pt_dma(vm, obj))
> goto skip_obj;
>
> /* We need a single contiguous page for our scratch */
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index e67e34e17913..40e486704558 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -180,6 +180,9 @@ struct page *__px_page(struct drm_i915_gem_object *p);
> dma_addr_t __px_dma(struct drm_i915_gem_object *p);
> #define px_dma(px) (__px_dma(px_base(px)))
>
> +void *__px_vaddr(struct drm_i915_gem_object *p);
> +#define px_vaddr(px) (__px_vaddr(px_base(px)))
> +
> #define px_pt(px) \
> __px_choose_expr(px, struct i915_page_table *, __x, \
> __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
> @@ -511,8 +514,6 @@ struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
> void i915_ggtt_suspend(struct i915_ggtt *gtt);
> void i915_ggtt_resume(struct i915_ggtt *ggtt);
>
> -#define kmap_atomic_px(px) kmap_atomic(__px_page(px_base(px)))
> -
> void
> fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count);
>
> @@ -530,8 +531,8 @@ struct i915_page_table *alloc_pt(struct i915_address_space *vm);
> struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
> struct i915_page_directory *__alloc_pd(int npde);
>
> -int pin_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
> -int pin_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
> +int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
> +int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
>
> void free_px(struct i915_address_space *vm,
> struct i915_page_table *pt, int lvl);
> @@ -578,7 +579,7 @@ void setup_private_pat(struct intel_uncore *uncore);
> int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
> struct i915_vm_pt_stash *stash,
> u64 size);
> -int i915_vm_pin_pt_stash(struct i915_address_space *vm,
> +int i915_vm_map_pt_stash(struct i915_address_space *vm,
> struct i915_vm_pt_stash *stash);
> void i915_vm_free_pt_stash(struct i915_address_space *vm,
> struct i915_vm_pt_stash *stash);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> index 014ae8ac4480..4e3d80c2295c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> @@ -87,11 +87,10 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
> const unsigned short idx,
> const u64 encoded_entry)
> {
> - u64 * const vaddr = kmap_atomic(__px_page(pdma));
> + u64 * const vaddr = __px_vaddr(pdma);
>
> vaddr[idx] = encoded_entry;
> clflush_cache_range(&vaddr[idx], sizeof(u64));
> - kunmap_atomic(vaddr);
> }
>
> void
> @@ -258,7 +257,7 @@ int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
> return 0;
> }
>
> -int i915_vm_pin_pt_stash(struct i915_address_space *vm,
> +int i915_vm_map_pt_stash(struct i915_address_space *vm,
> struct i915_vm_pt_stash *stash)
> {
> struct i915_page_table *pt;
> @@ -266,7 +265,7 @@ int i915_vm_pin_pt_stash(struct i915_address_space *vm,
>
> for (n = 0; n < ARRAY_SIZE(stash->pt); n++) {
> for (pt = stash->pt[n]; pt; pt = pt->stash) {
> - err = pin_pt_dma_locked(vm, pt->base);
> + err = map_pt_dma_locked(vm, pt->base);
> if (err)
> return err;
> }
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index 07490db51cdc..eb01899ac6b7 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -905,8 +905,7 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
> if (err)
> goto err_fence;
>
> - err = i915_vm_pin_pt_stash(vma->vm,
> - &work->stash);
> + err = i915_vm_map_pt_stash(vma->vm, &work->stash);
> if (err)
> goto err_fence;
> }
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> index 2e4f06eaacc1..e060e455e9f6 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> @@ -186,7 +186,7 @@ static int igt_ppgtt_alloc(void *arg)
> if (err)
> goto err_ppgtt_cleanup;
>
> - err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
> + err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
> if (err) {
> i915_vm_free_pt_stash(&ppgtt->vm, &stash);
> goto err_ppgtt_cleanup;
> @@ -208,7 +208,7 @@ static int igt_ppgtt_alloc(void *arg)
> if (err)
> goto err_ppgtt_cleanup;
>
> - err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
> + err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
> if (err) {
> i915_vm_free_pt_stash(&ppgtt->vm, &stash);
> goto err_ppgtt_cleanup;
> @@ -325,11 +325,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
> BIT_ULL(size)))
> goto alloc_vm_end;
>
> - err = i915_vm_pin_pt_stash(vm, &stash);
> + err = i915_vm_map_pt_stash(vm, &stash);
> if (!err)
> vm->allocate_va_range(vm, &stash,
> addr, BIT_ULL(size));
> -
> i915_vm_free_pt_stash(vm, &stash);
> alloc_vm_end:
> if (err == -EDEADLK) {
> @@ -1967,10 +1966,9 @@ static int igt_cs_tlb(void *arg)
> if (err)
> goto end_ww;
>
> - err = i915_vm_pin_pt_stash(vm, &stash);
> + err = i915_vm_map_pt_stash(vm, &stash);
> if (!err)
> vm->allocate_va_range(vm, &stash, offset, chunk_size);
> -
> i915_vm_free_pt_stash(vm, &stash);
> end_ww:
> if (err == -EDEADLK) {
> diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
> index e9d86dab8677..bfb0290967a1 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_perf.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
> @@ -307,7 +307,7 @@ static int live_noa_gpr(void *arg)
> }
>
> /* Poison the ce->vm so we detect writes not to the GGTT gt->scratch */
> - scratch = kmap(__px_page(ce->vm->scratch[0]));
> + scratch = __px_vaddr(ce->vm->scratch[0]);
> memset(scratch, POISON_FREE, PAGE_SIZE);
>
> rq = intel_context_create_request(ce);
> @@ -405,7 +405,6 @@ static int live_noa_gpr(void *arg)
> out_rq:
> i915_request_put(rq);
> out_ce:
> - kunmap(__px_page(ce->vm->scratch[0]));
> intel_context_put(ce);
> out:
> stream_destroy(stream);
>
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/7] drm/i915/gtt/dgfx: place the PD in LMEM
2021-04-26 10:18 ` [PATCH 4/7] drm/i915/gtt/dgfx: place the PD in LMEM Matthew Auld
@ 2021-04-26 15:22 ` Tvrtko Ursulin
2021-04-26 16:42 ` Matthew Auld
0 siblings, 1 reply; 12+ messages in thread
From: Tvrtko Ursulin @ 2021-04-26 15:22 UTC (permalink / raw)
To: Matthew Auld, intel-gfx; +Cc: dri-devel
On 26/04/2021 11:18, Matthew Auld wrote:
> It's a requirement that for dgfx we place all the paging structures in
> device local-memory.
>
> v2: use i915_coherent_map_type()
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 ++++-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 21 +++++++++++++++++++--
> drivers/gpu/drm/i915/gt/intel_gtt.h | 1 +
> 3 files changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index f83496836f0f..11fb5df45a0f 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -712,7 +712,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> */
> ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
>
> - ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
> + if (HAS_LMEM(gt->i915))
> + ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
> + else
> + ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
>
> err = gen8_init_scratch(&ppgtt->vm);
> if (err)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index d386b89e2758..bbe5b09e59ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -7,10 +7,23 @@
>
> #include <linux/fault-inject.h>
>
> +#include "gem/i915_gem_lmem.h"
> #include "i915_trace.h"
> #include "intel_gt.h"
> #include "intel_gtt.h"
>
> +struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
> +{
> + struct drm_i915_gem_object *obj;
> +
> + obj = i915_gem_object_create_lmem(vm->i915, sz, 0);
> +
> + /* ensure all dma objects have the same reservation class */
Class or actual object? And could the comment say why this is important?
Regards,
Tvrtko
> + if (!IS_ERR(obj))
> + obj->base.resv = &vm->resv;
> + return obj;
> +}
> +
> struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz)
> {
> struct drm_i915_gem_object *obj;
> @@ -27,9 +40,11 @@ struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz)
>
> int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
> {
> + enum i915_map_type type;
> void *vaddr;
>
> - vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
> + type = i915_coherent_map_type(vm->i915, obj, true);
> + vaddr = i915_gem_object_pin_map_unlocked(obj, type);
> if (IS_ERR(vaddr))
> return PTR_ERR(vaddr);
>
> @@ -39,9 +54,11 @@ int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
>
> int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
> {
> + enum i915_map_type type;
> void *vaddr;
>
> - vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
> + type = i915_coherent_map_type(vm->i915, obj, true);
> + vaddr = i915_gem_object_pin_map(obj, type);
> if (IS_ERR(vaddr))
> return PTR_ERR(vaddr);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index 40e486704558..44ce27c51631 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -527,6 +527,7 @@ int setup_scratch_page(struct i915_address_space *vm);
> void free_scratch(struct i915_address_space *vm);
>
> struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz);
> +struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz);
> struct i915_page_table *alloc_pt(struct i915_address_space *vm);
> struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
> struct i915_page_directory *__alloc_pd(int npde);
>
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/7] drm/i915/gtt: map the PD up front
2021-04-26 15:20 ` Tvrtko Ursulin
@ 2021-04-26 16:18 ` Matthew Auld
2021-04-27 8:20 ` Tvrtko Ursulin
0 siblings, 1 reply; 12+ messages in thread
From: Matthew Auld @ 2021-04-26 16:18 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: dri-devel, Chris Wilson
On 26/04/2021 16:20, Tvrtko Ursulin wrote:
>
> On 26/04/2021 11:18, Matthew Auld wrote:
>> We need to general our accessor for the page directories and tables from
>
> Generalise?
>
>> using the simple kmap_atomic to support local memory, and this setup
>> must be done on acquisition of the backing storage prior to entering
>> fence execution contexts. Here we replace the kmap with the object
>> maping code that for simple single page shmemfs object will return a
>> plain kmap, that is then kept for the lifetime of the page directory.
>
> How big are the address spaces used for mapping types? On 32-bit?
>
> Do we have a mechanism to free something up if there is address space
> pressure in there and is that a concern if we do not?
It's a concern yes, since while the vma is pinned the mapping remains
there for the PDs underneath, or at least until the used_count reaches
zero, at which point we can safely destroy the mapping.
For the 32bit concern, this was brought up in some earlier review[1]
also. AFAIK the conclusion was just to not care about 32b for modern
platforms, so platforms with full ppGTT support where this patch
actually matters the most.
[1] https://patchwork.freedesktop.org/patch/404460/?series=84344&rev=1
>
> Regards,
>
> Tvrtko
>
>> v2: (Thomas) Rebase on dma_resv and obj->mm.lock removal.
>>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> ---
>> .../drm/i915/gem/selftests/i915_gem_context.c | 11 +----
>> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 11 ++---
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 26 ++++------
>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_gtt.c | 48 +++++++++----------
>> drivers/gpu/drm/i915/gt/intel_gtt.h | 11 +++--
>> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 7 ++-
>> drivers/gpu/drm/i915/i915_vma.c | 3 +-
>> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 10 ++--
>> drivers/gpu/drm/i915/selftests/i915_perf.c | 3 +-
>> 10 files changed, 54 insertions(+), 78 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> index 5fef592390cb..ce70d0a3afb2 100644
>> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> @@ -1740,7 +1740,6 @@ static int read_from_scratch(struct
>> i915_gem_context *ctx,
>> static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
>> {
>> struct i915_address_space *vm;
>> - struct page *page;
>> u32 *vaddr;
>> int err = 0;
>> @@ -1748,24 +1747,18 @@ static int check_scratch_page(struct
>> i915_gem_context *ctx, u32 *out)
>> if (!vm)
>> return -ENODEV;
>> - page = __px_page(vm->scratch[0]);
>> - if (!page) {
>> + if (!vm->scratch[0]) {
>> pr_err("No scratch page!\n");
>> return -EINVAL;
>> }
>> - vaddr = kmap(page);
>> - if (!vaddr) {
>> - pr_err("No (mappable) scratch page!\n");
>> - return -EINVAL;
>> - }
>> + vaddr = __px_vaddr(vm->scratch[0]);
>> memcpy(out, vaddr, sizeof(*out));
>> if (memchr_inv(vaddr, *out, PAGE_SIZE)) {
>> pr_err("Inconsistent initial state of scratch page!\n");
>> err = -EINVAL;
>> }
>> - kunmap(page);
>> return err;
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>> b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>> index e08dff376339..21b1085769be 100644
>> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>> @@ -96,9 +96,8 @@ static void gen6_ppgtt_clear_range(struct
>> i915_address_space *vm,
>> * entries back to scratch.
>> */
>> - vaddr = kmap_atomic_px(pt);
>> + vaddr = px_vaddr(pt);
>> memset32(vaddr + pte, scratch_pte, count);
>> - kunmap_atomic(vaddr);
>> pte = 0;
>> }
>> @@ -120,7 +119,7 @@ static void gen6_ppgtt_insert_entries(struct
>> i915_address_space *vm,
>> GEM_BUG_ON(!pd->entry[act_pt]);
>> - vaddr = kmap_atomic_px(i915_pt_entry(pd, act_pt));
>> + vaddr = px_vaddr(i915_pt_entry(pd, act_pt));
>> do {
>> GEM_BUG_ON(sg_dma_len(iter.sg) < I915_GTT_PAGE_SIZE);
>> vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
>> @@ -136,12 +135,10 @@ static void gen6_ppgtt_insert_entries(struct
>> i915_address_space *vm,
>> }
>> if (++act_pte == GEN6_PTES) {
>> - kunmap_atomic(vaddr);
>> - vaddr = kmap_atomic_px(i915_pt_entry(pd, ++act_pt));
>> + vaddr = px_vaddr(i915_pt_entry(pd, ++act_pt));
>> act_pte = 0;
>> }
>> } while (1);
>> - kunmap_atomic(vaddr);
>> vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
>> }
>> @@ -235,7 +232,7 @@ static int gen6_ppgtt_init_scratch(struct
>> gen6_ppgtt *ppgtt)
>> goto err_scratch0;
>> }
>> - ret = pin_pt_dma(vm, vm->scratch[1]);
>> + ret = map_pt_dma(vm, vm->scratch[1]);
>> if (ret)
>> goto err_scratch1;
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> index 176c19633412..f83496836f0f 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> @@ -242,11 +242,10 @@ static u64 __gen8_ppgtt_clear(struct
>> i915_address_space * const vm,
>> atomic_read(&pt->used));
>> GEM_BUG_ON(!count || count >= atomic_read(&pt->used));
>> - vaddr = kmap_atomic_px(pt);
>> + vaddr = px_vaddr(pt);
>> memset64(vaddr + gen8_pd_index(start, 0),
>> vm->scratch[0]->encode,
>> count);
>> - kunmap_atomic(vaddr);
>> atomic_sub(count, &pt->used);
>> start += count;
>> @@ -375,7 +374,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
>> gen8_pte_t *vaddr;
>> pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
>> - vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
>> + vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
>> do {
>> GEM_BUG_ON(sg_dma_len(iter->sg) < I915_GTT_PAGE_SIZE);
>> vaddr[gen8_pd_index(idx, 0)] = pte_encode | iter->dma;
>> @@ -402,12 +401,10 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
>> }
>> clflush_cache_range(vaddr, PAGE_SIZE);
>> - kunmap_atomic(vaddr);
>> - vaddr = kmap_atomic_px(i915_pt_entry(pd,
>> gen8_pd_index(idx, 1)));
>> + vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
>> }
>> } while (1);
>> clflush_cache_range(vaddr, PAGE_SIZE);
>> - kunmap_atomic(vaddr);
>> return idx;
>> }
>> @@ -442,7 +439,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma
>> *vma,
>> encode |= GEN8_PDE_PS_2M;
>> page_size = I915_GTT_PAGE_SIZE_2M;
>> - vaddr = kmap_atomic_px(pd);
>> + vaddr = px_vaddr(pd);
>> } else {
>> struct i915_page_table *pt =
>> i915_pt_entry(pd, __gen8_pte_index(start, 1));
>> @@ -457,7 +454,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma
>> *vma,
>> rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE))
>> maybe_64K = __gen8_pte_index(start, 1);
>> - vaddr = kmap_atomic_px(pt);
>> + vaddr = px_vaddr(pt);
>> }
>> do {
>> @@ -491,7 +488,6 @@ static void gen8_ppgtt_insert_huge(struct i915_vma
>> *vma,
>> } while (rem >= page_size && index < I915_PDES);
>> clflush_cache_range(vaddr, PAGE_SIZE);
>> - kunmap_atomic(vaddr);
>> /*
>> * Is it safe to mark the 2M block as 64K? -- Either we have
>> @@ -505,9 +501,8 @@ static void gen8_ppgtt_insert_huge(struct i915_vma
>> *vma,
>> !iter->sg && IS_ALIGNED(vma->node.start +
>> vma->node.size,
>> I915_GTT_PAGE_SIZE_2M)))) {
>> - vaddr = kmap_atomic_px(pd);
>> + vaddr = px_vaddr(pd);
>> vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
>> - kunmap_atomic(vaddr);
>> page_size = I915_GTT_PAGE_SIZE_64K;
>> /*
>> @@ -523,12 +518,11 @@ static void gen8_ppgtt_insert_huge(struct
>> i915_vma *vma,
>> u16 i;
>> encode = vma->vm->scratch[0]->encode;
>> - vaddr = kmap_atomic_px(i915_pt_entry(pd, maybe_64K));
>> + vaddr = px_vaddr(i915_pt_entry(pd, maybe_64K));
>> for (i = 1; i < index; i += 16)
>> memset64(vaddr + i, encode, 15);
>> - kunmap_atomic(vaddr);
>> }
>> }
>> @@ -602,7 +596,7 @@ static int gen8_init_scratch(struct
>> i915_address_space *vm)
>> if (IS_ERR(obj))
>> goto free_scratch;
>> - ret = pin_pt_dma(vm, obj);
>> + ret = map_pt_dma(vm, obj);
>> if (ret) {
>> i915_gem_object_put(obj);
>> goto free_scratch;
>> @@ -639,7 +633,7 @@ static int gen8_preallocate_top_level_pdp(struct
>> i915_ppgtt *ppgtt)
>> if (IS_ERR(pde))
>> return PTR_ERR(pde);
>> - err = pin_pt_dma(vm, pde->pt.base);
>> + err = map_pt_dma(vm, pde->pt.base);
>> if (err) {
>> i915_gem_object_put(pde->pt.base);
>> free_pd(vm, pde);
>> @@ -675,7 +669,7 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
>> goto err_pd;
>> }
>> - err = pin_pt_dma(vm, pd->pt.base);
>> + err = map_pt_dma(vm, pd->pt.base);
>> if (err)
>> goto err_pd;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> index 670c1271e7d5..d94628b9d89e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> @@ -657,7 +657,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt
>> *ggtt)
>> goto err_ppgtt;
>> i915_gem_object_lock(ppgtt->vm.scratch[0], NULL);
>> - err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
>> + err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
>> i915_gem_object_unlock(ppgtt->vm.scratch[0]);
>> if (err)
>> goto err_stash;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
>> b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> index 941f8af016d6..d386b89e2758 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> @@ -25,27 +25,25 @@ struct drm_i915_gem_object *alloc_pt_dma(struct
>> i915_address_space *vm, int sz)
>> return obj;
>> }
>> -int pin_pt_dma(struct i915_address_space *vm, struct
>> drm_i915_gem_object *obj)
>> +int map_pt_dma(struct i915_address_space *vm, struct
>> drm_i915_gem_object *obj)
>> {
>> - int err;
>> + void *vaddr;
>> - i915_gem_object_lock(obj, NULL);
>> - err = i915_gem_object_pin_pages(obj);
>> - i915_gem_object_unlock(obj);
>> - if (err)
>> - return err;
>> + vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
>> + if (IS_ERR(vaddr))
>> + return PTR_ERR(vaddr);
>> i915_gem_object_make_unshrinkable(obj);
>> return 0;
>> }
>> -int pin_pt_dma_locked(struct i915_address_space *vm, struct
>> drm_i915_gem_object *obj)
>> +int map_pt_dma_locked(struct i915_address_space *vm, struct
>> drm_i915_gem_object *obj)
>> {
>> - int err;
>> + void *vaddr;
>> - err = i915_gem_object_pin_pages(obj);
>> - if (err)
>> - return err;
>> + vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
>> + if (IS_ERR(vaddr))
>> + return PTR_ERR(vaddr);
>> i915_gem_object_make_unshrinkable(obj);
>> return 0;
>> @@ -155,6 +153,14 @@ void clear_pages(struct i915_vma *vma)
>> memset(&vma->page_sizes, 0, sizeof(vma->page_sizes));
>> }
>> +void *__px_vaddr(struct drm_i915_gem_object *p)
>> +{
>> + enum i915_map_type type;
>> +
>> + GEM_BUG_ON(!i915_gem_object_has_pages(p));
>> + return page_unpack_bits(p->mm.mapping, &type);
>> +}
>> +
>> dma_addr_t __px_dma(struct drm_i915_gem_object *p)
>> {
>> GEM_BUG_ON(!i915_gem_object_has_pages(p));
>> @@ -170,32 +176,22 @@ struct page *__px_page(struct
>> drm_i915_gem_object *p)
>> void
>> fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned
>> int count)
>> {
>> - struct page *page = __px_page(p);
>> - void *vaddr;
>> + void *vaddr = __px_vaddr(p);
>> - vaddr = kmap(page);
>> memset64(vaddr, val, count);
>> clflush_cache_range(vaddr, PAGE_SIZE);
>> - kunmap(page);
>> }
>> static void poison_scratch_page(struct drm_i915_gem_object *scratch)
>> {
>> - struct sgt_iter sgt;
>> - struct page *page;
>> + void *vaddr = __px_vaddr(scratch);
>> u8 val;
>> val = 0;
>> if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
>> val = POISON_FREE;
>> - for_each_sgt_page(page, sgt, scratch->mm.pages) {
>> - void *vaddr;
>> -
>> - vaddr = kmap(page);
>> - memset(vaddr, val, PAGE_SIZE);
>> - kunmap(page);
>> - }
>> + memset(vaddr, val, scratch->base.size);
>> }
>> int setup_scratch_page(struct i915_address_space *vm)
>> @@ -225,7 +221,7 @@ int setup_scratch_page(struct i915_address_space *vm)
>> if (IS_ERR(obj))
>> goto skip;
>> - if (pin_pt_dma(vm, obj))
>> + if (map_pt_dma(vm, obj))
>> goto skip_obj;
>> /* We need a single contiguous page for our scratch */
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
>> b/drivers/gpu/drm/i915/gt/intel_gtt.h
>> index e67e34e17913..40e486704558 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
>> @@ -180,6 +180,9 @@ struct page *__px_page(struct drm_i915_gem_object
>> *p);
>> dma_addr_t __px_dma(struct drm_i915_gem_object *p);
>> #define px_dma(px) (__px_dma(px_base(px)))
>> +void *__px_vaddr(struct drm_i915_gem_object *p);
>> +#define px_vaddr(px) (__px_vaddr(px_base(px)))
>> +
>> #define px_pt(px) \
>> __px_choose_expr(px, struct i915_page_table *, __x, \
>> __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
>> @@ -511,8 +514,6 @@ struct i915_ppgtt *i915_ppgtt_create(struct
>> intel_gt *gt);
>> void i915_ggtt_suspend(struct i915_ggtt *gtt);
>> void i915_ggtt_resume(struct i915_ggtt *ggtt);
>> -#define kmap_atomic_px(px) kmap_atomic(__px_page(px_base(px)))
>> -
>> void
>> fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned
>> int count);
>> @@ -530,8 +531,8 @@ struct i915_page_table *alloc_pt(struct
>> i915_address_space *vm);
>> struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
>> struct i915_page_directory *__alloc_pd(int npde);
>> -int pin_pt_dma(struct i915_address_space *vm, struct
>> drm_i915_gem_object *obj);
>> -int pin_pt_dma_locked(struct i915_address_space *vm, struct
>> drm_i915_gem_object *obj);
>> +int map_pt_dma(struct i915_address_space *vm, struct
>> drm_i915_gem_object *obj);
>> +int map_pt_dma_locked(struct i915_address_space *vm, struct
>> drm_i915_gem_object *obj);
>> void free_px(struct i915_address_space *vm,
>> struct i915_page_table *pt, int lvl);
>> @@ -578,7 +579,7 @@ void setup_private_pat(struct intel_uncore *uncore);
>> int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
>> struct i915_vm_pt_stash *stash,
>> u64 size);
>> -int i915_vm_pin_pt_stash(struct i915_address_space *vm,
>> +int i915_vm_map_pt_stash(struct i915_address_space *vm,
>> struct i915_vm_pt_stash *stash);
>> void i915_vm_free_pt_stash(struct i915_address_space *vm,
>> struct i915_vm_pt_stash *stash);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> index 014ae8ac4480..4e3d80c2295c 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> @@ -87,11 +87,10 @@ write_dma_entry(struct drm_i915_gem_object * const
>> pdma,
>> const unsigned short idx,
>> const u64 encoded_entry)
>> {
>> - u64 * const vaddr = kmap_atomic(__px_page(pdma));
>> + u64 * const vaddr = __px_vaddr(pdma);
>> vaddr[idx] = encoded_entry;
>> clflush_cache_range(&vaddr[idx], sizeof(u64));
>> - kunmap_atomic(vaddr);
>> }
>> void
>> @@ -258,7 +257,7 @@ int i915_vm_alloc_pt_stash(struct
>> i915_address_space *vm,
>> return 0;
>> }
>> -int i915_vm_pin_pt_stash(struct i915_address_space *vm,
>> +int i915_vm_map_pt_stash(struct i915_address_space *vm,
>> struct i915_vm_pt_stash *stash)
>> {
>> struct i915_page_table *pt;
>> @@ -266,7 +265,7 @@ int i915_vm_pin_pt_stash(struct i915_address_space
>> *vm,
>> for (n = 0; n < ARRAY_SIZE(stash->pt); n++) {
>> for (pt = stash->pt[n]; pt; pt = pt->stash) {
>> - err = pin_pt_dma_locked(vm, pt->base);
>> + err = map_pt_dma_locked(vm, pt->base);
>> if (err)
>> return err;
>> }
>> diff --git a/drivers/gpu/drm/i915/i915_vma.c
>> b/drivers/gpu/drm/i915/i915_vma.c
>> index 07490db51cdc..eb01899ac6b7 100644
>> --- a/drivers/gpu/drm/i915/i915_vma.c
>> +++ b/drivers/gpu/drm/i915/i915_vma.c
>> @@ -905,8 +905,7 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct
>> i915_gem_ww_ctx *ww,
>> if (err)
>> goto err_fence;
>> - err = i915_vm_pin_pt_stash(vma->vm,
>> - &work->stash);
>> + err = i915_vm_map_pt_stash(vma->vm, &work->stash);
>> if (err)
>> goto err_fence;
>> }
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> index 2e4f06eaacc1..e060e455e9f6 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> @@ -186,7 +186,7 @@ static int igt_ppgtt_alloc(void *arg)
>> if (err)
>> goto err_ppgtt_cleanup;
>> - err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
>> + err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
>> if (err) {
>> i915_vm_free_pt_stash(&ppgtt->vm, &stash);
>> goto err_ppgtt_cleanup;
>> @@ -208,7 +208,7 @@ static int igt_ppgtt_alloc(void *arg)
>> if (err)
>> goto err_ppgtt_cleanup;
>> - err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
>> + err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
>> if (err) {
>> i915_vm_free_pt_stash(&ppgtt->vm, &stash);
>> goto err_ppgtt_cleanup;
>> @@ -325,11 +325,10 @@ static int lowlevel_hole(struct
>> i915_address_space *vm,
>> BIT_ULL(size)))
>> goto alloc_vm_end;
>> - err = i915_vm_pin_pt_stash(vm, &stash);
>> + err = i915_vm_map_pt_stash(vm, &stash);
>> if (!err)
>> vm->allocate_va_range(vm, &stash,
>> addr, BIT_ULL(size));
>> -
>> i915_vm_free_pt_stash(vm, &stash);
>> alloc_vm_end:
>> if (err == -EDEADLK) {
>> @@ -1967,10 +1966,9 @@ static int igt_cs_tlb(void *arg)
>> if (err)
>> goto end_ww;
>> - err = i915_vm_pin_pt_stash(vm, &stash);
>> + err = i915_vm_map_pt_stash(vm, &stash);
>> if (!err)
>> vm->allocate_va_range(vm, &stash, offset, chunk_size);
>> -
>> i915_vm_free_pt_stash(vm, &stash);
>> end_ww:
>> if (err == -EDEADLK) {
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c
>> b/drivers/gpu/drm/i915/selftests/i915_perf.c
>> index e9d86dab8677..bfb0290967a1 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
>> @@ -307,7 +307,7 @@ static int live_noa_gpr(void *arg)
>> }
>> /* Poison the ce->vm so we detect writes not to the GGTT
>> gt->scratch */
>> - scratch = kmap(__px_page(ce->vm->scratch[0]));
>> + scratch = __px_vaddr(ce->vm->scratch[0]);
>> memset(scratch, POISON_FREE, PAGE_SIZE);
>> rq = intel_context_create_request(ce);
>> @@ -405,7 +405,6 @@ static int live_noa_gpr(void *arg)
>> out_rq:
>> i915_request_put(rq);
>> out_ce:
>> - kunmap(__px_page(ce->vm->scratch[0]));
>> intel_context_put(ce);
>> out:
>> stream_destroy(stream);
>>
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/7] drm/i915/gtt/dgfx: place the PD in LMEM
2021-04-26 15:22 ` Tvrtko Ursulin
@ 2021-04-26 16:42 ` Matthew Auld
0 siblings, 0 replies; 12+ messages in thread
From: Matthew Auld @ 2021-04-26 16:42 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: dri-devel
On 26/04/2021 16:22, Tvrtko Ursulin wrote:
>
> On 26/04/2021 11:18, Matthew Auld wrote:
>> It's a requirement that for dgfx we place all the paging structures in
>> device local-memory.
>>
>> v2: use i915_coherent_map_type()
>>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 ++++-
>> drivers/gpu/drm/i915/gt/intel_gtt.c | 21 +++++++++++++++++++--
>> drivers/gpu/drm/i915/gt/intel_gtt.h | 1 +
>> 3 files changed, 24 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> index f83496836f0f..11fb5df45a0f 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> @@ -712,7 +712,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct
>> intel_gt *gt)
>> */
>> ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
>> - ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
>> + if (HAS_LMEM(gt->i915))
>> + ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
>> + else
>> + ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
>> err = gen8_init_scratch(&ppgtt->vm);
>> if (err)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
>> b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> index d386b89e2758..bbe5b09e59ec 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> @@ -7,10 +7,23 @@
>> #include <linux/fault-inject.h>
>> +#include "gem/i915_gem_lmem.h"
>> #include "i915_trace.h"
>> #include "intel_gt.h"
>> #include "intel_gtt.h"
>> +struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space
>> *vm, int sz)
>> +{
>> + struct drm_i915_gem_object *obj;
>> +
>> + obj = i915_gem_object_create_lmem(vm->i915, sz, 0);
>> +
>> + /* ensure all dma objects have the same reservation class */
>
> Class or actual object? And could the comment say why this is important?
It's the dma-resv object. The paging structures for this vm share the
same dma-resv object underneath, with the idea that one object_lock()
will lock them all at once. I can try to improve the comment.
>
> Regards,
>
> Tvrtko
>
>> + if (!IS_ERR(obj))
>> + obj->base.resv = &vm->resv;
>> + return obj;
>> +}
>> +
>> struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space
>> *vm, int sz)
>> {
>> struct drm_i915_gem_object *obj;
>> @@ -27,9 +40,11 @@ struct drm_i915_gem_object *alloc_pt_dma(struct
>> i915_address_space *vm, int sz)
>> int map_pt_dma(struct i915_address_space *vm, struct
>> drm_i915_gem_object *obj)
>> {
>> + enum i915_map_type type;
>> void *vaddr;
>> - vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
>> + type = i915_coherent_map_type(vm->i915, obj, true);
>> + vaddr = i915_gem_object_pin_map_unlocked(obj, type);
>> if (IS_ERR(vaddr))
>> return PTR_ERR(vaddr);
>> @@ -39,9 +54,11 @@ int map_pt_dma(struct i915_address_space *vm,
>> struct drm_i915_gem_object *obj)
>> int map_pt_dma_locked(struct i915_address_space *vm, struct
>> drm_i915_gem_object *obj)
>> {
>> + enum i915_map_type type;
>> void *vaddr;
>> - vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
>> + type = i915_coherent_map_type(vm->i915, obj, true);
>> + vaddr = i915_gem_object_pin_map(obj, type);
>> if (IS_ERR(vaddr))
>> return PTR_ERR(vaddr);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
>> b/drivers/gpu/drm/i915/gt/intel_gtt.h
>> index 40e486704558..44ce27c51631 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
>> @@ -527,6 +527,7 @@ int setup_scratch_page(struct i915_address_space
>> *vm);
>> void free_scratch(struct i915_address_space *vm);
>> struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space
>> *vm, int sz);
>> +struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space
>> *vm, int sz);
>> struct i915_page_table *alloc_pt(struct i915_address_space *vm);
>> struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
>> struct i915_page_directory *__alloc_pd(int npde);
>>
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/7] drm/i915/gtt: map the PD up front
2021-04-26 16:18 ` Matthew Auld
@ 2021-04-27 8:20 ` Tvrtko Ursulin
0 siblings, 0 replies; 12+ messages in thread
From: Tvrtko Ursulin @ 2021-04-27 8:20 UTC (permalink / raw)
To: Matthew Auld, intel-gfx; +Cc: dri-devel, Chris Wilson
On 26/04/2021 17:18, Matthew Auld wrote:
> On 26/04/2021 16:20, Tvrtko Ursulin wrote:
>>
>> On 26/04/2021 11:18, Matthew Auld wrote:
>>> We need to general our accessor for the page directories and tables from
>>
>> Generalise?
>>
>>> using the simple kmap_atomic to support local memory, and this setup
>>> must be done on acquisition of the backing storage prior to entering
>>> fence execution contexts. Here we replace the kmap with the object
>>> maping code that for simple single page shmemfs object will return a
>>> plain kmap, that is then kept for the lifetime of the page directory.
>>
>> How big are the address spaces used for mapping types? On 32-bit?
>>
>> Do we have a mechanism to free something up if there is address space
>> pressure in there and is that a concern if we do not?
>
> It's a concern yes, since while the vma is pinned the mapping remains
> there for the PDs underneath, or at least until the used_count reaches
> zero, at which point we can safely destroy the mapping.
>
> For the 32bit concern, this was brought up in some earlier review[1]
> also. AFAIK the conclusion was just to not care about 32b for modern
> platforms, so platforms with full ppGTT support where this patch
> actually matters the most.
>
> [1] https://patchwork.freedesktop.org/patch/404460/?series=84344&rev=1
Okay thanks.
Can I suggest to capture at least the gist of this discussion in the
commit message?
Regards,
Tvrtko
>>
>> Regards,
>>
>> Tvrtko
>>
>>> v2: (Thomas) Rebase on dma_resv and obj->mm.lock removal.
>>>
>>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>>> ---
>>> .../drm/i915/gem/selftests/i915_gem_context.c | 11 +----
>>> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 11 ++---
>>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 26 ++++------
>>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
>>> drivers/gpu/drm/i915/gt/intel_gtt.c | 48 +++++++++----------
>>> drivers/gpu/drm/i915/gt/intel_gtt.h | 11 +++--
>>> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 7 ++-
>>> drivers/gpu/drm/i915/i915_vma.c | 3 +-
>>> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 10 ++--
>>> drivers/gpu/drm/i915/selftests/i915_perf.c | 3 +-
>>> 10 files changed, 54 insertions(+), 78 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>>> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>>> index 5fef592390cb..ce70d0a3afb2 100644
>>> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>>> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>>> @@ -1740,7 +1740,6 @@ static int read_from_scratch(struct
>>> i915_gem_context *ctx,
>>> static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
>>> {
>>> struct i915_address_space *vm;
>>> - struct page *page;
>>> u32 *vaddr;
>>> int err = 0;
>>> @@ -1748,24 +1747,18 @@ static int check_scratch_page(struct
>>> i915_gem_context *ctx, u32 *out)
>>> if (!vm)
>>> return -ENODEV;
>>> - page = __px_page(vm->scratch[0]);
>>> - if (!page) {
>>> + if (!vm->scratch[0]) {
>>> pr_err("No scratch page!\n");
>>> return -EINVAL;
>>> }
>>> - vaddr = kmap(page);
>>> - if (!vaddr) {
>>> - pr_err("No (mappable) scratch page!\n");
>>> - return -EINVAL;
>>> - }
>>> + vaddr = __px_vaddr(vm->scratch[0]);
>>> memcpy(out, vaddr, sizeof(*out));
>>> if (memchr_inv(vaddr, *out, PAGE_SIZE)) {
>>> pr_err("Inconsistent initial state of scratch page!\n");
>>> err = -EINVAL;
>>> }
>>> - kunmap(page);
>>> return err;
>>> }
>>> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>>> b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>>> index e08dff376339..21b1085769be 100644
>>> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>>> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>>> @@ -96,9 +96,8 @@ static void gen6_ppgtt_clear_range(struct
>>> i915_address_space *vm,
>>> * entries back to scratch.
>>> */
>>> - vaddr = kmap_atomic_px(pt);
>>> + vaddr = px_vaddr(pt);
>>> memset32(vaddr + pte, scratch_pte, count);
>>> - kunmap_atomic(vaddr);
>>> pte = 0;
>>> }
>>> @@ -120,7 +119,7 @@ static void gen6_ppgtt_insert_entries(struct
>>> i915_address_space *vm,
>>> GEM_BUG_ON(!pd->entry[act_pt]);
>>> - vaddr = kmap_atomic_px(i915_pt_entry(pd, act_pt));
>>> + vaddr = px_vaddr(i915_pt_entry(pd, act_pt));
>>> do {
>>> GEM_BUG_ON(sg_dma_len(iter.sg) < I915_GTT_PAGE_SIZE);
>>> vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
>>> @@ -136,12 +135,10 @@ static void gen6_ppgtt_insert_entries(struct
>>> i915_address_space *vm,
>>> }
>>> if (++act_pte == GEN6_PTES) {
>>> - kunmap_atomic(vaddr);
>>> - vaddr = kmap_atomic_px(i915_pt_entry(pd, ++act_pt));
>>> + vaddr = px_vaddr(i915_pt_entry(pd, ++act_pt));
>>> act_pte = 0;
>>> }
>>> } while (1);
>>> - kunmap_atomic(vaddr);
>>> vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
>>> }
>>> @@ -235,7 +232,7 @@ static int gen6_ppgtt_init_scratch(struct
>>> gen6_ppgtt *ppgtt)
>>> goto err_scratch0;
>>> }
>>> - ret = pin_pt_dma(vm, vm->scratch[1]);
>>> + ret = map_pt_dma(vm, vm->scratch[1]);
>>> if (ret)
>>> goto err_scratch1;
>>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>>> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>>> index 176c19633412..f83496836f0f 100644
>>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>>> @@ -242,11 +242,10 @@ static u64 __gen8_ppgtt_clear(struct
>>> i915_address_space * const vm,
>>> atomic_read(&pt->used));
>>> GEM_BUG_ON(!count || count >= atomic_read(&pt->used));
>>> - vaddr = kmap_atomic_px(pt);
>>> + vaddr = px_vaddr(pt);
>>> memset64(vaddr + gen8_pd_index(start, 0),
>>> vm->scratch[0]->encode,
>>> count);
>>> - kunmap_atomic(vaddr);
>>> atomic_sub(count, &pt->used);
>>> start += count;
>>> @@ -375,7 +374,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
>>> gen8_pte_t *vaddr;
>>> pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
>>> - vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
>>> + vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
>>> do {
>>> GEM_BUG_ON(sg_dma_len(iter->sg) < I915_GTT_PAGE_SIZE);
>>> vaddr[gen8_pd_index(idx, 0)] = pte_encode | iter->dma;
>>> @@ -402,12 +401,10 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
>>> }
>>> clflush_cache_range(vaddr, PAGE_SIZE);
>>> - kunmap_atomic(vaddr);
>>> - vaddr = kmap_atomic_px(i915_pt_entry(pd,
>>> gen8_pd_index(idx, 1)));
>>> + vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
>>> }
>>> } while (1);
>>> clflush_cache_range(vaddr, PAGE_SIZE);
>>> - kunmap_atomic(vaddr);
>>> return idx;
>>> }
>>> @@ -442,7 +439,7 @@ static void gen8_ppgtt_insert_huge(struct
>>> i915_vma *vma,
>>> encode |= GEN8_PDE_PS_2M;
>>> page_size = I915_GTT_PAGE_SIZE_2M;
>>> - vaddr = kmap_atomic_px(pd);
>>> + vaddr = px_vaddr(pd);
>>> } else {
>>> struct i915_page_table *pt =
>>> i915_pt_entry(pd, __gen8_pte_index(start, 1));
>>> @@ -457,7 +454,7 @@ static void gen8_ppgtt_insert_huge(struct
>>> i915_vma *vma,
>>> rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE))
>>> maybe_64K = __gen8_pte_index(start, 1);
>>> - vaddr = kmap_atomic_px(pt);
>>> + vaddr = px_vaddr(pt);
>>> }
>>> do {
>>> @@ -491,7 +488,6 @@ static void gen8_ppgtt_insert_huge(struct
>>> i915_vma *vma,
>>> } while (rem >= page_size && index < I915_PDES);
>>> clflush_cache_range(vaddr, PAGE_SIZE);
>>> - kunmap_atomic(vaddr);
>>> /*
>>> * Is it safe to mark the 2M block as 64K? -- Either we have
>>> @@ -505,9 +501,8 @@ static void gen8_ppgtt_insert_huge(struct
>>> i915_vma *vma,
>>> !iter->sg && IS_ALIGNED(vma->node.start +
>>> vma->node.size,
>>> I915_GTT_PAGE_SIZE_2M)))) {
>>> - vaddr = kmap_atomic_px(pd);
>>> + vaddr = px_vaddr(pd);
>>> vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
>>> - kunmap_atomic(vaddr);
>>> page_size = I915_GTT_PAGE_SIZE_64K;
>>> /*
>>> @@ -523,12 +518,11 @@ static void gen8_ppgtt_insert_huge(struct
>>> i915_vma *vma,
>>> u16 i;
>>> encode = vma->vm->scratch[0]->encode;
>>> - vaddr = kmap_atomic_px(i915_pt_entry(pd, maybe_64K));
>>> + vaddr = px_vaddr(i915_pt_entry(pd, maybe_64K));
>>> for (i = 1; i < index; i += 16)
>>> memset64(vaddr + i, encode, 15);
>>> - kunmap_atomic(vaddr);
>>> }
>>> }
>>> @@ -602,7 +596,7 @@ static int gen8_init_scratch(struct
>>> i915_address_space *vm)
>>> if (IS_ERR(obj))
>>> goto free_scratch;
>>> - ret = pin_pt_dma(vm, obj);
>>> + ret = map_pt_dma(vm, obj);
>>> if (ret) {
>>> i915_gem_object_put(obj);
>>> goto free_scratch;
>>> @@ -639,7 +633,7 @@ static int gen8_preallocate_top_level_pdp(struct
>>> i915_ppgtt *ppgtt)
>>> if (IS_ERR(pde))
>>> return PTR_ERR(pde);
>>> - err = pin_pt_dma(vm, pde->pt.base);
>>> + err = map_pt_dma(vm, pde->pt.base);
>>> if (err) {
>>> i915_gem_object_put(pde->pt.base);
>>> free_pd(vm, pde);
>>> @@ -675,7 +669,7 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
>>> goto err_pd;
>>> }
>>> - err = pin_pt_dma(vm, pd->pt.base);
>>> + err = map_pt_dma(vm, pd->pt.base);
>>> if (err)
>>> goto err_pd;
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>> index 670c1271e7d5..d94628b9d89e 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>> @@ -657,7 +657,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt
>>> *ggtt)
>>> goto err_ppgtt;
>>> i915_gem_object_lock(ppgtt->vm.scratch[0], NULL);
>>> - err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
>>> + err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
>>> i915_gem_object_unlock(ppgtt->vm.scratch[0]);
>>> if (err)
>>> goto err_stash;
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
>>> b/drivers/gpu/drm/i915/gt/intel_gtt.c
>>> index 941f8af016d6..d386b89e2758 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
>>> @@ -25,27 +25,25 @@ struct drm_i915_gem_object *alloc_pt_dma(struct
>>> i915_address_space *vm, int sz)
>>> return obj;
>>> }
>>> -int pin_pt_dma(struct i915_address_space *vm, struct
>>> drm_i915_gem_object *obj)
>>> +int map_pt_dma(struct i915_address_space *vm, struct
>>> drm_i915_gem_object *obj)
>>> {
>>> - int err;
>>> + void *vaddr;
>>> - i915_gem_object_lock(obj, NULL);
>>> - err = i915_gem_object_pin_pages(obj);
>>> - i915_gem_object_unlock(obj);
>>> - if (err)
>>> - return err;
>>> + vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
>>> + if (IS_ERR(vaddr))
>>> + return PTR_ERR(vaddr);
>>> i915_gem_object_make_unshrinkable(obj);
>>> return 0;
>>> }
>>> -int pin_pt_dma_locked(struct i915_address_space *vm, struct
>>> drm_i915_gem_object *obj)
>>> +int map_pt_dma_locked(struct i915_address_space *vm, struct
>>> drm_i915_gem_object *obj)
>>> {
>>> - int err;
>>> + void *vaddr;
>>> - err = i915_gem_object_pin_pages(obj);
>>> - if (err)
>>> - return err;
>>> + vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
>>> + if (IS_ERR(vaddr))
>>> + return PTR_ERR(vaddr);
>>> i915_gem_object_make_unshrinkable(obj);
>>> return 0;
>>> @@ -155,6 +153,14 @@ void clear_pages(struct i915_vma *vma)
>>> memset(&vma->page_sizes, 0, sizeof(vma->page_sizes));
>>> }
>>> +void *__px_vaddr(struct drm_i915_gem_object *p)
>>> +{
>>> + enum i915_map_type type;
>>> +
>>> + GEM_BUG_ON(!i915_gem_object_has_pages(p));
>>> + return page_unpack_bits(p->mm.mapping, &type);
>>> +}
>>> +
>>> dma_addr_t __px_dma(struct drm_i915_gem_object *p)
>>> {
>>> GEM_BUG_ON(!i915_gem_object_has_pages(p));
>>> @@ -170,32 +176,22 @@ struct page *__px_page(struct
>>> drm_i915_gem_object *p)
>>> void
>>> fill_page_dma(struct drm_i915_gem_object *p, const u64 val,
>>> unsigned int count)
>>> {
>>> - struct page *page = __px_page(p);
>>> - void *vaddr;
>>> + void *vaddr = __px_vaddr(p);
>>> - vaddr = kmap(page);
>>> memset64(vaddr, val, count);
>>> clflush_cache_range(vaddr, PAGE_SIZE);
>>> - kunmap(page);
>>> }
>>> static void poison_scratch_page(struct drm_i915_gem_object *scratch)
>>> {
>>> - struct sgt_iter sgt;
>>> - struct page *page;
>>> + void *vaddr = __px_vaddr(scratch);
>>> u8 val;
>>> val = 0;
>>> if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
>>> val = POISON_FREE;
>>> - for_each_sgt_page(page, sgt, scratch->mm.pages) {
>>> - void *vaddr;
>>> -
>>> - vaddr = kmap(page);
>>> - memset(vaddr, val, PAGE_SIZE);
>>> - kunmap(page);
>>> - }
>>> + memset(vaddr, val, scratch->base.size);
>>> }
>>> int setup_scratch_page(struct i915_address_space *vm)
>>> @@ -225,7 +221,7 @@ int setup_scratch_page(struct i915_address_space
>>> *vm)
>>> if (IS_ERR(obj))
>>> goto skip;
>>> - if (pin_pt_dma(vm, obj))
>>> + if (map_pt_dma(vm, obj))
>>> goto skip_obj;
>>> /* We need a single contiguous page for our scratch */
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
>>> b/drivers/gpu/drm/i915/gt/intel_gtt.h
>>> index e67e34e17913..40e486704558 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
>>> @@ -180,6 +180,9 @@ struct page *__px_page(struct drm_i915_gem_object
>>> *p);
>>> dma_addr_t __px_dma(struct drm_i915_gem_object *p);
>>> #define px_dma(px) (__px_dma(px_base(px)))
>>> +void *__px_vaddr(struct drm_i915_gem_object *p);
>>> +#define px_vaddr(px) (__px_vaddr(px_base(px)))
>>> +
>>> #define px_pt(px) \
>>> __px_choose_expr(px, struct i915_page_table *, __x, \
>>> __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
>>> @@ -511,8 +514,6 @@ struct i915_ppgtt *i915_ppgtt_create(struct
>>> intel_gt *gt);
>>> void i915_ggtt_suspend(struct i915_ggtt *gtt);
>>> void i915_ggtt_resume(struct i915_ggtt *ggtt);
>>> -#define kmap_atomic_px(px) kmap_atomic(__px_page(px_base(px)))
>>> -
>>> void
>>> fill_page_dma(struct drm_i915_gem_object *p, const u64 val,
>>> unsigned int count);
>>> @@ -530,8 +531,8 @@ struct i915_page_table *alloc_pt(struct
>>> i915_address_space *vm);
>>> struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
>>> struct i915_page_directory *__alloc_pd(int npde);
>>> -int pin_pt_dma(struct i915_address_space *vm, struct
>>> drm_i915_gem_object *obj);
>>> -int pin_pt_dma_locked(struct i915_address_space *vm, struct
>>> drm_i915_gem_object *obj);
>>> +int map_pt_dma(struct i915_address_space *vm, struct
>>> drm_i915_gem_object *obj);
>>> +int map_pt_dma_locked(struct i915_address_space *vm, struct
>>> drm_i915_gem_object *obj);
>>> void free_px(struct i915_address_space *vm,
>>> struct i915_page_table *pt, int lvl);
>>> @@ -578,7 +579,7 @@ void setup_private_pat(struct intel_uncore *uncore);
>>> int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
>>> struct i915_vm_pt_stash *stash,
>>> u64 size);
>>> -int i915_vm_pin_pt_stash(struct i915_address_space *vm,
>>> +int i915_vm_map_pt_stash(struct i915_address_space *vm,
>>> struct i915_vm_pt_stash *stash);
>>> void i915_vm_free_pt_stash(struct i915_address_space *vm,
>>> struct i915_vm_pt_stash *stash);
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>>> b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>>> index 014ae8ac4480..4e3d80c2295c 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>>> @@ -87,11 +87,10 @@ write_dma_entry(struct drm_i915_gem_object *
>>> const pdma,
>>> const unsigned short idx,
>>> const u64 encoded_entry)
>>> {
>>> - u64 * const vaddr = kmap_atomic(__px_page(pdma));
>>> + u64 * const vaddr = __px_vaddr(pdma);
>>> vaddr[idx] = encoded_entry;
>>> clflush_cache_range(&vaddr[idx], sizeof(u64));
>>> - kunmap_atomic(vaddr);
>>> }
>>> void
>>> @@ -258,7 +257,7 @@ int i915_vm_alloc_pt_stash(struct
>>> i915_address_space *vm,
>>> return 0;
>>> }
>>> -int i915_vm_pin_pt_stash(struct i915_address_space *vm,
>>> +int i915_vm_map_pt_stash(struct i915_address_space *vm,
>>> struct i915_vm_pt_stash *stash)
>>> {
>>> struct i915_page_table *pt;
>>> @@ -266,7 +265,7 @@ int i915_vm_pin_pt_stash(struct
>>> i915_address_space *vm,
>>> for (n = 0; n < ARRAY_SIZE(stash->pt); n++) {
>>> for (pt = stash->pt[n]; pt; pt = pt->stash) {
>>> - err = pin_pt_dma_locked(vm, pt->base);
>>> + err = map_pt_dma_locked(vm, pt->base);
>>> if (err)
>>> return err;
>>> }
>>> diff --git a/drivers/gpu/drm/i915/i915_vma.c
>>> b/drivers/gpu/drm/i915/i915_vma.c
>>> index 07490db51cdc..eb01899ac6b7 100644
>>> --- a/drivers/gpu/drm/i915/i915_vma.c
>>> +++ b/drivers/gpu/drm/i915/i915_vma.c
>>> @@ -905,8 +905,7 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct
>>> i915_gem_ww_ctx *ww,
>>> if (err)
>>> goto err_fence;
>>> - err = i915_vm_pin_pt_stash(vma->vm,
>>> - &work->stash);
>>> + err = i915_vm_map_pt_stash(vma->vm, &work->stash);
>>> if (err)
>>> goto err_fence;
>>> }
>>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>>> b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>>> index 2e4f06eaacc1..e060e455e9f6 100644
>>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>>> @@ -186,7 +186,7 @@ static int igt_ppgtt_alloc(void *arg)
>>> if (err)
>>> goto err_ppgtt_cleanup;
>>> - err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
>>> + err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
>>> if (err) {
>>> i915_vm_free_pt_stash(&ppgtt->vm, &stash);
>>> goto err_ppgtt_cleanup;
>>> @@ -208,7 +208,7 @@ static int igt_ppgtt_alloc(void *arg)
>>> if (err)
>>> goto err_ppgtt_cleanup;
>>> - err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
>>> + err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
>>> if (err) {
>>> i915_vm_free_pt_stash(&ppgtt->vm, &stash);
>>> goto err_ppgtt_cleanup;
>>> @@ -325,11 +325,10 @@ static int lowlevel_hole(struct
>>> i915_address_space *vm,
>>> BIT_ULL(size)))
>>> goto alloc_vm_end;
>>> - err = i915_vm_pin_pt_stash(vm, &stash);
>>> + err = i915_vm_map_pt_stash(vm, &stash);
>>> if (!err)
>>> vm->allocate_va_range(vm, &stash,
>>> addr, BIT_ULL(size));
>>> -
>>> i915_vm_free_pt_stash(vm, &stash);
>>> alloc_vm_end:
>>> if (err == -EDEADLK) {
>>> @@ -1967,10 +1966,9 @@ static int igt_cs_tlb(void *arg)
>>> if (err)
>>> goto end_ww;
>>> - err = i915_vm_pin_pt_stash(vm, &stash);
>>> + err = i915_vm_map_pt_stash(vm, &stash);
>>> if (!err)
>>> vm->allocate_va_range(vm, &stash, offset, chunk_size);
>>> -
>>> i915_vm_free_pt_stash(vm, &stash);
>>> end_ww:
>>> if (err == -EDEADLK) {
>>> diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c
>>> b/drivers/gpu/drm/i915/selftests/i915_perf.c
>>> index e9d86dab8677..bfb0290967a1 100644
>>> --- a/drivers/gpu/drm/i915/selftests/i915_perf.c
>>> +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
>>> @@ -307,7 +307,7 @@ static int live_noa_gpr(void *arg)
>>> }
>>> /* Poison the ce->vm so we detect writes not to the GGTT
>>> gt->scratch */
>>> - scratch = kmap(__px_page(ce->vm->scratch[0]));
>>> + scratch = __px_vaddr(ce->vm->scratch[0]);
>>> memset(scratch, POISON_FREE, PAGE_SIZE);
>>> rq = intel_context_create_request(ce);
>>> @@ -405,7 +405,6 @@ static int live_noa_gpr(void *arg)
>>> out_rq:
>>> i915_request_put(rq);
>>> out_ce:
>>> - kunmap(__px_page(ce->vm->scratch[0]));
>>> intel_context_put(ce);
>>> out:
>>> stream_destroy(stream);
>>>
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-04-27 8:20 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-26 10:18 [PATCH 1/7] drm/i915/dg1: Fix mapping type for default state object Matthew Auld
2021-04-26 10:18 ` [PATCH 2/7] drm/i915: Update the helper to set correct mapping Matthew Auld
2021-04-26 10:18 ` [PATCH 3/7] drm/i915/gtt: map the PD up front Matthew Auld
2021-04-26 15:20 ` Tvrtko Ursulin
2021-04-26 16:18 ` Matthew Auld
2021-04-27 8:20 ` Tvrtko Ursulin
2021-04-26 10:18 ` [PATCH 4/7] drm/i915/gtt/dgfx: place the PD in LMEM Matthew Auld
2021-04-26 15:22 ` Tvrtko Ursulin
2021-04-26 16:42 ` Matthew Auld
2021-04-26 10:18 ` [PATCH 5/7] drm/i915/fbdev: Use lmem physical addresses for fb_mmap() on discrete Matthew Auld
2021-04-26 10:18 ` [PATCH 6/7] drm/i915/lmem: Bypass aperture when lmem is available Matthew Auld
2021-04-26 10:18 ` [PATCH 7/7] drm/i915: Return error value when bo not in LMEM for discrete Matthew Auld
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