* [PATCHv2 1/5] rtc: m41t80: add support for fixed clock
2021-04-28 22:29 [PATCHv2 0/5] Support for GE B1x5v2 and B1x5Pv2 Sebastian Reichel
@ 2021-04-28 22:29 ` Sebastian Reichel
2021-04-29 1:11 ` Saravana Kannan
2021-05-05 23:00 ` Rob Herring
2021-04-28 22:29 ` [PATCHv2 2/5] drm/imx: Add 8 pixel alignment fix Sebastian Reichel
` (4 subsequent siblings)
5 siblings, 2 replies; 13+ messages in thread
From: Sebastian Reichel @ 2021-04-28 22:29 UTC (permalink / raw)
To: Sebastian Reichel, Philipp Zabel, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, Saravana Kannan,
devicetree, David Airlie, linux-kernel, dri-devel, Rob Herring,
linux-mtd, Miquel Raynal, kernel, linux-arm-kernel
Congatec's QMX6 system on module (SoM) uses a m41t62 as RTC. The
modules SQW clock output defaults to 32768 Hz. This behaviour is
used to provide the i.MX6 CKIL clock. Once the RTC driver is probed,
the clock is disabled and all i.MX6 functionality depending on
the 32 KHz clock has undefined behaviour. For example when using
the hardware watchdog the system will likely do arbitrary reboots.
Referencing the m41t62 directly results in a deadlock. The kernel
will see, that i.MX6 system clock needs the RTC clock and do probe
deferral. But the i.MX6 I2C module never becomes usable without the
i.MX6 CKIL clock and thus the RTC's clock will not be probed. So
from the kernel's perspective this is a chicken-and-egg problem.
Technically everything is fine by not touching anything, since
the RTC clock correctly enables the clock on reset (i.e. on
battery backup power loss) and also the bootloader enables it
in case an something (e.g. an unpatched kernel) disabled this
incorrectly.
A workaround for this issue is describing the square wave pin
as fixed-clock, which is registered early and basically how
this pin is used on the i.MX6.
Suggested-by: Saravana Kannan <saravanak@google.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Documentation/devicetree/bindings/rtc/rtc-m41t80.txt | 9 +++++++++
drivers/rtc/rtc-m41t80.c | 12 ++++++++++++
2 files changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt
index c746cb221210..cdd196b1e9bd 100644
--- a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt
+++ b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt
@@ -21,10 +21,19 @@ Optional properties:
clock name
- wakeup-source: Enables wake up of host system on alarm
+Optional child node:
+- clock: Provide this if the square wave pin is used as boot-enabled fixed clock.
+
Example:
rtc@68 {
compatible = "st,m41t80";
reg = <0x68>;
interrupt-parent = <&UIC0>;
interrupts = <0x9 0x8>;
+
+ clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
};
diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c
index 89128fc29ccc..b3ece42b6f90 100644
--- a/drivers/rtc/rtc-m41t80.c
+++ b/drivers/rtc/rtc-m41t80.c
@@ -544,10 +544,22 @@ static struct clk *m41t80_sqw_register_clk(struct m41t80_data *m41t80)
{
struct i2c_client *client = m41t80->client;
struct device_node *node = client->dev.of_node;
+ struct device_node *fixed_clock;
struct clk *clk;
struct clk_init_data init;
int ret;
+ fixed_clock = of_get_child_by_name(node, "clock");
+ if (fixed_clock) {
+ /*
+ * skip registering square wave clock when a fixed
+ * clock has been registered. The fixed clock is
+ * registered automatically when being referenced.
+ */
+ of_node_put(fixed_clock);
+ return 0;
+ }
+
/* First disable the clock */
ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
if (ret < 0)
--
2.30.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCHv2 1/5] rtc: m41t80: add support for fixed clock
2021-04-28 22:29 ` [PATCHv2 1/5] rtc: m41t80: add support for fixed clock Sebastian Reichel
@ 2021-04-29 1:11 ` Saravana Kannan
2021-05-05 23:00 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Saravana Kannan @ 2021-04-29 1:11 UTC (permalink / raw)
To: Sebastian Reichel
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
David Airlie, Shawn Guo, Sascha Hauer, LKML, dri-devel,
Rob Herring, linux-mtd, NXP Linux Team, Pengutronix Kernel Team,
Miquel Raynal, Collabora Kernel ML, linux-arm-kernel
On Wed, Apr 28, 2021 at 3:29 PM Sebastian Reichel
<sebastian.reichel@collabora.com> wrote:
>
> Congatec's QMX6 system on module (SoM) uses a m41t62 as RTC. The
> modules SQW clock output defaults to 32768 Hz. This behaviour is
> used to provide the i.MX6 CKIL clock. Once the RTC driver is probed,
> the clock is disabled and all i.MX6 functionality depending on
> the 32 KHz clock has undefined behaviour. For example when using
> the hardware watchdog the system will likely do arbitrary reboots.
>
> Referencing the m41t62 directly results in a deadlock. The kernel
> will see, that i.MX6 system clock needs the RTC clock and do probe
> deferral. But the i.MX6 I2C module never becomes usable without the
> i.MX6 CKIL clock and thus the RTC's clock will not be probed. So
> from the kernel's perspective this is a chicken-and-egg problem.
>
> Technically everything is fine by not touching anything, since
> the RTC clock correctly enables the clock on reset (i.e. on
> battery backup power loss) and also the bootloader enables it
> in case an something (e.g. an unpatched kernel) disabled this
> incorrectly.
>
> A workaround for this issue is describing the square wave pin
> as fixed-clock, which is registered early and basically how
> this pin is used on the i.MX6.
>
> Suggested-by: Saravana Kannan <saravanak@google.com>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> Documentation/devicetree/bindings/rtc/rtc-m41t80.txt | 9 +++++++++
> drivers/rtc/rtc-m41t80.c | 12 ++++++++++++
> 2 files changed, 21 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt
> index c746cb221210..cdd196b1e9bd 100644
> --- a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt
> +++ b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt
> @@ -21,10 +21,19 @@ Optional properties:
> clock name
> - wakeup-source: Enables wake up of host system on alarm
>
> +Optional child node:
> +- clock: Provide this if the square wave pin is used as boot-enabled fixed clock.
> +
> Example:
> rtc@68 {
> compatible = "st,m41t80";
> reg = <0x68>;
> interrupt-parent = <&UIC0>;
> interrupts = <0x9 0x8>;
> +
> + clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> };
> diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c
> index 89128fc29ccc..b3ece42b6f90 100644
> --- a/drivers/rtc/rtc-m41t80.c
> +++ b/drivers/rtc/rtc-m41t80.c
> @@ -544,10 +544,22 @@ static struct clk *m41t80_sqw_register_clk(struct m41t80_data *m41t80)
> {
> struct i2c_client *client = m41t80->client;
> struct device_node *node = client->dev.of_node;
> + struct device_node *fixed_clock;
> struct clk *clk;
> struct clk_init_data init;
> int ret;
>
> + fixed_clock = of_get_child_by_name(node, "clock");
> + if (fixed_clock) {
> + /*
> + * skip registering square wave clock when a fixed
> + * clock has been registered. The fixed clock is
> + * registered automatically when being referenced.
> + */
> + of_node_put(fixed_clock);
> + return 0;
> + }
> +
> /* First disable the clock */
> ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
> if (ret < 0)
Reviewed-by: Saravana Kannan <saravanak@google.com>
-Saravana
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCHv2 1/5] rtc: m41t80: add support for fixed clock
2021-04-28 22:29 ` [PATCHv2 1/5] rtc: m41t80: add support for fixed clock Sebastian Reichel
2021-04-29 1:11 ` Saravana Kannan
@ 2021-05-05 23:00 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Rob Herring @ 2021-05-05 23:00 UTC (permalink / raw)
To: Sebastian Reichel
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni,
Pengutronix Kernel Team, Saravana Kannan, devicetree,
David Airlie, Shawn Guo, Sascha Hauer, linux-kernel, dri-devel,
Rob Herring, linux-mtd, NXP Linux Team, Miquel Raynal, kernel,
linux-arm-kernel
On Thu, 29 Apr 2021 00:29:49 +0200, Sebastian Reichel wrote:
> Congatec's QMX6 system on module (SoM) uses a m41t62 as RTC. The
> modules SQW clock output defaults to 32768 Hz. This behaviour is
> used to provide the i.MX6 CKIL clock. Once the RTC driver is probed,
> the clock is disabled and all i.MX6 functionality depending on
> the 32 KHz clock has undefined behaviour. For example when using
> the hardware watchdog the system will likely do arbitrary reboots.
>
> Referencing the m41t62 directly results in a deadlock. The kernel
> will see, that i.MX6 system clock needs the RTC clock and do probe
> deferral. But the i.MX6 I2C module never becomes usable without the
> i.MX6 CKIL clock and thus the RTC's clock will not be probed. So
> from the kernel's perspective this is a chicken-and-egg problem.
>
> Technically everything is fine by not touching anything, since
> the RTC clock correctly enables the clock on reset (i.e. on
> battery backup power loss) and also the bootloader enables it
> in case an something (e.g. an unpatched kernel) disabled this
> incorrectly.
>
> A workaround for this issue is describing the square wave pin
> as fixed-clock, which is registered early and basically how
> this pin is used on the i.MX6.
>
> Suggested-by: Saravana Kannan <saravanak@google.com>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> Documentation/devicetree/bindings/rtc/rtc-m41t80.txt | 9 +++++++++
> drivers/rtc/rtc-m41t80.c | 12 ++++++++++++
> 2 files changed, 21 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCHv2 2/5] drm/imx: Add 8 pixel alignment fix
2021-04-28 22:29 [PATCHv2 0/5] Support for GE B1x5v2 and B1x5Pv2 Sebastian Reichel
2021-04-28 22:29 ` [PATCHv2 1/5] rtc: m41t80: add support for fixed clock Sebastian Reichel
@ 2021-04-28 22:29 ` Sebastian Reichel
2021-05-10 14:47 ` Philipp Zabel
2021-04-28 22:29 ` [PATCHv2 3/5] dt-bindings: vendor-prefixes: add congatec Sebastian Reichel
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Sebastian Reichel @ 2021-04-28 22:29 UTC (permalink / raw)
To: Sebastian Reichel, Philipp Zabel, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, Saravana Kannan,
devicetree, David Airlie, linux-kernel, dri-devel, Rob Herring,
linux-mtd, Miquel Raynal, Boris Brezillon, kernel,
linux-arm-kernel
Some standard resolutions like 1366x768 do not work properly with
i.MX6 SoCs, since the horizontal resolution needs to be aligned
to 8 pixels (so 1360x768 or 1368x768 would work).
This patch allocates framebuffers allocated to 8 pixels. The extra
time required to send the extra pixels are removed from the blank
time. In order to expose the correct display size to userspace,
the stride is increased without increasing the width.
Without this patch systems with this display resolution hang
indefinitely during boot up.
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/gpu/drm/imx/imx-drm-core.c | 19 ++++++++++++++++++-
drivers/gpu/drm/imx/imx-ldb.c | 5 +++++
drivers/gpu/drm/imx/ipuv3-crtc.c | 11 ++++++++++-
drivers/gpu/drm/imx/ipuv3-plane.c | 19 +++++++++++++++----
drivers/gpu/ipu-v3/ipu-dc.c | 5 +++++
drivers/gpu/ipu-v3/ipu-di.c | 7 +++++++
6 files changed, 60 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c
index e6a88c8cbd69..8457b9788cda 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -145,9 +145,26 @@ static const struct drm_ioctl_desc imx_drm_ioctls[] = {
/* none so far */
};
+static int imx_drm_dumb_create(struct drm_file *file_priv,
+ struct drm_device *drm,
+ struct drm_mode_create_dumb *args)
+{
+ u32 width = args->width;
+ int ret;
+
+ args->width = ALIGN(width, 8);
+
+ ret = drm_gem_cma_dumb_create(file_priv, drm, args);
+ if (ret)
+ return ret;
+
+ args->width = width;
+ return ret;
+}
+
static const struct drm_driver imx_drm_driver = {
.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
- DRM_GEM_CMA_DRIVER_OPS,
+ DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(imx_drm_dumb_create),
.ioctls = imx_drm_ioctls,
.num_ioctls = ARRAY_SIZE(imx_drm_ioctls),
.fops = &imx_drm_driver_fops,
diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c
index ffdc492c5bc5..53132ddf9587 100644
--- a/drivers/gpu/drm/imx/imx-ldb.c
+++ b/drivers/gpu/drm/imx/imx-ldb.c
@@ -274,6 +274,11 @@ imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
"%s: mode exceeds 85 MHz pixel clock\n", __func__);
}
+ if (!IS_ALIGNED(mode->hdisplay, 8)) {
+ dev_warn(ldb->dev,
+ "%s: hdisplay does not align to 8 byte\n", __func__);
+ }
+
if (dual) {
serial_clk = 3500UL * mode->clock;
imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c
index e6431a227feb..9c8829f945b2 100644
--- a/drivers/gpu/drm/imx/ipuv3-crtc.c
+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
@@ -305,10 +305,19 @@ static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
drm_display_mode_to_videomode(mode, &sig_cfg.mode);
+ if (!IS_ALIGNED(sig_cfg.mode.hactive, 8)) {
+ unsigned int new_hactive = ALIGN(sig_cfg.mode.hactive, 8);
+
+ dev_warn(ipu_crtc->dev, "8-pixel align hactive %d -> %d\n",
+ sig_cfg.mode.hactive, new_hactive);
+
+ sig_cfg.mode.hfront_porch = new_hactive - sig_cfg.mode.hactive;
+ sig_cfg.mode.hactive = new_hactive;
+ }
ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
mode->flags & DRM_MODE_FLAG_INTERLACE,
- imx_crtc_state->bus_format, mode->hdisplay);
+ imx_crtc_state->bus_format, sig_cfg.mode.hactive);
ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
}
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
index fa5009705365..06ad6dece61f 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -30,6 +30,11 @@ to_ipu_plane_state(struct drm_plane_state *p)
return container_of(p, struct ipu_plane_state, base);
}
+static unsigned int ipu_src_rect_width(const struct drm_plane_state *state)
+{
+ return ALIGN(drm_rect_width(&state->src) >> 16, 8);
+}
+
static inline struct ipu_plane *to_ipu_plane(struct drm_plane *p)
{
return container_of(p, struct ipu_plane, base);
@@ -415,6 +420,12 @@ static int ipu_plane_atomic_check(struct drm_plane *plane,
if (old_fb && fb->pitches[0] != old_fb->pitches[0])
crtc_state->mode_changed = true;
+ if (ALIGN(fb->width, 8) * fb->format->cpp[0] >
+ fb->pitches[0] + fb->offsets[0]) {
+ dev_warn(dev, "pitch is not big enough for 8 pixels alignment");
+ return -EINVAL;
+ }
+
switch (fb->format->format) {
case DRM_FORMAT_YUV420:
case DRM_FORMAT_YVU420:
@@ -590,7 +601,7 @@ static void ipu_plane_atomic_update(struct drm_plane *plane,
if (ipu_state->use_pre) {
axi_id = ipu_chan_assign_axi_id(ipu_plane->dma);
ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id,
- drm_rect_width(&new_state->src) >> 16,
+ ipu_src_rect_width(new_state),
drm_rect_height(&new_state->src) >> 16,
fb->pitches[0], fb->format->format,
fb->modifier, &eba);
@@ -623,9 +634,9 @@ static void ipu_plane_atomic_update(struct drm_plane *plane,
break;
}
- ipu_dmfc_config_wait4eot(ipu_plane->dmfc, drm_rect_width(dst));
+ ipu_dmfc_config_wait4eot(ipu_plane->dmfc, ALIGN(drm_rect_width(dst), 8));
- width = drm_rect_width(&new_state->src) >> 16;
+ width = ipu_src_rect_width(new_state);
height = drm_rect_height(&new_state->src) >> 16;
info = drm_format_info(fb->format->format);
ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0],
@@ -690,7 +701,7 @@ static void ipu_plane_atomic_update(struct drm_plane *plane,
ipu_cpmem_zero(ipu_plane->alpha_ch);
ipu_cpmem_set_resolution(ipu_plane->alpha_ch,
- drm_rect_width(&new_state->src) >> 16,
+ ipu_src_rect_width(new_state),
drm_rect_height(&new_state->src) >> 16);
ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8);
ipu_cpmem_set_high_priority(ipu_plane->alpha_ch);
diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 34b4075a6a8e..ca96b235491a 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -167,6 +167,11 @@ int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
dc->di = ipu_di_get_num(di);
+ if (!IS_ALIGNED(width, 8)) {
+ dev_warn(priv->dev,
+ "%s: hactive does not align to 8 byte\n", __func__);
+ }
+
map = ipu_bus_format_to_map(bus_format);
/*
diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index e617f60afeea..666223c6bec4 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -506,6 +506,13 @@ int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode)
{
u32 diff;
+ if (!IS_ALIGNED(mode->hactive, 8) &&
+ mode->hfront_porch < ALIGN(mode->hactive, 8) - mode->hactive) {
+ dev_err(di->ipu->dev, "hactive %d is not aligned to 8 and front porch is too small to compensate\n",
+ mode->hactive);
+ return -EINVAL;
+ }
+
if (mode->vfront_porch >= 2)
return 0;
--
2.30.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCHv2 2/5] drm/imx: Add 8 pixel alignment fix
2021-04-28 22:29 ` [PATCHv2 2/5] drm/imx: Add 8 pixel alignment fix Sebastian Reichel
@ 2021-05-10 14:47 ` Philipp Zabel
0 siblings, 0 replies; 13+ messages in thread
From: Philipp Zabel @ 2021-05-10 14:47 UTC (permalink / raw)
To: Sebastian Reichel, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, Saravana Kannan,
devicetree, David Airlie, linux-kernel, dri-devel, Rob Herring,
linux-mtd, Miquel Raynal, Boris Brezillon, kernel,
linux-arm-kernel
Hi Sebastian,
On Thu, 2021-04-29 at 00:29 +0200, Sebastian Reichel wrote:
> Some standard resolutions like 1366x768 do not work properly with
> i.MX6 SoCs, since the horizontal resolution needs to be aligned
> to 8 pixels (so 1360x768 or 1368x768 would work).
>
> This patch allocates framebuffers allocated to 8 pixels. The extra
> time required to send the extra pixels are removed from the blank
> time. In order to expose the correct display size to userspace,
> the stride is increased without increasing the width.
>
> Without this patch systems with this display resolution hang
> indefinitely during boot up.
>
> Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Thank you, I've rebased and applied this patch on top of imx-drm/next.
regards
Philipp
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCHv2 3/5] dt-bindings: vendor-prefixes: add congatec
2021-04-28 22:29 [PATCHv2 0/5] Support for GE B1x5v2 and B1x5Pv2 Sebastian Reichel
2021-04-28 22:29 ` [PATCHv2 1/5] rtc: m41t80: add support for fixed clock Sebastian Reichel
2021-04-28 22:29 ` [PATCHv2 2/5] drm/imx: Add 8 pixel alignment fix Sebastian Reichel
@ 2021-04-28 22:29 ` Sebastian Reichel
2021-05-05 23:01 ` Rob Herring
2021-04-28 22:29 ` [PATCHv2 4/5] dt-bindings: arm: fsl: add GE B1x5pv2 boards Sebastian Reichel
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Sebastian Reichel @ 2021-04-28 22:29 UTC (permalink / raw)
To: Sebastian Reichel, Philipp Zabel, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, Saravana Kannan,
devicetree, David Airlie, linux-kernel, dri-devel, Rob Herring,
linux-mtd, Miquel Raynal, kernel, linux-arm-kernel
Document binding for congatec.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index c88b1cfb52cb..10e3ce8a29c5 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -247,6 +247,8 @@ patternProperties:
description: Colorful GRP, Shenzhen Xueyushi Technology Ltd.
"^compulab,.*":
description: CompuLab Ltd.
+ "^congatec,.*":
+ description: congatec GmbH
"^coreriver,.*":
description: CORERIVER Semiconductor Co.,Ltd.
"^corpro,.*":
--
2.30.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCHv2 3/5] dt-bindings: vendor-prefixes: add congatec
2021-04-28 22:29 ` [PATCHv2 3/5] dt-bindings: vendor-prefixes: add congatec Sebastian Reichel
@ 2021-05-05 23:01 ` Rob Herring
0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2021-05-05 23:01 UTC (permalink / raw)
To: Sebastian Reichel
Cc: linux-rtc, devicetree, Alexandre Belloni,
Pengutronix Kernel Team, Saravana Kannan, Alessandro Zummo,
David Airlie, Shawn Guo, Sascha Hauer, linux-kernel, dri-devel,
Rob Herring, linux-mtd, NXP Linux Team, Miquel Raynal, kernel,
linux-arm-kernel
On Thu, 29 Apr 2021 00:29:51 +0200, Sebastian Reichel wrote:
> Document binding for congatec.
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCHv2 4/5] dt-bindings: arm: fsl: add GE B1x5pv2 boards
2021-04-28 22:29 [PATCHv2 0/5] Support for GE B1x5v2 and B1x5Pv2 Sebastian Reichel
` (2 preceding siblings ...)
2021-04-28 22:29 ` [PATCHv2 3/5] dt-bindings: vendor-prefixes: add congatec Sebastian Reichel
@ 2021-04-28 22:29 ` Sebastian Reichel
2021-05-05 23:02 ` Rob Herring
2021-04-28 22:29 ` [PATCHv2 5/5] ARM: dts: imx6: Add GE B1x5v2 Sebastian Reichel
2021-05-24 22:29 ` (subset) [PATCHv2 0/5] Support for GE B1x5v2 and B1x5Pv2 Alexandre Belloni
5 siblings, 1 reply; 13+ messages in thread
From: Sebastian Reichel @ 2021-04-28 22:29 UTC (permalink / raw)
To: Sebastian Reichel, Philipp Zabel, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, Saravana Kannan,
devicetree, David Airlie, linux-kernel, dri-devel, Rob Herring,
linux-mtd, Miquel Raynal, kernel, linux-arm-kernel
Document the compatible for GE B1x5pv2 boards.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index e3c50f231d71..6e5b14c75325 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -400,6 +400,17 @@ properties:
- const: armadeus,imx6dl-apf6 # APF6 (Solo) SoM
- const: fsl,imx6dl
+ - description: i.MX6DL based congatec QMX6 Boards
+ items:
+ - enum:
+ - ge,imx6dl-b105v2 # General Electric B105v2
+ - ge,imx6dl-b105pv2 # General Electric B105Pv2
+ - ge,imx6dl-b125v2 # General Electric B125v2
+ - ge,imx6dl-b125pv2 # General Electric B125Pv2
+ - ge,imx6dl-b155v2 # General Electric B155v2
+ - const: congatec,qmx6
+ - const: fsl,imx6dl
+
- description: i.MX6DL based DFI FS700-M60-6DL Board
items:
- const: dfi,fs700-m60-6dl
--
2.30.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCHv2 4/5] dt-bindings: arm: fsl: add GE B1x5pv2 boards
2021-04-28 22:29 ` [PATCHv2 4/5] dt-bindings: arm: fsl: add GE B1x5pv2 boards Sebastian Reichel
@ 2021-05-05 23:02 ` Rob Herring
0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2021-05-05 23:02 UTC (permalink / raw)
To: Sebastian Reichel
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, Saravana Kannan,
devicetree, David Airlie, Shawn Guo, Sascha Hauer, linux-kernel,
dri-devel, Rob Herring, linux-mtd, NXP Linux Team,
Pengutronix Kernel Team, Miquel Raynal, kernel, linux-arm-kernel
On Thu, 29 Apr 2021 00:29:52 +0200, Sebastian Reichel wrote:
> Document the compatible for GE B1x5pv2 boards.
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCHv2 5/5] ARM: dts: imx6: Add GE B1x5v2
2021-04-28 22:29 [PATCHv2 0/5] Support for GE B1x5v2 and B1x5Pv2 Sebastian Reichel
` (3 preceding siblings ...)
2021-04-28 22:29 ` [PATCHv2 4/5] dt-bindings: arm: fsl: add GE B1x5pv2 boards Sebastian Reichel
@ 2021-04-28 22:29 ` Sebastian Reichel
2021-05-22 14:04 ` Shawn Guo
2021-05-24 22:29 ` (subset) [PATCHv2 0/5] Support for GE B1x5v2 and B1x5Pv2 Alexandre Belloni
5 siblings, 1 reply; 13+ messages in thread
From: Sebastian Reichel @ 2021-04-28 22:29 UTC (permalink / raw)
To: Sebastian Reichel, Philipp Zabel, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, Saravana Kannan,
devicetree, David Airlie, linux-kernel, dri-devel, Rob Herring,
linux-mtd, Miquel Raynal, kernel, linux-arm-kernel
This adds device tree files for the General Electric Healthcare
(GEHC) B1x5v2 series. All models make use of Congatec's QMX6 module,
which is described in its own device tree include, so that it can
also be used by other boards.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm/boot/dts/Makefile | 5 +
arch/arm/boot/dts/imx6dl-b105pv2.dts | 35 ++
arch/arm/boot/dts/imx6dl-b105v2.dts | 35 ++
arch/arm/boot/dts/imx6dl-b125pv2.dts | 33 ++
arch/arm/boot/dts/imx6dl-b125v2.dts | 33 ++
arch/arm/boot/dts/imx6dl-b155v2.dts | 36 ++
arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi | 434 ++++++++++++++++++
arch/arm/boot/dts/imx6dl-b1x5v2.dtsi | 61 +++
arch/arm/boot/dts/imx6dl-qmx6.dtsi | 624 ++++++++++++++++++++++++++
9 files changed, 1296 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-b105pv2.dts
create mode 100644 arch/arm/boot/dts/imx6dl-b105v2.dts
create mode 100644 arch/arm/boot/dts/imx6dl-b125pv2.dts
create mode 100644 arch/arm/boot/dts/imx6dl-b125v2.dts
create mode 100644 arch/arm/boot/dts/imx6dl-b155v2.dts
create mode 100644 arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi
create mode 100644 arch/arm/boot/dts/imx6dl-b1x5v2.dtsi
create mode 100644 arch/arm/boot/dts/imx6dl-qmx6.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f8f09c5066e7..811f22ed1e37 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -515,6 +515,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-dms-ba16.dtb \
imx6q-emcon-avari.dtb \
imx6q-evi.dtb \
+ imx6dl-b105v2.dtb \
+ imx6dl-b105pv2.dtb \
+ imx6dl-b125v2.dtb \
+ imx6dl-b125pv2.dtb \
+ imx6dl-b155v2.dtb \
imx6q-gk802.dtb \
imx6q-gw51xx.dtb \
imx6q-gw52xx.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-b105pv2.dts b/arch/arm/boot/dts/imx6dl-b105pv2.dts
new file mode 100644
index 000000000000..0d5be2f9471f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b105pv2.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B105Pv2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5pv2.dtsi"
+
+/ {
+ model = "General Electric B105Pv2";
+ compatible = "ge,imx6dl-b105pv2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g101evn010";
+ status = "okay";
+ };
+};
+
+&i2c3 {
+ touchscreen@41 {
+ reg = <0x41>;
+ compatible = "ilitek,ili251x";
+
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>;
+
+ touchscreen-size-x = <1280>;
+ touchscreen-size-y = <800>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-b105v2.dts b/arch/arm/boot/dts/imx6dl-b105v2.dts
new file mode 100644
index 000000000000..72a085348304
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b105v2.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B105v2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5v2.dtsi"
+
+/ {
+ model = "General Electric B105v2";
+ compatible = "ge,imx6dl-b105v2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g101evn010";
+ status = "okay";
+ };
+};
+
+&i2c3 {
+ touchscreen@41 {
+ reg = <0x41>;
+ compatible = "ilitek,ili251x";
+
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>;
+
+ touchscreen-size-x = <1280>;
+ touchscreen-size-y = <800>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-b125pv2.dts b/arch/arm/boot/dts/imx6dl-b125pv2.dts
new file mode 100644
index 000000000000..8fd6c8ed6750
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b125pv2.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B125Pv2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5pv2.dtsi"
+
+/ {
+ model = "General Electric B125Pv2";
+ compatible = "ge,imx6dl-b125pv2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g121ean01";
+ status = "okay";
+ };
+};
+
+&i2c3 {
+ touchscreen@2a {
+ reg = <0x2a>;
+ compatible = "eeti,exc80h60";
+
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-b125v2.dts b/arch/arm/boot/dts/imx6dl-b125v2.dts
new file mode 100644
index 000000000000..eb26ffde9f72
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b125v2.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B125v2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5v2.dtsi"
+
+/ {
+ model = "General Electric B125v2";
+ compatible = "ge,imx6dl-b125v2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g121ean01";
+ status = "okay";
+ };
+};
+
+&i2c3 {
+ touchscreen@2a {
+ reg = <0x2a>;
+ compatible = "eeti,exc80h60";
+
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-b155v2.dts b/arch/arm/boot/dts/imx6dl-b155v2.dts
new file mode 100644
index 000000000000..620cd6f9da82
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b155v2.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B155v2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5v2.dtsi"
+
+/ {
+ model = "General Electric B155v2";
+ compatible = "ge,imx6dl-b155v2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g156xtn01";
+ status = "okay";
+ };
+};
+
+&i2c3 {
+ touchscreen@2a {
+ reg = <0x2a>;
+ compatible = "eeti,exc80h84";
+
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi
new file mode 100644
index 000000000000..1f9e66e1afc0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi
@@ -0,0 +1,434 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B1x5v2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+#include <dt-bindings/input/input.h>
+#include "imx6dl-qmx6.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ /* Do not allow frequencies above 800MHz */
+ cpus {
+ cpu@0 {
+ operating-points = <
+ /* kHz uV */
+ 792000 1175000
+ 396000 1150000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 792000 1175000
+ 396000 1175000
+ >;
+ };
+
+ cpu@1 {
+ operating-points = <
+ /* kHz uV */
+ 792000 1175000
+ 396000 1150000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 792000 1175000
+ 396000 1175000
+ >;
+ };
+ };
+
+ reg_syspwr: regulator-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "SYS_PWR";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ };
+
+ reg_5v_pmc: regulator-5v-pmc {
+ compatible = "regulator-fixed";
+ regulator-name = "5V PMC";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <®_syspwr>;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <®_syspwr>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <®_syspwr>;
+ };
+
+ reg_5v0_audio: regulator-5v0-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "5V0_AUDIO";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_5v>;
+
+ gpio = <&tca6424a 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ /*
+ * This must be always-on for da7212, which has some not
+ * properly documented dependencies for it's speaker supply
+ * pin. The issue manifests as speaker volume being very low.
+ */
+ regulator-always-on;
+ };
+
+
+ reg_3v3_audio: regulator-3v3-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3_AUDIO";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_3v3>;
+
+ pinctrl-0 = <&pinctrl_q7_hda_rst>;
+ pinctrl-names = "default";
+ gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_2v5_audio: regulator-2v5-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "2V5_AUDIO";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ vin-supply = <®_3v3_audio>;
+
+ };
+
+ reg_wlan: regulator-wlan {
+ compatible = "regulator-fixed";
+ regulator-name = "WLAN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_sdio_pwr>;
+ gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ reg_bl: regulator-backlight {
+ compatible = "regulator-fixed";
+ regulator-name = "LED_VCC";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <®_syspwr>;
+
+ pinctrl-0 = <&pinctrl_q7_lcd_power>;
+ pinctrl-names = "default";
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_lcd: regulator-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "LCD_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_5v>;
+ };
+
+ usb_power: regulator-usb-power {
+ compatible = "regulator-fixed";
+ regulator-name = "USB POWER";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_5v>;
+ };
+
+ charger: battery-charger {
+ compatible = "gpio-charger"; /* ti,bq24172 */
+
+ charger-type = "mains";
+ gpios = <&tca6424a 3 GPIO_ACTIVE_LOW>;
+ charge-current-limit-gpios = <&tca6424a 11 GPIO_ACTIVE_HIGH>,
+ <&tca6424a 12 GPIO_ACTIVE_HIGH>;
+ charge-current-limit-mapping = <1300000 0x0>,
+ <700000 0x1>,
+ <0 0x2>;
+
+ charge-status-gpios = <&tca6424a 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_spi_cs1>;
+ gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
+ };
+
+ power-button-key {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_slp_btn>;
+
+ power-button {
+ label = "power button";
+ gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ rotary-encoder-key {
+ compatible = "gpio-keys";
+
+ rotary-encoder-press {
+ label = "rotary-encoder press";
+ gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_ENTER>;
+ linux,can-disable;
+ };
+ };
+
+ rotary-encoder {
+ compatible = "rotary-encoder";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio2 &pinctrl_q7_gpio4>;
+ gpios = <&gpio4 26 GPIO_ACTIVE_LOW>, <&gpio1 0 GPIO_ACTIVE_LOW>;
+ rotary-encoder,relative-axis;
+ rotary-encoder,steps-per-period = <2>;
+ wakeup-source;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>;
+
+ alarm1 {
+ label = "alarm:red";
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ alarm2 {
+ label = "alarm:yellow";
+ gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+ };
+
+ alarm3 {
+ label = "alarm:blue";
+ gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_backlight_enable>;
+ power-supply = <®_bl>;
+ pwms = <&pwm4 0 5000000 0>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
+ default-brightness-level = <179>;
+ enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ panel {
+ backlight = <&backlight>;
+ power-supply = <®_lcd>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+
+ simple-audio-card,widgets = "Speaker", "Ext Spk";
+ simple-audio-card,audio-routing = "Ext Spk", "LINE";
+
+ simple-audio-card,cpu {
+ sound-dai = <&ssi1>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&codec>;
+ };
+ };
+
+ clk_ext_audio_codec: clock-codec {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+};
+
+&i2c1 {
+ battery: battery@b {
+ compatible = "ti,bq20z65", "sbs,sbs-battery";
+ reg = <0x0b>;
+
+ sbs,battery-detect-gpios = <&tca6424a 5 GPIO_ACTIVE_LOW>;
+ sbs,i2c-retry-count = <5>;
+
+ power-supplies = <&charger>;
+ };
+
+ codec: audio-codec@1a {
+ compatible = "dlg,da7212";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+ VDDA-supply = <®_2v5_audio>;
+ VDDSP-supply = <®_5v0_audio>;
+ VDDMIC-supply = <®_3v3_audio>;
+ VDDIO-supply = <®_3v3_audio>;
+ clocks = <&clk_ext_audio_codec>;
+ clock-names = "mclk";
+ };
+};
+
+&i2c5 {
+ tmp75: temperature-sensor@48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ vs-supply = <®_3v3>;
+ interrupt-parent = <&tca6424a>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ tca6424a: gpio-controller@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ vcc-supply = <®_3v3>;
+
+ interrupt-parent = <&gpio7>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-line-names = "GPIO_ROTOR#", "ACM_IO_INT", "TMP_SENSOR_IRQ", "AC_IN",
+ "TF_S", "BATT_T", "LED_INC_CHAR", "ACM1_OCF",
+ "ACM2_OCF", "ACM_IO_RST", "USB1_POWER_EN", "EGPIO_CC_CTL0",
+ "EGPIO_CC_CTL1", "12V_OEMNBP_EN", "CP2105_RST", "",
+ "SPEAKER_PA_EN", "ARM7_UPI_RESET", "ARM7_PWR_RST", "NURSE_CALL",
+ "MARKER_EN", "EGPIO_TOUCH_RST", "PRESSURE_INT1", "PRESSURE_INT2";
+
+ };
+};
+
+&fec {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&audmux {
+ status = "okay";
+};
+
+&ssi1 {
+ fsl,mode = "i2s-slave";
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <&usb_power>;
+ disable-over-current;
+ dr_mode = "host";
+ status = "okay";
+
+ /*
+ * TPS2051BDGN fault-gpio is connected to Q7[86] USB_0_1_OC_N.
+ * On QMX6 this is not connceted to the i.MX6, but to the USB Hub
+ * from &usbh1. This means, that we cannot easily detect and handle
+ * over-current events. Fortunately the regulator limits the current
+ * automatically, so the hardware is still protected.
+ */
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&ldb {
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ status = "okay";
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+
+ port@4 {
+ reg = <4>;
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&usdhc4 {
+ /* WiFi module */
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ wakeup-source;
+ keep-power-in-suspend;
+ cap-power-off-card;
+ max-frequency = <25000000>;
+ vmmc-supply = <®_wlan>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1837";
+ reg = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio7>;
+
+ interrupt-parent = <&gpio4>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+
+ tcxo-clock-frequency = <26000000>;
+ };
+
+};
diff --git a/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi
new file mode 100644
index 000000000000..b4c6fbd802fb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B1x5v2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+#include <dt-bindings/input/input.h>
+#include "imx6dl-b1x5pv2.dtsi"
+
+/ {
+ reg_3v3_acm: regulator-3v3-acm {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3 ACM";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <®_3v3>;
+ };
+};
+
+&i2c1 {
+ tca6416: gpio-controller@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ vcc-supply = <®_3v3_acm>;
+
+ /*
+ * TCA6424 cannot handle low type interrupts at the moment and
+ * it cannot be added without quite a few hacks. Since this
+ * controller does not have any input type GPIOs, pretend that
+ * the interrupt pin is unconnected.
+ */
+ //interrupt-parent = <&tca6424a>;
+ //interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ //interrupt-controller;
+ //#interrupt-cells = <2>;
+
+ reset-gpios = <&tca6424a 9 GPIO_ACTIVE_LOW>;
+
+ gpio-line-names = "ACM1_EN", "ACM1_CL0", "ACM1_CL1", "ACM1_CL2",
+ "", "ACM2_EN", "ACM2_CL0", "ACM2_CL1",
+ "ACM2_CL2", "", "", "",
+ "", "", "", "";
+ };
+};
+
+&i2c5 {
+ mpl3115a2: pressure-sensor@60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+
+ vcc-supply = <®_3v3_acm>;
+
+ /* The MPL3115 binding does not yet support interrupts */
+ //interrupt-parent = <&tca6424a>;
+ //interrupts = <22 IRQ_TYPE_EDGE_RISING 23 IRQ_TYPE_EDGE_RISING>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/imx6dl-qmx6.dtsi
new file mode 100644
index 000000000000..575dad47bf72
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-qmx6.dtsi
@@ -0,0 +1,624 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for i.MX6DL based congatec QMX6
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+// Copyright 2016 congatec AG
+
+#include "imx6dl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
+
+/ {
+ memory@10000000 {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
+ i2c-parent = <&i2c2>;
+
+ i2c5: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c6: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio3 19 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst,sst25vf032b", "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ partition@0 {
+ label = "bootloader";
+ reg = <0x0000000 0x100000>;
+ };
+
+ partition@100000 {
+ label = "user";
+ reg = <0x0100000 0x2fc000>;
+ };
+
+ partition@3fc000 {
+ label = "reserved";
+ reg = <0x03fc000 0x4000>;
+ read-only;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>;
+ phy-mode = "rgmii-id";
+ phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ fsl,magic-packet;
+ phy-handle = <&phy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@6 {
+ reg = <6>;
+ qca,clk-out-frequency = <125000000>;
+ };
+ };
+};
+
+&i2c6 {
+ pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /*
+ * keep VGEN3, VGEN4 and VGEN5 enabled in order to
+ * maintain backward compatibility with hw-rev. A.0
+ */
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ /* supply voltage for eMMC */
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&pcie {
+ reset-gpio = <&gpio1 20 0>;
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+
+ audmux_ssi1 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
+ fsl,port-config = <
+ (IMX_AUDMUX_V2_PTCR_TFSDIR |
+ IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) |
+ IMX_AUDMUX_V2_PTCR_TCLKDIR |
+ IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) |
+ IMX_AUDMUX_V2_PTCR_SYN)
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6)
+ >;
+ };
+
+ audmux_aud6 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT6>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
+ >;
+ };
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+ <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ status = "okay";
+
+ rtc: m41t62@68 {
+ compatible = "st,m41t62";
+ reg = <0x68>;
+
+ rtc_sqw: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
+
+&clks {
+ clocks = <&rtc_sqw>;
+ clock-names = "ckil";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+};
+
+®_arm {
+ vin-supply = <&sw1a_reg>;
+};
+
+®_pu {
+ vin-supply = <&sw1c_reg>;
+};
+
+®_soc {
+ vin-supply = <&sw1c_reg>;
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usdhc2 {
+ /* MicroSD card slot */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&usdhc3 {
+ /* eMMC module */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ non-removable;
+ bus-width = <8>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&usbh1 {
+ /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ qmx6mux: imx6qdl-qmx6 {
+ };
+};
+
+&qmx6mux {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */
+ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */
+ >;
+ };
+
+ /* Watchdog output signal */
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
+ >;
+ };
+
+ pinctrl_q7_hda_rst: hdarstgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */
+ >;
+ };
+
+ pinctrl_q7_backlight_enable: blengrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */
+ >;
+ };
+
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */
+ MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 /* Q7[59] HDA_SYNC */
+ MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 /* Q7[65] HDA_SDI */
+ MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 /* Q7[63] HDA_BITCLK */
+ >;
+ };
+
+ /* SPI bus does not leave System on Module */
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
+ >;
+ };
+
+ /* PHY is on System on Module, Q7[3-15] have Ethernet lines */
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ >;
+ };
+
+ /* RGMII Phy Reset */
+ pinctrl_phy_reset: phyrstgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */
+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */
+ >;
+ };
+
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */
+ >;
+ };
+
+ /* Debug connector on Q7 module */
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */
+ >;
+ };
+
+ /* µSD card slot on Q7 module */
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */
+ >;
+ };
+
+ /* eMMC module on Q7 module */
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */
+ >;
+ };
+
+ pinctrl_q7_slp_btn: q7slpbtngrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */
+ >;
+ };
+
+ pinctrl_q7_sdio_pwr: q7sdiopwrgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */
+ >;
+ };
+
+ pinctrl_q7_gpio0: q7gpio0grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */
+ >;
+ };
+
+ pinctrl_q7_gpio1: q7gpio1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */
+ >;
+ };
+
+ pinctrl_q7_gpio2: q7gpio2grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */
+ >;
+ };
+
+ pinctrl_q7_gpio3: q7gpio3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */
+ >;
+ };
+
+ pinctrl_q7_gpio4: q7gpio4grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */
+ >;
+ };
+
+ pinctrl_q7_gpio5: q7gpio5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */
+ >;
+ };
+
+ pinctrl_q7_gpio6: q7gpio6grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */
+ >;
+ };
+
+ pinctrl_q7_gpio7: q7gpio7grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */
+ >;
+ };
+
+ pinctrl_q7_lcd_power: lcdpwrgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */
+ >;
+ };
+
+ pinctrl_q7_spi_cs1: spics1grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */
+ >;
+ };
+};
--
2.30.2
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCHv2 5/5] ARM: dts: imx6: Add GE B1x5v2
2021-04-28 22:29 ` [PATCHv2 5/5] ARM: dts: imx6: Add GE B1x5v2 Sebastian Reichel
@ 2021-05-22 14:04 ` Shawn Guo
0 siblings, 0 replies; 13+ messages in thread
From: Shawn Guo @ 2021-05-22 14:04 UTC (permalink / raw)
To: Sebastian Reichel
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, Saravana Kannan,
devicetree, David Airlie, Sascha Hauer, linux-kernel, dri-devel,
Rob Herring, linux-mtd, NXP Linux Team, Pengutronix Kernel Team,
Miquel Raynal, kernel, linux-arm-kernel
On Thu, Apr 29, 2021 at 12:29:53AM +0200, Sebastian Reichel wrote:
> This adds device tree files for the General Electric Healthcare
> (GEHC) B1x5v2 series. All models make use of Congatec's QMX6 module,
> which is described in its own device tree include, so that it can
> also be used by other boards.
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> arch/arm/boot/dts/Makefile | 5 +
> arch/arm/boot/dts/imx6dl-b105pv2.dts | 35 ++
> arch/arm/boot/dts/imx6dl-b105v2.dts | 35 ++
> arch/arm/boot/dts/imx6dl-b125pv2.dts | 33 ++
> arch/arm/boot/dts/imx6dl-b125v2.dts | 33 ++
> arch/arm/boot/dts/imx6dl-b155v2.dts | 36 ++
> arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi | 434 ++++++++++++++++++
> arch/arm/boot/dts/imx6dl-b1x5v2.dtsi | 61 +++
> arch/arm/boot/dts/imx6dl-qmx6.dtsi | 624 ++++++++++++++++++++++++++
> 9 files changed, 1296 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6dl-b105pv2.dts
> create mode 100644 arch/arm/boot/dts/imx6dl-b105v2.dts
> create mode 100644 arch/arm/boot/dts/imx6dl-b125pv2.dts
> create mode 100644 arch/arm/boot/dts/imx6dl-b125v2.dts
> create mode 100644 arch/arm/boot/dts/imx6dl-b155v2.dts
> create mode 100644 arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi
> create mode 100644 arch/arm/boot/dts/imx6dl-b1x5v2.dtsi
> create mode 100644 arch/arm/boot/dts/imx6dl-qmx6.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f8f09c5066e7..811f22ed1e37 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -515,6 +515,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> imx6q-dms-ba16.dtb \
> imx6q-emcon-avari.dtb \
> imx6q-evi.dtb \
> + imx6dl-b105v2.dtb \
> + imx6dl-b105pv2.dtb \
'p' goes before 'v'.
> + imx6dl-b125v2.dtb \
> + imx6dl-b125pv2.dtb \
> + imx6dl-b155v2.dtb \
> imx6q-gk802.dtb \
> imx6q-gw51xx.dtb \
> imx6q-gw52xx.dtb \
> diff --git a/arch/arm/boot/dts/imx6dl-b105pv2.dts b/arch/arm/boot/dts/imx6dl-b105pv2.dts
> new file mode 100644
> index 000000000000..0d5be2f9471f
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-b105pv2.dts
> @@ -0,0 +1,35 @@
> +// SPDX-License-Identifier: GPL-2.0 or MIT
> +//
> +// Device Tree Source for General Electric B105Pv2
> +//
> +// Copyright 2018-2021 General Electric Company
> +// Copyright 2018-2021 Collabora
> +
> +/dts-v1/;
> +#include "imx6dl-b1x5pv2.dtsi"
> +
> +/ {
> + model = "General Electric B105Pv2";
> + compatible = "ge,imx6dl-b105pv2", "congatec,qmx6", "fsl,imx6dl";
> +
> + panel {
> + compatible = "auo,g101evn010";
> + status = "okay";
Unneeded okay status.
> + };
> +};
> +
> +&i2c3 {
> + touchscreen@41 {
> + reg = <0x41>;
We generally start property list with 'compatible'.
> + compatible = "ilitek,ili251x";
> +
In general, we do not use newline in middle of property list.
> + pinctrl-names = "default";
> + pinctrl-0 =<&pinctrl_q7_gpio0>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>;
> +
> + touchscreen-size-x = <1280>;
> + touchscreen-size-y = <800>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6dl-b105v2.dts b/arch/arm/boot/dts/imx6dl-b105v2.dts
> new file mode 100644
> index 000000000000..72a085348304
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-b105v2.dts
> @@ -0,0 +1,35 @@
> +// SPDX-License-Identifier: GPL-2.0 or MIT
> +//
> +// Device Tree Source for General Electric B105v2
> +//
> +// Copyright 2018-2021 General Electric Company
> +// Copyright 2018-2021 Collabora
> +
> +/dts-v1/;
> +#include "imx6dl-b1x5v2.dtsi"
> +
> +/ {
> + model = "General Electric B105v2";
> + compatible = "ge,imx6dl-b105v2", "congatec,qmx6", "fsl,imx6dl";
> +
> + panel {
> + compatible = "auo,g101evn010";
> + status = "okay";
> + };
> +};
> +
> +&i2c3 {
> + touchscreen@41 {
> + reg = <0x41>;
> + compatible = "ilitek,ili251x";
> +
> + pinctrl-names = "default";
> + pinctrl-0 =<&pinctrl_q7_gpio0>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>;
> +
> + touchscreen-size-x = <1280>;
> + touchscreen-size-y = <800>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6dl-b125pv2.dts b/arch/arm/boot/dts/imx6dl-b125pv2.dts
> new file mode 100644
> index 000000000000..8fd6c8ed6750
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-b125pv2.dts
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0 or MIT
> +//
> +// Device Tree Source for General Electric B125Pv2
> +//
> +// Copyright 2018-2021 General Electric Company
> +// Copyright 2018-2021 Collabora
> +
> +/dts-v1/;
> +#include "imx6dl-b1x5pv2.dtsi"
> +
> +/ {
> + model = "General Electric B125Pv2";
> + compatible = "ge,imx6dl-b125pv2", "congatec,qmx6", "fsl,imx6dl";
> +
> + panel {
> + compatible = "auo,g121ean01";
> + status = "okay";
> + };
> +};
> +
> +&i2c3 {
> + touchscreen@2a {
> + reg = <0x2a>;
> + compatible = "eeti,exc80h60";
> +
> + pinctrl-names = "default";
> + pinctrl-0 =<&pinctrl_q7_gpio0>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
> +
> + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6dl-b125v2.dts b/arch/arm/boot/dts/imx6dl-b125v2.dts
> new file mode 100644
> index 000000000000..eb26ffde9f72
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-b125v2.dts
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0 or MIT
> +//
> +// Device Tree Source for General Electric B125v2
> +//
> +// Copyright 2018-2021 General Electric Company
> +// Copyright 2018-2021 Collabora
> +
> +/dts-v1/;
> +#include "imx6dl-b1x5v2.dtsi"
> +
> +/ {
> + model = "General Electric B125v2";
> + compatible = "ge,imx6dl-b125v2", "congatec,qmx6", "fsl,imx6dl";
> +
> + panel {
> + compatible = "auo,g121ean01";
> + status = "okay";
> + };
> +};
> +
> +&i2c3 {
> + touchscreen@2a {
> + reg = <0x2a>;
> + compatible = "eeti,exc80h60";
> +
> + pinctrl-names = "default";
> + pinctrl-0 =<&pinctrl_q7_gpio0>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
> +
> + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6dl-b155v2.dts b/arch/arm/boot/dts/imx6dl-b155v2.dts
> new file mode 100644
> index 000000000000..620cd6f9da82
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-b155v2.dts
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: GPL-2.0 or MIT
> +//
> +// Device Tree Source for General Electric B155v2
> +//
> +// Copyright 2018-2021 General Electric Company
> +// Copyright 2018-2021 Collabora
> +
> +/dts-v1/;
> +#include "imx6dl-b1x5v2.dtsi"
> +
> +/ {
> + model = "General Electric B155v2";
> + compatible = "ge,imx6dl-b155v2", "congatec,qmx6", "fsl,imx6dl";
> +
> + panel {
> + compatible = "auo,g156xtn01";
> + status = "okay";
> + };
> +};
> +
> +&i2c3 {
> + touchscreen@2a {
> + reg = <0x2a>;
> + compatible = "eeti,exc80h84";
> +
> + pinctrl-names = "default";
> + pinctrl-0 =<&pinctrl_q7_gpio0>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
> +
> + touchscreen-inverted-x;
> + touchscreen-inverted-y;
> +
> + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi
> new file mode 100644
> index 000000000000..1f9e66e1afc0
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi
> @@ -0,0 +1,434 @@
> +// SPDX-License-Identifier: GPL-2.0 or MIT
> +//
> +// Device Tree Source for General Electric B1x5v2
> +//
> +// Copyright 2018-2021 General Electric Company
> +// Copyright 2018-2021 Collabora
> +
> +#include <dt-bindings/input/input.h>
> +#include "imx6dl-qmx6.dtsi"
> +
> +/ {
> + chosen {
> + stdout-path = &uart3;
> + };
> +
> + /* Do not allow frequencies above 800MHz */
> + cpus {
> + cpu@0 {
> + operating-points = <
> + /* kHz uV */
> + 792000 1175000
> + 396000 1150000
> + >;
> + fsl,soc-operating-points = <
> + /* ARM kHz SOC-PU uV */
> + 792000 1175000
> + 396000 1175000
> + >;
> + };
> +
> + cpu@1 {
> + operating-points = <
> + /* kHz uV */
> + 792000 1175000
> + 396000 1150000
> + >;
> + fsl,soc-operating-points = <
> + /* ARM kHz SOC-PU uV */
> + 792000 1175000
> + 396000 1175000
> + >;
> + };
> + };
> +
> + reg_syspwr: regulator-12v {
> + compatible = "regulator-fixed";
> + regulator-name = "SYS_PWR";
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + regulator-always-on;
always-on is meaningless for a regulator that doesn't have on/off
control.
> + };
> +
> + reg_5v_pmc: regulator-5v-pmc {
> + compatible = "regulator-fixed";
> + regulator-name = "5V PMC";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + vin-supply = <®_syspwr>;
> + };
> +
> + reg_5v: regulator-5v {
> + compatible = "regulator-fixed";
> + regulator-name = "5V";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + vin-supply = <®_syspwr>;
> + };
> +
> + reg_3v3: regulator-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + vin-supply = <®_syspwr>;
> + };
> +
> + reg_5v0_audio: regulator-5v0-audio {
> + compatible = "regulator-fixed";
> + regulator-name = "5V0_AUDIO";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <®_5v>;
> +
Unneeded newline.
> + gpio = <&tca6424a 16 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
Ditto
> + /*
> + * This must be always-on for da7212, which has some not
> + * properly documented dependencies for it's speaker supply
> + * pin. The issue manifests as speaker volume being very low.
> + */
> + regulator-always-on;
> + };
> +
> +
> + reg_3v3_audio: regulator-3v3-audio {
> + compatible = "regulator-fixed";
> + regulator-name = "3V3_AUDIO";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <®_3v3>;
> +
> + pinctrl-0 = <&pinctrl_q7_hda_rst>;
> + pinctrl-names = "default";
> + gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_2v5_audio: regulator-2v5-audio {
> + compatible = "regulator-fixed";
> + regulator-name = "2V5_AUDIO";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-always-on;
> + vin-supply = <®_3v3_audio>;
> +
> + };
> +
> + reg_wlan: regulator-wlan {
> + compatible = "regulator-fixed";
> + regulator-name = "WLAN";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <®_3v3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_q7_sdio_pwr>;
> + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
> +
> + startup-delay-us = <70000>;
> + enable-active-high;
Put it right after GPIO_ACTIVE_HIGH line.
> + };
> +
> + reg_bl: regulator-backlight {
> + compatible = "regulator-fixed";
> + regulator-name = "LED_VCC";
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + vin-supply = <®_syspwr>;
> +
> + pinctrl-0 = <&pinctrl_q7_lcd_power>;
> + pinctrl-names = "default";
> + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_lcd: regulator-lcd {
> + compatible = "regulator-fixed";
> + regulator-name = "LCD_5V";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <®_5v>;
> + };
> +
> + usb_power: regulator-usb-power {
> + compatible = "regulator-fixed";
> + regulator-name = "USB POWER";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <®_5v>;
> + };
> +
> + charger: battery-charger {
> + compatible = "gpio-charger"; /* ti,bq24172 */
> +
> + charger-type = "mains";
> + gpios = <&tca6424a 3 GPIO_ACTIVE_LOW>;
> + charge-current-limit-gpios = <&tca6424a 11 GPIO_ACTIVE_HIGH>,
> + <&tca6424a 12 GPIO_ACTIVE_HIGH>;
> + charge-current-limit-mapping = <1300000 0x0>,
> + <700000 0x1>,
> + <0 0x2>;
> +
> + charge-status-gpios = <&tca6424a 6 GPIO_ACTIVE_HIGH>;
> + };
> +
> + poweroff {
> + compatible = "gpio-poweroff";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_q7_spi_cs1>;
> + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
> + };
> +
> + power-button-key {
> + compatible = "gpio-keys";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_q7_slp_btn>;
> +
> + power-button {
> + label = "power button";
> + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_POWER>;
> + };
> + };
> +
> + rotary-encoder-key {
> + compatible = "gpio-keys";
> +
> + rotary-encoder-press {
> + label = "rotary-encoder press";
> + gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>;
> + linux,code = <KEY_ENTER>;
> + linux,can-disable;
> + };
> + };
> +
> + rotary-encoder {
> + compatible = "rotary-encoder";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_q7_gpio2 &pinctrl_q7_gpio4>;
> + gpios = <&gpio4 26 GPIO_ACTIVE_LOW>, <&gpio1 0 GPIO_ACTIVE_LOW>;
> + rotary-encoder,relative-axis;
> + rotary-encoder,steps-per-period = <2>;
> + wakeup-source;
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>;
> +
> + alarm1 {
> + label = "alarm:red";
> + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
> + };
> +
> + alarm2 {
> + label = "alarm:yellow";
> + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
> + };
> +
> + alarm3 {
> + label = "alarm:blue";
> + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_q7_backlight_enable>;
> + power-supply = <®_bl>;
> + pwms = <&pwm4 0 5000000 0>;
> + brightness-levels = <0 255>;
> + num-interpolated-steps = <255>;
> + default-brightness-level = <179>;
> + enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
> + status = "okay";
Unneeded okay status.
> + };
> +
> + panel {
> + backlight = <&backlight>;
> + power-supply = <®_lcd>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&lvds0_out>;
> + };
> + };
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "audio-card";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&dailink_master>;
> + simple-audio-card,frame-master = <&dailink_master>;
> +
> + simple-audio-card,widgets = "Speaker", "Ext Spk";
> + simple-audio-card,audio-routing = "Ext Spk", "LINE";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&ssi1>;
> + };
> +
> + dailink_master: simple-audio-card,codec {
> + sound-dai = <&codec>;
> + };
> + };
> +
> + clk_ext_audio_codec: clock-codec {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12288000>;
> + };
> +};
> +
> +&i2c1 {
> + battery: battery@b {
> + compatible = "ti,bq20z65", "sbs,sbs-battery";
> + reg = <0x0b>;
> +
> + sbs,battery-detect-gpios = <&tca6424a 5 GPIO_ACTIVE_LOW>;
> + sbs,i2c-retry-count = <5>;
> +
> + power-supplies = <&charger>;
> + };
> +
> + codec: audio-codec@1a {
> + compatible = "dlg,da7212";
> + reg = <0x1a>;
> + #sound-dai-cells = <0>;
> + VDDA-supply = <®_2v5_audio>;
> + VDDSP-supply = <®_5v0_audio>;
> + VDDMIC-supply = <®_3v3_audio>;
> + VDDIO-supply = <®_3v3_audio>;
> + clocks = <&clk_ext_audio_codec>;
> + clock-names = "mclk";
> + };
> +};
> +
> +&i2c5 {
> + tmp75: temperature-sensor@48 {
> + compatible = "ti,tmp75";
> + reg = <0x48>;
> + vs-supply = <®_3v3>;
> + interrupt-parent = <&tca6424a>;
> + interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
> + };
> +
> + tca6424a: gpio-controller@22 {
> + compatible = "ti,tca6424";
> + reg = <0x22>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + vcc-supply = <®_3v3>;
> +
> + interrupt-parent = <&gpio7>;
> + interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_q7_gpio6>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + gpio-line-names = "GPIO_ROTOR#", "ACM_IO_INT", "TMP_SENSOR_IRQ", "AC_IN",
> + "TF_S", "BATT_T", "LED_INC_CHAR", "ACM1_OCF",
> + "ACM2_OCF", "ACM_IO_RST", "USB1_POWER_EN", "EGPIO_CC_CTL0",
> + "EGPIO_CC_CTL1", "12V_OEMNBP_EN", "CP2105_RST", "",
> + "SPEAKER_PA_EN", "ARM7_UPI_RESET", "ARM7_PWR_RST", "NURSE_CALL",
> + "MARKER_EN", "EGPIO_TOUCH_RST", "PRESSURE_INT1", "PRESSURE_INT2";
> +
> + };
> +};
> +
> +&fec {
> + status = "okay";
> +};
> +
> +&hdmi {
> + status = "okay";
> +};
> +
> +&audmux {
Sort them alphabetically.
> + status = "okay";
> +};
> +
> +&ssi1 {
> + fsl,mode = "i2s-slave";
> + status = "okay";
> +};
> +
> +&usbotg {
> + vbus-supply = <&usb_power>;
> + disable-over-current;
> + dr_mode = "host";
> + status = "okay";
> +
> + /*
> + * TPS2051BDGN fault-gpio is connected to Q7[86] USB_0_1_OC_N.
> + * On QMX6 this is not connceted to the i.MX6, but to the USB Hub
> + * from &usbh1. This means, that we cannot easily detect and handle
> + * over-current events. Fortunately the regulator limits the current
> + * automatically, so the hardware is still protected.
> + */
> +};
> +
> +&pwm4 {
> + status = "okay";
> +};
> +
> +&ldb {
> + status = "okay";
> +
> + lvds0: lvds-channel@0 {
> + status = "okay";
We generally end property list with 'status'.
> + fsl,data-mapping = "spwg";
> + fsl,data-width = <24>;
> +
> + port@4 {
> + reg = <4>;
Have a newline between property list and child node.
> + lvds0_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> + };
> +};
> +
> +&usdhc4 {
> + /* WiFi module */
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc4>;
> +
> + bus-width = <4>;
> + no-1-8-v;
> + non-removable;
> + wakeup-source;
> + keep-power-in-suspend;
> + cap-power-off-card;
> + max-frequency = <25000000>;
> + vmmc-supply = <®_wlan>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + wlcore: wlcore@2 {
> + compatible = "ti,wl1837";
> + reg = <2>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_q7_gpio7>;
> +
> + interrupt-parent = <&gpio4>;
> + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
> +
> + tcxo-clock-frequency = <26000000>;
> + };
> +
Unneeded newline.
> +};
> diff --git a/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi
> new file mode 100644
> index 000000000000..b4c6fbd802fb
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: GPL-2.0 or MIT
> +//
> +// Device Tree Source for General Electric B1x5v2
> +//
> +// Copyright 2018-2021 General Electric Company
> +// Copyright 2018-2021 Collabora
> +
> +#include <dt-bindings/input/input.h>
> +#include "imx6dl-b1x5pv2.dtsi"
> +
> +/ {
> + reg_3v3_acm: regulator-3v3-acm {
> + compatible = "regulator-fixed";
> + regulator-name = "3V3 ACM";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + vin-supply = <®_3v3>;
> + };
> +};
> +
> +&i2c1 {
> + tca6416: gpio-controller@21 {
> + compatible = "ti,tca6416";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + vcc-supply = <®_3v3_acm>;
> +
> + /*
> + * TCA6424 cannot handle low type interrupts at the moment and
> + * it cannot be added without quite a few hacks. Since this
> + * controller does not have any input type GPIOs, pretend that
> + * the interrupt pin is unconnected.
> + */
> + //interrupt-parent = <&tca6424a>;
> + //interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
> + //interrupt-controller;
> + //#interrupt-cells = <2>;
Maintain commented code out-of-tree please.
> +
> + reset-gpios = <&tca6424a 9 GPIO_ACTIVE_LOW>;
> +
> + gpio-line-names = "ACM1_EN", "ACM1_CL0", "ACM1_CL1", "ACM1_CL2",
> + "", "ACM2_EN", "ACM2_CL0", "ACM2_CL1",
> + "ACM2_CL2", "", "", "",
> + "", "", "", "";
> + };
> +};
> +
> +&i2c5 {
> + mpl3115a2: pressure-sensor@60 {
> + compatible = "fsl,mpl3115";
> + reg = <0x60>;
> +
> + vcc-supply = <®_3v3_acm>;
> +
> + /* The MPL3115 binding does not yet support interrupts */
> + //interrupt-parent = <&tca6424a>;
> + //interrupts = <22 IRQ_TYPE_EDGE_RISING 23 IRQ_TYPE_EDGE_RISING>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/imx6dl-qmx6.dtsi
> new file mode 100644
> index 000000000000..575dad47bf72
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-qmx6.dtsi
> @@ -0,0 +1,624 @@
> +// SPDX-License-Identifier: GPL-2.0 or MIT
> +//
> +// Device Tree Source for i.MX6DL based congatec QMX6
> +//
> +// Copyright 2018-2021 General Electric Company
> +// Copyright 2018-2021 Collabora
> +// Copyright 2016 congatec AG
> +
> +#include "imx6dl.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/sound/fsl-imx-audmux.h>
> +
> +/ {
> + memory@10000000 {
> + reg = <0x10000000 0x40000000>;
> + };
> +
> + reg_3p3v: 3p3v {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + i2cmux {
> + compatible = "i2c-mux-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
> + i2c-parent = <&i2c2>;
> +
> + i2c5: i2c@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c6: i2c@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +};
> +
> +&ecspi1 {
> + fsl,spi-num-chipselects = <1>;
Is it supported?
> + cs-gpios = <&gpio3 19 0>;
Use define for polarity.
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + status = "okay";
> +
> + flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "sst,sst25vf032b", "jedec,spi-nor";
> + spi-max-frequency = <20000000>;
> + reg = <0>;
> +
> + partition@0 {
> + label = "bootloader";
> + reg = <0x0000000 0x100000>;
> + };
> +
> + partition@100000 {
> + label = "user";
> + reg = <0x0100000 0x2fc000>;
> + };
> +
> + partition@3fc000 {
> + label = "reserved";
> + reg = <0x03fc000 0x4000>;
> + read-only;
> + };
> + };
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>;
> + phy-mode = "rgmii-id";
> + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
> + fsl,magic-packet;
> + phy-handle = <&phy0>;
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + phy0: ethernet-phy@6 {
> + reg = <6>;
> + qca,clk-out-frequency = <125000000>;
> + };
> + };
> +};
> +
> +&i2c6 {
> + pmic@8 {
> + compatible = "fsl,pfuze100";
> + reg = <0x08>;
> +
> + regulators {
> + sw1a_reg: sw1ab {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw1c_reg: sw1c {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw2_reg: sw2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3a_reg: sw3a {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3b_reg: sw3b {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw4_reg: sw4 {
> + regulator-min-microvolt = <675000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + swbst_reg: swbst {
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + };
> +
> + snvs_reg: vsnvs {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vref_reg: vrefddr {
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /*
> + * keep VGEN3, VGEN4 and VGEN5 enabled in order to
> + * maintain backward compatibility with hw-rev. A.0
> + */
> + vgen3_reg: vgen3 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen4_reg: vgen4 {
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-always-on;
> + };
> +
> + vgen5_reg: vgen5 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + /* supply voltage for eMMC */
> + vgen6_reg: vgen6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> +&pcie {
> + reset-gpio = <&gpio1 20 0>;
> +};
> +
> +&audmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_audmux>;
> +
> + audmux_ssi1 {
> + fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
> + fsl,port-config = <
> + (IMX_AUDMUX_V2_PTCR_TFSDIR |
> + IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) |
> + IMX_AUDMUX_V2_PTCR_TCLKDIR |
> + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) |
> + IMX_AUDMUX_V2_PTCR_SYN)
> + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6)
> + >;
> + };
> +
> + audmux_aud6 {
> + fsl,audmux-port = <MX51_AUDMUX_PORT6>;
> + fsl,port-config = <
> + IMX_AUDMUX_V2_PTCR_SYN
> + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
> + >;
> + };
> +};
> +
> +&clks {
> + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
> + <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
> + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
> + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + pinctrl-1 = <&pinctrl_i2c1_gpio>;
> + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + pinctrl-1 = <&pinctrl_i2c2_gpio>;
> + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +};
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + pinctrl-1 = <&pinctrl_i2c3_gpio>;
> + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +
> + status = "okay";
> +
> + rtc: m41t62@68 {
> + compatible = "st,m41t62";
> + reg = <0x68>;
> +
> + rtc_sqw: clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> + };
> +};
> +
> +&clks {
> + clocks = <&rtc_sqw>;
> + clock-names = "ckil";
> +};
> +
> +&pwm4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm4>;
> +};
> +
> +®_arm {
> + vin-supply = <&sw1a_reg>;
> +};
> +
> +®_pu {
> + vin-supply = <&sw1c_reg>;
> +};
> +
> +®_soc {
> + vin-supply = <&sw1c_reg>;
> +};
> +
> +&snvs_poweroff {
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + /* MicroSD card slot */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + keep-power-in-suspend;
> + wakeup-source;
> + vmmc-supply = <®_3p3v>;
> + status = "okay";
> +};
> +
> +&usdhc3 {
> + /* eMMC module */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + non-removable;
> + bus-width = <8>;
> + no-1-8-v;
> + keep-power-in-suspend;
> + wakeup-source;
> + vmmc-supply = <®_3p3v>;
> + status = "okay";
> +};
> +
> +&usbh1 {
> + /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */
> + vbus-supply = <®_5v>;
> + status = "okay";
> +};
> +
> +&usbotg {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg>;
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog>;
> +
> + qmx6mux: imx6qdl-qmx6 {
> + };
What is this for?
> +};
> +
> +&qmx6mux {
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */
> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */
> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */
> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */
> + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */
> + >;
> + };
> +
> + /* Watchdog output signal */
> + pinctrl_wdog: wdoggrp {
Sort pinctrl nodes alphabetically.
Shawn
> + fsl,pins = <
> + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
> + >;
> + };
> +
> + pinctrl_q7_hda_rst: hdarstgrp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */
> + >;
> + };
> +
> + pinctrl_q7_backlight_enable: blengrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */
> + >;
> + };
> +
> + pinctrl_audmux: audmuxgrp {
> + fsl,pins = <
> + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */
> + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 /* Q7[59] HDA_SYNC */
> + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 /* Q7[65] HDA_SDI */
> + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 /* Q7[63] HDA_BITCLK */
> + >;
> + };
> +
> + /* SPI bus does not leave System on Module */
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
> + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
> + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
> + >;
> + };
> +
> + /* PHY is on System on Module, Q7[3-15] have Ethernet lines */
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
> + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
> + >;
> + };
> +
> + /* RGMII Phy Reset */
> + pinctrl_phy_reset: phyrstgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */
> + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */
> + >;
> + };
> +
> + pinctrl_i2c1_gpio: i2c1gpiogrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */
> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */
> + >;
> + };
> +
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */
> + >;
> + };
> +
> + pinctrl_i2c2_gpio: i2c2gpiogrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */
> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */
> + >;
> + };
> +
> + pinctrl_i2c3_gpio: i2c3gpiogrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */
> + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */
> + >;
> + };
> +
> + pinctrl_pwm4: pwm4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */
> + >;
> + };
> +
> + /* Debug connector on Q7 module */
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */
> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */
> + >;
> + };
> +
> + /* µSD card slot on Q7 module */
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */
> + >;
> + };
> +
> + /* eMMC module on Q7 module */
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> + >;
> + };
> +
> +
> + pinctrl_usdhc4: usdhc4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */
> + >;
> + };
> +
> + pinctrl_q7_slp_btn: q7slpbtngrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */
> + >;
> + };
> +
> + pinctrl_q7_sdio_pwr: q7sdiopwrgrp {
> + fsl,pins = <
> + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */
> + >;
> + };
> +
> + pinctrl_q7_gpio0: q7gpio0grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */
> + >;
> + };
> +
> + pinctrl_q7_gpio1: q7gpio1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */
> + >;
> + };
> +
> + pinctrl_q7_gpio2: q7gpio2grp {
> + fsl,pins = <
> + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */
> + >;
> + };
> +
> + pinctrl_q7_gpio3: q7gpio3grp {
> + fsl,pins = <
> + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */
> + >;
> + };
> +
> + pinctrl_q7_gpio4: q7gpio4grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */
> + >;
> + };
> +
> + pinctrl_q7_gpio5: q7gpio5grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */
> + >;
> + };
> +
> + pinctrl_q7_gpio6: q7gpio6grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */
> + >;
> + };
> +
> + pinctrl_q7_gpio7: q7gpio7grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */
> + >;
> + };
> +
> + pinctrl_usbotg: usbotggrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */
> + >;
> + };
> +
> + pinctrl_q7_lcd_power: lcdpwrgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */
> + >;
> + };
> +
> + pinctrl_q7_spi_cs1: spics1grp {
> + fsl,pins = <
> + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */
> + >;
> + };
> +};
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: (subset) [PATCHv2 0/5] Support for GE B1x5v2 and B1x5Pv2
2021-04-28 22:29 [PATCHv2 0/5] Support for GE B1x5v2 and B1x5Pv2 Sebastian Reichel
` (4 preceding siblings ...)
2021-04-28 22:29 ` [PATCHv2 5/5] ARM: dts: imx6: Add GE B1x5v2 Sebastian Reichel
@ 2021-05-24 22:29 ` Alexandre Belloni
5 siblings, 0 replies; 13+ messages in thread
From: Alexandre Belloni @ 2021-05-24 22:29 UTC (permalink / raw)
To: Fabio Estevam, Shawn Guo, Pengutronix Kernel Team,
NXP Linux Team, Sascha Hauer, Sebastian Reichel, Philipp Zabel
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, Saravana Kannan,
devicetree, David Airlie, linux-kernel, dri-devel, Rob Herring,
linux-mtd, Miquel Raynal, kernel, linux-arm-kernel
On Thu, 29 Apr 2021 00:29:48 +0200, Sebastian Reichel wrote:
> This series adds support for another General Electric patient
> monitor series (similar to existing Bx50v3), which is based on
> i.MX6DL using Congatec's QMX6 module.
>
> The module uses an I2C RTC to provide the i.MX6 32768 Hz clock,
> so it's important to keep it enabled. Not doing so results in
> incorrect timings of watchdog and i.MX6 RTC. The bootloader
> enables the watchdog, so disabling the clock results in system
> reboot. [0]
>
> [...]
Applied, thanks!
[1/5] rtc: m41t80: add support for fixed clock
commit: f765e349c3e1f2e676ad4bd61197216b26976022
Best regards,
--
Alexandre Belloni <alexandre.belloni@bootlin.com>
^ permalink raw reply [flat|nested] 13+ messages in thread