From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Cc: daniel.vetter@intel.com
Subject: [PATCH 20/20] drm/i915/guc: Use guc_class instead of engine_class in fw interface
Date: Wed, 2 Jun 2021 22:16:30 -0700 [thread overview]
Message-ID: <20210603051630.2635-21-matthew.brost@intel.com> (raw)
In-Reply-To: <20210603051630.2635-1-matthew.brost@intel.com>
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
GuC has its own defines for the engine classes. They're currently
mapping 1:1 to the defines used by the driver, but there is no guarantee
this will continue in the future. Given that we've been caught off-guard
in the past by similar divergences, we can prepare for the changes by
introducing helper functions to convert from engine class to GuC class and
back again.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +++--
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 20 +++++++++-------
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 26 +++++++++++++++++++++
3 files changed, 42 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3f9a811eb02b..69281b5aba51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -265,6 +265,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
const struct engine_info *info = &intel_engines[id];
struct drm_i915_private *i915 = gt->i915;
struct intel_engine_cs *engine;
+ u8 guc_class;
BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
@@ -293,9 +294,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
engine->i915 = i915;
engine->gt = gt;
engine->uncore = gt->uncore;
- engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
engine->hw_id = info->hw_id;
- engine->guc_id = MAKE_GUC_ID(info->class, info->instance);
+ guc_class = engine_class_to_guc_class(info->class);
+ engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
+ engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
engine->irq_handler = nop_irq_handler;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 17526717368c..efdce309b6f1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -6,6 +6,7 @@
#include "gt/intel_gt.h"
#include "gt/intel_lrc.h"
#include "intel_guc_ads.h"
+#include "intel_guc_fwif.h"
#include "intel_uc.h"
#include "i915_drv.h"
@@ -104,7 +105,7 @@ static void guc_mapping_table_init(struct intel_gt *gt,
GUC_MAX_INSTANCES_PER_CLASS;
for_each_engine(engine, gt, id) {
- u8 guc_class = engine->class;
+ u8 guc_class = engine_class_to_guc_class(engine->class);
system_info->mapping_table[guc_class][engine->instance] =
engine->instance;
@@ -124,7 +125,7 @@ static void __guc_ads_init(struct intel_guc *guc)
struct __guc_ads_blob *blob = guc->ads_blob;
const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
u32 base;
- u8 engine_class;
+ u8 engine_class, guc_class;
/* GuC scheduling policies */
guc_policies_init(&blob->policies);
@@ -140,22 +141,25 @@ static void __guc_ads_init(struct intel_guc *guc)
for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
if (engine_class == OTHER_CLASS)
continue;
+
+ guc_class = engine_class_to_guc_class(engine_class);
+
/*
* TODO: Set context pointer to default state to allow
* GuC to re-init guilty contexts after internal reset.
*/
- blob->ads.golden_context_lrca[engine_class] = 0;
- blob->ads.eng_state_size[engine_class] =
+ blob->ads.golden_context_lrca[guc_class] = 0;
+ blob->ads.eng_state_size[guc_class] =
intel_engine_context_size(guc_to_gt(guc),
engine_class) -
skipped_size;
}
/* System info */
- blob->system_info.engine_enabled_masks[RENDER_CLASS] = 1;
- blob->system_info.engine_enabled_masks[COPY_ENGINE_CLASS] = 1;
- blob->system_info.engine_enabled_masks[VIDEO_DECODE_CLASS] = VDBOX_MASK(gt);
- blob->system_info.engine_enabled_masks[VIDEO_ENHANCEMENT_CLASS] = VEBOX_MASK(gt);
+ blob->system_info.engine_enabled_masks[GUC_RENDER_CLASS] = 1;
+ blob->system_info.engine_enabled_masks[GUC_BLITTER_CLASS] = 1;
+ blob->system_info.engine_enabled_masks[GUC_VIDEO_CLASS] = VDBOX_MASK(gt);
+ blob->system_info.engine_enabled_masks[GUC_VIDEOENHANCE_CLASS] = VEBOX_MASK(gt);
blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED] =
hweight8(gt->info.sseu.slice_mask);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 9bf35240e723..e9a9d85e2aa3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -9,6 +9,7 @@
#include <linux/bits.h>
#include <linux/compiler.h>
#include <linux/types.h>
+#include "gt/intel_engine_types.h"
#include "abi/guc_actions_abi.h"
#include "abi/guc_errors_abi.h"
@@ -32,6 +33,12 @@
#define GUC_VIDEO_ENGINE2 4
#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
+#define GUC_RENDER_CLASS 0
+#define GUC_VIDEO_CLASS 1
+#define GUC_VIDEOENHANCE_CLASS 2
+#define GUC_BLITTER_CLASS 3
+#define GUC_RESERVED_CLASS 4
+#define GUC_LAST_ENGINE_CLASS GUC_RESERVED_CLASS
#define GUC_MAX_ENGINE_CLASSES 16
#define GUC_MAX_INSTANCES_PER_CLASS 32
@@ -129,6 +136,25 @@
#define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \
(((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT)
+static inline u8 engine_class_to_guc_class(u8 class)
+{
+ BUILD_BUG_ON(GUC_RENDER_CLASS != RENDER_CLASS);
+ BUILD_BUG_ON(GUC_BLITTER_CLASS != COPY_ENGINE_CLASS);
+ BUILD_BUG_ON(GUC_VIDEO_CLASS != VIDEO_DECODE_CLASS);
+ BUILD_BUG_ON(GUC_VIDEOENHANCE_CLASS != VIDEO_ENHANCEMENT_CLASS);
+ GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
+
+ return class;
+}
+
+static inline u8 guc_class_to_engine_class(u8 guc_class)
+{
+ GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS);
+ GEM_BUG_ON(guc_class == GUC_RESERVED_CLASS);
+
+ return guc_class;
+}
+
/* Work item for submitting workloads into work queue of GuC. */
struct guc_wq_item {
u32 header;
--
2.28.0
next prev parent reply other threads:[~2021-06-03 4:59 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-03 5:16 [PATCH 00/20] GuC CTBs changes + a few misc patches Matthew Brost
2021-06-03 5:16 ` [PATCH 01/20] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost
2021-06-03 5:16 ` [PATCH 02/20] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost
2021-06-03 5:16 ` [PATCH 03/20] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost
2021-06-03 5:16 ` [PATCH 04/20] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost
2021-06-03 5:16 ` [PATCH 05/20] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost
2021-06-03 5:16 ` [PATCH 06/20] drm/i915/guc: Drop guc->interrupts.enabled Matthew Brost
2021-06-03 5:16 ` [PATCH 07/20] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost
2021-06-03 5:16 ` [PATCH 08/20] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost
2021-06-03 21:35 ` Daniel Vetter
2021-06-04 2:02 ` Matthew Brost
2021-06-04 8:11 ` Daniel Vetter
2021-06-03 5:16 ` [PATCH 09/20] drm/i915/guc: Only rely on own CTB size Matthew Brost
2021-06-03 5:16 ` [PATCH 10/20] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost
2021-06-03 5:16 ` [PATCH 11/20] drm/i915/guc: Replace CTB array with explicit members Matthew Brost
2021-06-03 7:25 ` kernel test robot
2021-06-03 21:37 ` [Intel-gfx] " Daniel Vetter
2021-06-03 22:44 ` [PATCH 1/2] " Matthew Brost
2021-06-03 22:44 ` [PATCH 2/2] drm/i915/guc: Update sizes of CTB buffers Matthew Brost
2021-06-03 23:04 ` [v3 PATCH 1/2] drm/i915/guc: Replace CTB array with explicit members Matthew Brost
2021-06-03 23:04 ` [v3 PATCH 2/2] drm/i915/guc: Update sizes of CTB buffers Matthew Brost
2021-06-04 8:20 ` Daniel Vetter
2021-06-04 8:49 ` Michal Wajdeczko
2021-06-03 5:16 ` [PATCH 12/20] " Matthew Brost
2021-06-03 5:16 ` [PATCH 13/20] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-06-04 8:33 ` [Intel-gfx] " Daniel Vetter
2021-06-04 18:35 ` Matthew Brost
2021-06-09 13:24 ` Daniel Vetter
2021-06-03 5:16 ` [PATCH 14/20] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost
2021-06-04 8:35 ` Daniel Vetter
2021-06-03 5:16 ` [PATCH 15/20] drm/i915/guc: Ensure H2G buffer updates visible before tail update Matthew Brost
2021-06-03 9:44 ` [Intel-gfx] " Michal Wajdeczko
2021-06-03 16:10 ` Matthew Brost
2021-06-04 8:39 ` Daniel Vetter
2021-06-03 5:16 ` [PATCH 16/20] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost
2021-06-03 5:16 ` [PATCH 17/20] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost
2021-06-03 5:16 ` [PATCH 18/20] drm/i915/guc: Always copy CT message to new allocation Matthew Brost
2021-06-03 5:16 ` [PATCH 19/20] drm/i915/guc: Early initialization of GuC send registers Matthew Brost
2021-06-03 5:16 ` Matthew Brost [this message]
2021-06-04 8:44 ` [PATCH 20/20] drm/i915/guc: Use guc_class instead of engine_class in fw interface Daniel Vetter
2021-06-04 18:12 ` Matthew Brost
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