From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Subject: [PATCH 09/33] drm/i915: Reset GPU immediately if submission is disabled
Date: Thu, 22 Jul 2021 16:54:02 -0700 [thread overview]
Message-ID: <20210722235426.31831-10-matthew.brost@intel.com> (raw)
In-Reply-To: <20210722235426.31831-1-matthew.brost@intel.com>
If submission is disabled by the backend for any reason, reset the GPU
immediately in the heartbeat code as the backend can't be reenabled
until the GPU is reset.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 63 +++++++++++++++----
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 4 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 9 +++
drivers/gpu/drm/i915/i915_scheduler.c | 6 ++
drivers/gpu/drm/i915/i915_scheduler.h | 6 ++
drivers/gpu/drm/i915/i915_scheduler_types.h | 5 ++
6 files changed, 80 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index b6a305e6a974..a8495364d906 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -70,12 +70,30 @@ static void show_heartbeat(const struct i915_request *rq,
{
struct drm_printer p = drm_debug_printer("heartbeat");
- intel_engine_dump(engine, &p,
- "%s heartbeat {seqno:%llx:%lld, prio:%d} not ticking\n",
- engine->name,
- rq->fence.context,
- rq->fence.seqno,
- rq->sched.attr.priority);
+ if (!rq) {
+ intel_engine_dump(engine, &p,
+ "%s heartbeat not ticking\n",
+ engine->name);
+ } else {
+ intel_engine_dump(engine, &p,
+ "%s heartbeat {seqno:%llx:%lld, prio:%d} not ticking\n",
+ engine->name,
+ rq->fence.context,
+ rq->fence.seqno,
+ rq->sched.attr.priority);
+ }
+}
+
+static void
+reset_engine(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ show_heartbeat(rq, engine);
+
+ intel_gt_handle_error(engine->gt, engine->mask,
+ I915_ERROR_CAPTURE,
+ "stopped heartbeat on %s",
+ engine->name);
}
static void heartbeat(struct work_struct *wrk)
@@ -102,6 +120,11 @@ static void heartbeat(struct work_struct *wrk)
if (intel_gt_is_wedged(engine->gt))
goto out;
+ if (i915_sched_engine_disabled(engine->sched_engine)) {
+ reset_engine(engine, engine->heartbeat.systole);
+ goto out;
+ }
+
if (engine->heartbeat.systole) {
long delay = READ_ONCE(engine->props.heartbeat_interval_ms);
@@ -139,13 +162,7 @@ static void heartbeat(struct work_struct *wrk)
engine->sched_engine->schedule(rq, &attr);
local_bh_enable();
} else {
- if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
- show_heartbeat(rq, engine);
-
- intel_gt_handle_error(engine->gt, engine->mask,
- I915_ERROR_CAPTURE,
- "stopped heartbeat on %s",
- engine->name);
+ reset_engine(engine, rq);
}
rq->emitted_jiffies = jiffies;
@@ -194,6 +211,26 @@ void intel_engine_park_heartbeat(struct intel_engine_cs *engine)
i915_request_put(fetch_and_zero(&engine->heartbeat.systole));
}
+void intel_gt_unpark_heartbeats(struct intel_gt *gt)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, gt, id)
+ if (intel_engine_pm_is_awake(engine))
+ intel_engine_unpark_heartbeat(engine);
+
+}
+
+void intel_gt_park_heartbeats(struct intel_gt *gt)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, gt, id)
+ intel_engine_park_heartbeat(engine);
+}
+
void intel_engine_init_heartbeat(struct intel_engine_cs *engine)
{
INIT_DELAYED_WORK(&engine->heartbeat.work, heartbeat);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
index a488ea3e84a3..5da6d809a87a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -7,6 +7,7 @@
#define INTEL_ENGINE_HEARTBEAT_H
struct intel_engine_cs;
+struct intel_gt;
void intel_engine_init_heartbeat(struct intel_engine_cs *engine);
@@ -16,6 +17,9 @@ int intel_engine_set_heartbeat(struct intel_engine_cs *engine,
void intel_engine_park_heartbeat(struct intel_engine_cs *engine);
void intel_engine_unpark_heartbeat(struct intel_engine_cs *engine);
+void intel_gt_park_heartbeats(struct intel_gt *gt);
+void intel_gt_unpark_heartbeats(struct intel_gt *gt);
+
int intel_engine_pulse(struct intel_engine_cs *engine);
int intel_engine_flush_barriers(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 227225a7917c..aef059b909d8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -10,6 +10,7 @@
#include "gt/intel_breadcrumbs.h"
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_irq.h"
#include "gt/intel_gt_pm.h"
@@ -603,6 +604,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
return;
}
+ intel_gt_park_heartbeats(guc_to_gt(guc));
disable_submission(guc);
guc->interrupts.disable(guc);
@@ -890,6 +892,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc)
atomic_set(&guc->outstanding_submission_g2h, 0);
enable_submission(guc);
+ intel_gt_unpark_heartbeats(guc_to_gt(guc));
}
/*
@@ -1865,6 +1868,11 @@ static int guc_resume(struct intel_engine_cs *engine)
return 0;
}
+static bool guc_sched_engine_disabled(struct i915_sched_engine *sched_engine)
+{
+ return !sched_engine->tasklet.callback;
+}
+
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = guc_submit_request;
@@ -2015,6 +2023,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
return -ENOMEM;
guc->sched_engine->schedule = i915_schedule;
+ guc->sched_engine->disabled = guc_sched_engine_disabled;
guc->sched_engine->private_data = guc;
guc->sched_engine->destroy = guc_sched_engine_destroy;
tasklet_setup(&guc->sched_engine->tasklet,
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index 2804fd5b660b..28dd887eb1be 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -440,6 +440,11 @@ static void default_destroy(struct kref *kref)
kfree(sched_engine);
}
+static bool default_disabled(struct i915_sched_engine *sched_engine)
+{
+ return false;
+}
+
struct i915_sched_engine *
i915_sched_engine_create(unsigned int subclass)
{
@@ -454,6 +459,7 @@ i915_sched_engine_create(unsigned int subclass)
sched_engine->queue = RB_ROOT_CACHED;
sched_engine->queue_priority_hint = INT_MIN;
sched_engine->destroy = default_destroy;
+ sched_engine->disabled = default_disabled;
INIT_LIST_HEAD(&sched_engine->requests);
INIT_LIST_HEAD(&sched_engine->hold);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index 3c9504e9f409..f4d9811ade5b 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -96,4 +96,10 @@ void i915_request_show_with_schedule(struct drm_printer *m,
const char *prefix,
int indent);
+static inline bool
+i915_sched_engine_disabled(struct i915_sched_engine *sched_engine)
+{
+ return sched_engine->disabled(sched_engine);
+}
+
#endif /* _I915_SCHEDULER_H_ */
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
index 00384e2c5273..eaef233e9080 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -168,6 +168,11 @@ struct i915_sched_engine {
*/
void (*destroy)(struct kref *kref);
+ /**
+ * @disabled: check if backend has disabled submission
+ */
+ bool (*disabled)(struct i915_sched_engine *sched_engine);
+
/**
* @kick_backend: kick backend after a request's priority has changed
*/
--
2.28.0
next prev parent reply other threads:[~2021-07-22 23:37 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-22 23:53 [PATCH 00/33] Remaining patches for basic GuC submission Matthew Brost
2021-07-22 23:53 ` [PATCH 01/33] drm/i915/guc: GuC virtual engines Matthew Brost
2021-07-24 0:47 ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-24 23:13 ` Matthew Brost
2021-07-26 15:56 ` Daniele Ceraolo Spurio
2021-07-22 23:53 ` [PATCH 02/33] drm/i915/guc: Make hangcheck work with " Matthew Brost
2021-07-22 23:53 ` [PATCH 03/33] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-07-22 23:53 ` [PATCH 04/33] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-07-22 23:53 ` [PATCH 05/33] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-07-22 23:53 ` [PATCH 06/33] drm/i915: Add i915_sched_engine destroy vfunc Matthew Brost
2021-07-22 23:54 ` [PATCH 07/33] drm/i915: Move active request tracking to a vfunc Matthew Brost
2021-07-22 23:54 ` [PATCH 08/33] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-07-26 23:09 ` [Intel-gfx] " John Harrison
2021-07-22 23:54 ` Matthew Brost [this message]
2021-07-22 23:54 ` [PATCH 10/33] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-07-22 23:54 ` [PATCH 11/33] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-07-22 23:54 ` [PATCH 12/33] drm/i915/guc: Handle context reset notification Matthew Brost
2021-07-22 23:54 ` [PATCH 13/33] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-07-22 23:54 ` [PATCH 14/33] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-07-22 23:54 ` [PATCH 15/33] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-07-22 23:54 ` [PATCH 16/33] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-07-22 23:54 ` [PATCH 17/33] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-07-22 23:54 ` [PATCH 18/33] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-07-22 23:54 ` [PATCH 19/33] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-07-22 23:54 ` [PATCH 20/33] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-07-22 23:54 ` [PATCH 21/33] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-07-22 23:54 ` [PATCH 22/33] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-07-22 23:54 ` [PATCH 23/33] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-07-22 23:54 ` [PATCH 24/33] drm/i915/guc: Implement banned contexts for GuC submission Matthew Brost
2021-07-22 23:54 ` [PATCH 25/33] drm/i915/guc: Support request cancellation Matthew Brost
2021-07-26 17:49 ` Daniele Ceraolo Spurio
2021-07-26 17:56 ` Matthew Brost
2021-07-22 23:54 ` [PATCH 26/33] drm/i915/selftest: Better error reporting from hangcheck selftest Matthew Brost
2021-07-22 23:54 ` [PATCH 27/33] drm/i915/selftest: Fix workarounds selftest for GuC submission Matthew Brost
2021-07-22 23:54 ` [PATCH 28/33] drm/i915/selftest: Fix MOCS " Matthew Brost
2021-07-22 23:54 ` [PATCH 29/33] drm/i915/selftest: Increase some timeouts in live_requests Matthew Brost
2021-07-22 23:54 ` [PATCH 30/33] drm/i915/selftest: Fix hangcheck self test for GuC submission Matthew Brost
2021-07-22 23:54 ` [PATCH 31/33] drm/i915/selftest: Bump selftest timeouts for hangcheck Matthew Brost
2021-07-22 23:54 ` [PATCH 32/33] drm/i915/guc: Implement GuC priority management Matthew Brost
2021-07-24 0:54 ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-22 23:54 ` [PATCH 33/33] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-07-27 0:23 [PATCH 00/33] Remaining patches for basic GuC submission Matthew Brost
2021-07-27 0:23 ` [PATCH 09/33] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
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